SystemVerilog Unions #560
SystemVerilog Unions #560
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| if(type.id() == ID_union) | ||
| { | ||
| // find the biggest | ||
| mp_integer max = 0; | ||
| for(auto &component : to_verilog_union_type(type).components()) | ||
| max = std::max(max, get_width(component.type())); | ||
| return max; | ||
| } |
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union_typet::find_widest_union_component should do the trick.
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That uses C widths, in bytes, whereas we'd need Verilog widths, in bits. That method would need to take a functor that computes the width of a field.
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It uses pointer_offset_bits, so should be bits. Might, however, still be a problem that pointer_offset_bits doesn't know all the Verilog types? If so, is ID_union the right type at all?
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If I make it verilog_union, then the flattener would need to learn about it.
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So perhaps the better route is to produce an implementation that is similar to union_typet::find_widest_union_component to have almost-the-same-code twice in the Verilog front-end?
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I'll see of those two pieces of code can become one.
| else if(type.id() == ID_union) | ||
| { | ||
| auto &union_type = to_verilog_union_type(type); | ||
| mp_integer max = 0; | ||
| for(auto &component : union_type.components()) | ||
| { | ||
| auto component_bits_opt = bits_rec(component.type()); | ||
| if(!component_bits_opt.has_value()) | ||
| return component_bits_opt.value(); | ||
| max = std::max(max, component_bits_opt.value()); | ||
| } | ||
| return max; | ||
| } |
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Should use union_typet::find_widest_union_component.
| if(type.id() == ID_union) | ||
| { | ||
| // find the biggest | ||
| mp_integer max = 0; | ||
| for(auto &component : to_verilog_union_type(type).components()) | ||
| max = std::max(max, get_width(component.type())); | ||
| return max; | ||
| } |
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So perhaps the better route is to produce an implementation that is similar to union_typet::find_widest_union_component to have almost-the-same-code twice in the Verilog front-end?
This replaces verilog_typecheck_exprt::bits_rec by an invocation to verilog_typecheck_baset::get_width_opt.
This adds basic support for SystemVerilog unions.
This adds basic support for SystemVerilog unions.