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KNOWNBUG tests for Verilog logical and case equality.
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KNOWNBUG
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equality1.v
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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Missing Verilog case equality implementation.
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module main;
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always assert property01: (10==10)===1;
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always assert property02: (10==20)===0;
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always assert property03: (10!=20)===1;
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always assert property04: (10==20)===0;
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always assert property05: ('bx==10)==='bx;
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always assert property06: ('bz==20)==='bx;
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always assert property07: ('bx!=10)==='bx;
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always assert property08: ('bz!=20)==='bx;
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always assert property09: ('sb1=='b11)===0; // zero extension
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always assert property10: ('sb1=='sb11)===1; // sign extension
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endmodule
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KNOWNBUG
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equality2.v
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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Missing Verilog case equality implementation.
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module main;
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always assert property01: (10===10)==1;
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always assert property02: (10===20)==0;
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always assert property03: (10!==10)==1;
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always assert property04: (10!==20)==0;
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always assert property05: ('bx==='bx)==1;
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always assert property06: ('bz==='bz)==1;
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always assert property07: ('bx==='bz)==0;
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always assert property08: ('bx==='b1)==0;
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always assert property09: ('bz==='b1)==0;
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always assert property10: ('b1==='b01)==1; // zero extension
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always assert property11: ('b1==='sb11)==0; // zero extension
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always assert property12: ('sb1==='sb11)==1; // sign extension
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endmodule

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