File tree Expand file tree Collapse file tree 4 files changed +48
-0
lines changed
regression/verilog/expressions Expand file tree Collapse file tree 4 files changed +48
-0
lines changed Original file line number Diff line number Diff line change
1
+ KNOWNBUG
2
+ equality1.v
3
+ --bound 0
4
+ ^EXIT=0$
5
+ ^SIGNAL=0$
6
+ --
7
+ ^warning: ignoring
8
+ --
9
+ Missing Verilog case equality implementation.
Original file line number Diff line number Diff line change
1
+ module main ;
2
+
3
+ always assert property01: (10 == 10 )=== 1 ;
4
+ always assert property02: (10 == 20 )=== 0 ;
5
+ always assert property03: (10 != 20 )=== 1 ;
6
+ always assert property04: (10 == 20 )=== 0 ;
7
+ always assert property05: ('bx== 10 )=== 'bx;
8
+ always assert property06: ('bz== 20 )=== 'bx;
9
+ always assert property07: ('bx!= 10 )=== 'bx;
10
+ always assert property08: ('bz!= 20 )=== 'bx;
11
+ always assert property09: ('sb1== 'b11)=== 0 ; // zero extension
12
+ always assert property10: ('sb1== 'sb11)=== 1 ; // sign extension
13
+
14
+ endmodule
Original file line number Diff line number Diff line change
1
+ KNOWNBUG
2
+ equality2.v
3
+ --bound 0
4
+ ^EXIT=0$
5
+ ^SIGNAL=0$
6
+ --
7
+ ^warning: ignoring
8
+ --
9
+ Missing Verilog case equality implementation.
Original file line number Diff line number Diff line change
1
+ module main ;
2
+
3
+ always assert property01: (10 === 10 )== 1 ;
4
+ always assert property02: (10 === 20 )== 0 ;
5
+ always assert property03: (10 !== 10 )== 1 ;
6
+ always assert property04: (10 !== 20 )== 0 ;
7
+ always assert property05: ('bx=== 'bx)== 1 ;
8
+ always assert property06: ('bz=== 'bz)== 1 ;
9
+ always assert property07: ('bx=== 'bz)== 0 ;
10
+ always assert property08: ('bx=== 'b1)== 0 ;
11
+ always assert property09: ('bz=== 'b1)== 0 ;
12
+ always assert property10: ('b1=== 'b01)== 1 ; // zero extension
13
+ always assert property11: ('b1=== 'sb11)== 0 ; // zero extension
14
+ always assert property12: ('sb1=== 'sb11)== 1 ; // sign extension
15
+
16
+ endmodule
You can’t perform that action at this time.
0 commit comments