KNOWNBUG test for Verilog logical and case equality.

Author: kroening

regression/verilog/expressions/equality1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+equality1.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+Missing Verilog case equality implementation.

regression/verilog/expressions/equality1.v

@@ -0,0 +1,12 @@
+module main;
+
+  always assert property1: (10==10)===1;
+  always assert property2: (10==20)===0;
+  always assert property3: (10!=20)===1;
+  always assert property4: (10==20)===0;
+  always assert property5: ('bx==10)==='bx;
+  always assert property6: ('bz==20)==='bx;
+  always assert property7: ('bx!=10)==='bx;
+  always assert property8: ('bz!=20)==='bx;
+
+endmodule