[vm] Remove ARMv6 related code

This also allows unaligned access, since it's mandatory for ARMv7 (we
already take advantage of it for ARMv8).

Issue #42069

Change-Id: I0bd61a930e61dea330ab21fd187fe64b057ca28e
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/152322
Reviewed-by: Siva Annamalai <[email protected]>
Reviewed-by: Vyacheslav Egorov <[email protected]>
Commit-Queue: Martin Kustermann <[email protected]>

Author: mkustermann

runtime/BUILD.gn

@@ -101,9 +101,6 @@ config("dart_arch_config") {
 
   if (dart_target_arch == "arm") {
     defines += [ "TARGET_ARCH_ARM" ]
-  } else if (dart_target_arch == "armv6") {
-    defines += [ "TARGET_ARCH_ARM" ]
-    defines += [ "TARGET_ARCH_ARM_6" ]
   } else if (dart_target_arch == "arm64") {
     defines += [ "TARGET_ARCH_ARM64" ]
   } else if (dart_target_arch == "x64") {

runtime/tests/vm/vm.status

@@ -357,7 +357,7 @@ cc/GenKernelKernelReadAllBytecode: SkipByDesign # No interpreter support.
 # On the simluator stack traces produced by the Profiler do not match
 # up with the real Dart stack trace and hence we don't get correct
 # symbol names.
-[ $arch == simarm || $arch == simarm64 || $arch == simarmv6 ]
+[ $arch == simarm || $arch == simarm64 ]
 cc/LargeMap: SkipByDesign
 cc/Profiler_AllocationSampleTest: SkipByDesign
 cc/Profiler_ArrayAllocation: SkipByDesign

runtime/vm/compiler/assembler/assembler_arm.cc

@@ -364,13 +364,8 @@ void Assembler::mls(Register rd,
                     Register ra,
                     Condition cond) {
   // rd <- ra - rn * rm.
-  if (TargetCPUFeatures::arm_version() == ARMv7) {
-    // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
-    EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
-  } else {
-    mul(IP, rn, rm, cond);
-    sub(rd, ra, Operand(IP), cond);
-  }
+  // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
+  EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
 }
 
 void Assembler::smull(Register rd_lo,
@@ -978,9 +973,6 @@ void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
 }
 
 bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
-  if (TargetCPUFeatures::arm_version() != ARMv7) {
-    return false;
-  }
   uint32_t imm32 = bit_cast<uint32_t, float>(s_imm);
   if (((imm32 & ((1 << 19) - 1)) == 0) &&
       ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) ||
@@ -995,9 +987,6 @@ bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
 }
 
 bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
-  if (TargetCPUFeatures::arm_version() != ARMv7) {
-    return false;
-  }
   uint64_t imm64 = bit_cast<uint64_t, double>(d_imm);
   if (((imm64 & ((1LL << 48) - 1)) == 0) &&
       ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) ||
@@ -2074,69 +2063,15 @@ static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
   return offset;
 }
 
-static int32_t DecodeARMv6LoadImmediate(int32_t mov,
-                                        int32_t or1,
-                                        int32_t or2,
-                                        int32_t or3) {
-  int32_t offset = 0;
-  offset |= (mov & 0xff) << 24;
-  offset |= (or1 & 0xff) << 16;
-  offset |= (or2 & 0xff) << 8;
-  offset |= (or3 & 0xff);
-  return offset;
-}
-
 class PatchFarBranch : public AssemblerFixup {
  public:
   PatchFarBranch() {}
 
   void Process(const MemoryRegion& region, intptr_t position) {
-    const ARMVersion version = TargetCPUFeatures::arm_version();
-    if (version == ARMv6) {
-      ProcessARMv6(region, position);
-    } else {
-      ASSERT(version == ARMv7);
-      ProcessARMv7(region, position);
-    }
+    ProcessARMv7(region, position);
   }
 
  private:
-  void ProcessARMv6(const MemoryRegion& region, intptr_t position) {
-    const int32_t mov = region.Load<int32_t>(position);
-    const int32_t or1 = region.Load<int32_t>(position + 1 * Instr::kInstrSize);
-    const int32_t or2 = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
-    const int32_t or3 = region.Load<int32_t>(position + 3 * Instr::kInstrSize);
-    const int32_t bx = region.Load<int32_t>(position + 4 * Instr::kInstrSize);
-
-    if (((mov & 0xffffff00) == 0xe3a0c400) &&  // mov IP, (byte3 rot 4)
-        ((or1 & 0xffffff00) == 0xe38cc800) &&  // orr IP, IP, (byte2 rot 8)
-        ((or2 & 0xffffff00) == 0xe38ccc00) &&  // orr IP, IP, (byte1 rot 12)
-        ((or3 & 0xffffff00) == 0xe38cc000)) {  // orr IP, IP, byte0
-      const int32_t offset = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
-      const int32_t dest = region.start() + offset;
-      const int32_t dest0 = (dest & 0x000000ff);
-      const int32_t dest1 = (dest & 0x0000ff00) >> 8;
-      const int32_t dest2 = (dest & 0x00ff0000) >> 16;
-      const int32_t dest3 = (dest & 0xff000000) >> 24;
-      const int32_t patched_mov = 0xe3a0c400 | dest3;
-      const int32_t patched_or1 = 0xe38cc800 | dest2;
-      const int32_t patched_or2 = 0xe38ccc00 | dest1;
-      const int32_t patched_or3 = 0xe38cc000 | dest0;
-
-      region.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
-      region.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
-      region.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
-      region.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
-      return;
-    }
-
-    // If the offset loading instructions aren't there, we must have replaced
-    // the far branch with a near one, and so these instructions
-    // should be NOPs.
-    ASSERT((or1 == Instr::kNopInstruction) && (or2 == Instr::kNopInstruction) &&
-           (or3 == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
-  }
-
   void ProcessARMv7(const MemoryRegion& region, intptr_t position) {
     const int32_t movw = region.Load<int32_t>(position);
     const int32_t movt = region.Load<int32_t>(position + Instr::kInstrSize);
@@ -2198,85 +2133,6 @@ void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
   }
 }
 
-void Assembler::BindARMv6(Label* label) {
-  ASSERT(!label->IsBound());
-  intptr_t bound_pc = buffer_.Size();
-  while (label->IsLinked()) {
-    const int32_t position = label->Position();
-    int32_t dest = bound_pc - position;
-    if (use_far_branches() && !CanEncodeBranchDistance(dest)) {
-      // Far branches are enabled and we can't encode the branch offset.
-
-      // Grab instructions that load the offset.
-      const int32_t mov = buffer_.Load<int32_t>(position);
-      const int32_t or1 =
-          buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
-      const int32_t or2 =
-          buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
-      const int32_t or3 =
-          buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
-
-      // Change from relative to the branch to relative to the assembler
-      // buffer.
-      dest = buffer_.Size();
-      const int32_t dest0 = (dest & 0x000000ff);
-      const int32_t dest1 = (dest & 0x0000ff00) >> 8;
-      const int32_t dest2 = (dest & 0x00ff0000) >> 16;
-      const int32_t dest3 = (dest & 0xff000000) >> 24;
-      const int32_t patched_mov = 0xe3a0c400 | dest3;
-      const int32_t patched_or1 = 0xe38cc800 | dest2;
-      const int32_t patched_or2 = 0xe38ccc00 | dest1;
-      const int32_t patched_or3 = 0xe38cc000 | dest0;
-
-      // Rewrite the instructions.
-      buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
-      buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
-      buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
-      buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
-      label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
-    } else if (use_far_branches() && CanEncodeBranchDistance(dest)) {
-      // Grab instructions that load the offset, and the branch.
-      const int32_t mov = buffer_.Load<int32_t>(position);
-      const int32_t or1 =
-          buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
-      const int32_t or2 =
-          buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
-      const int32_t or3 =
-          buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
-      const int32_t branch =
-          buffer_.Load<int32_t>(position + 4 * Instr::kInstrSize);
-
-      // Grab the branch condition, and encode the link bit.
-      const int32_t cond = branch & 0xf0000000;
-      const int32_t link = (branch & 0x20) << 19;
-
-      // Encode the branch and the offset.
-      const int32_t new_branch = cond | link | 0x0a000000;
-      const int32_t encoded = EncodeBranchOffset(dest, new_branch);
-
-      // Write the encoded branch instruction followed by two nops.
-      buffer_.Store<int32_t>(position, encoded);
-      buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
-                             Instr::kNopInstruction);
-      buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
-                             Instr::kNopInstruction);
-      buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize,
-                             Instr::kNopInstruction);
-      buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize,
-                             Instr::kNopInstruction);
-
-      label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
-    } else {
-      BailoutIfInvalidBranchOffset(dest);
-      int32_t next = buffer_.Load<int32_t>(position);
-      int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
-      buffer_.Store<int32_t>(position, encoded);
-      label->position_ = Assembler::DecodeBranchOffset(next);
-    }
-  }
-  label->BindTo(bound_pc);
-}
-
 void Assembler::BindARMv7(Label* label) {
   ASSERT(!label->IsBound());
   intptr_t bound_pc = buffer_.Size();
@@ -2345,13 +2201,7 @@ void Assembler::BindARMv7(Label* label) {
 }
 
 void Assembler::Bind(Label* label) {
-  const ARMVersion version = TargetCPUFeatures::arm_version();
-  if (version == ARMv6) {
-    BindARMv6(label);
-  } else {
-    ASSERT(version == ARMv7);
-    BindARMv7(label);
-  }
+  BindARMv7(label);
 }
 
 OperandSize Address::OperandSizeFor(intptr_t cid) {
@@ -2794,45 +2644,19 @@ void Assembler::BranchLinkOffset(Register base, int32_t offset) {
 void Assembler::LoadPatchableImmediate(Register rd,
                                        int32_t value,
                                        Condition cond) {
-  const ARMVersion version = TargetCPUFeatures::arm_version();
-  if (version == ARMv6) {
-    // This sequence is patched in a few places, and should remain fixed.
-    const uint32_t byte0 = (value & 0x000000ff);
-    const uint32_t byte1 = (value & 0x0000ff00) >> 8;
-    const uint32_t byte2 = (value & 0x00ff0000) >> 16;
-    const uint32_t byte3 = (value & 0xff000000) >> 24;
-    mov(rd, Operand(4, byte3), cond);
-    orr(rd, rd, Operand(8, byte2), cond);
-    orr(rd, rd, Operand(12, byte1), cond);
-    orr(rd, rd, Operand(byte0), cond);
-  } else {
-    ASSERT(version == ARMv7);
-    const uint16_t value_low = Utils::Low16Bits(value);
-    const uint16_t value_high = Utils::High16Bits(value);
-    movw(rd, value_low, cond);
-    movt(rd, value_high, cond);
-  }
+  const uint16_t value_low = Utils::Low16Bits(value);
+  const uint16_t value_high = Utils::High16Bits(value);
+  movw(rd, value_low, cond);
+  movt(rd, value_high, cond);
 }
 
 void Assembler::LoadDecodableImmediate(Register rd,
                                        int32_t value,
                                        Condition cond) {
-  const ARMVersion version = TargetCPUFeatures::arm_version();
-  if (version == ARMv6) {
-    if (constant_pool_allowed()) {
-      const int32_t offset =
-          target::ObjectPool::element_offset(FindImmediate(value));
-      LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, PP, cond);
-    } else {
-      LoadPatchableImmediate(rd, value, cond);
-    }
-  } else {
-    ASSERT(version == ARMv7);
-    movw(rd, Utils::Low16Bits(value), cond);
-    const uint16_t value_high = Utils::High16Bits(value);
-    if (value_high != 0) {
-      movt(rd, value_high, cond);
-    }
+  movw(rd, Utils::Low16Bits(value), cond);
+  const uint16_t value_high = Utils::High16Bits(value);
+  if (value_high != 0) {
+    movt(rd, value_high, cond);
   }
 }
 

runtime/vm/compiler/assembler/assembler_arm.h

@@ -1283,7 +1283,6 @@ class Assembler : public AssemblerBase {
   void movw(Register rd, uint16_t imm16, Condition cond = AL);
   void movt(Register rd, uint16_t imm16, Condition cond = AL);
 
-  void BindARMv6(Label* label);
   void BindARMv7(Label* label);
 
   void BranchLink(const ExternalLabel* label);

runtime/vm/compiler/assembler/assembler_arm_test.cc

@@ -101,18 +101,8 @@ ASSEMBLER_TEST_RUN(MoveRotImm, test) {
 }
 
 ASSEMBLER_TEST_GENERATE(MovImm16, assembler) {
-#if defined(USING_SIMULATOR)
-  // ARMv7 is the default.
-  HostCPUFeatures::set_arm_version(ARMv6);
-  __ LoadPatchableImmediate(R0, 0x12345678 << 1);
-  HostCPUFeatures::set_arm_version(ARMv7);
-  __ LoadPatchableImmediate(R1, 0x12345678);
-  __ sub(R0, R0, Operand(R1));
-  __ bx(LR);
-#else
   __ LoadPatchableImmediate(R0, 0x12345678);
   __ bx(LR);
-#endif
 }
 
 ASSEMBLER_TEST_RUN(MovImm16, test) {

runtime/vm/compiler/assembler/disassembler_arm.cc

@@ -693,10 +693,6 @@ void ARMDecoder::DecodeType01(Instr* instr) {
             break;
           }
           case 3: {
-            if (TargetCPUFeatures::arm_version() != ARMv7) {
-              Unknown(instr);
-              return;
-            }
             // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
             Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
             break;
@@ -742,11 +738,7 @@ void ARMDecoder::DecodeType01(Instr* instr) {
       // 16-bit immediate loads, msr (immediate), and hints
       switch (instr->Bits(20, 5)) {
         case 16: {
-          if (TargetCPUFeatures::arm_version() == ARMv7) {
-            Format(instr, "movw'cond 'rd, #'imm4_12");
-          } else {
-            Unknown(instr);
-          }
+          Format(instr, "movw'cond 'rd, #'imm4_12");
           break;
         }
         case 18: {
@@ -758,11 +750,7 @@ void ARMDecoder::DecodeType01(Instr* instr) {
           break;
         }
         case 20: {
-          if (TargetCPUFeatures::arm_version() == ARMv7) {
-            Format(instr, "movt'cond 'rd, #'imm4_12");
-          } else {
-            Unknown(instr);
-          }
+          Format(instr, "movt'cond 'rd, #'imm4_12");
           break;
         }
         default: {

runtime/vm/compiler/backend/il_arm.cc

@@ -2677,7 +2677,7 @@ LocationSummary* LoadCodeUnitsInstr::MakeLocationSummary(Zone* zone,
                                                          bool opt) const {
   const bool might_box = (representation() == kTagged) && !can_pack_into_smi();
   const intptr_t kNumInputs = 2;
-  const intptr_t kNumTemps = might_box ? 1 : 0;
+  const intptr_t kNumTemps = might_box ? 2 : 0;
   LocationSummary* summary = new (zone) LocationSummary(
       zone, kNumInputs, kNumTemps,
       might_box ? LocationSummary::kCallOnSlowPath : LocationSummary::kNoCall);
@@ -2686,6 +2686,7 @@ LocationSummary* LoadCodeUnitsInstr::MakeLocationSummary(Zone* zone,
 
   if (might_box) {
     summary->set_temp(0, Location::RequiresRegister());
+    summary->set_temp(1, Location::RequiresRegister());
   }
 
   if (representation() == kUnboxedInt64) {

runtime/vm/compiler/ffi/native_calling_convention.cc

@@ -209,7 +209,6 @@ class ArgumentAllocator : public ValueObject {
   // > Procedure Call Standard is used. In this variant, floating-point
   // > (and vector) arguments are passed in general purpose registers
   // > (GPRs) instead of in VFP registers)
-  // https://developer.apple.com/library/archive/documentation/Xcode/Conceptual/iPhoneOSABIReference/Articles/ARMv6FunctionCallingConventions.html#//apple_ref/doc/uid/TP40009021-SW1
   // https://developer.apple.com/library/archive/documentation/Xcode/Conceptual/iPhoneOSABIReference/Articles/ARMv7FunctionCallingConventions.html#//apple_ref/doc/uid/TP40009022-SW1
   void BlockAllFpuRegisters() {
     // Set all bits to 1.