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Apply backports from rust-lang/llvm#55, #57
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‎llvm.spec‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
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Name: llvm
99
Version: 3.9.0
10-
Release: 6%{?dist}
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Release: 7%{?dist}
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Summary: The Low Level Virtual Machine
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1313
License: NCSA
@@ -32,6 +32,8 @@ Patch48: rust-lang-llvm-pr48.patch
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Patch51: rust-lang-llvm-pr51.patch
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Patch53: rust-lang-llvm-pr53.patch
3434
Patch54: rust-lang-llvm-pr54.patch
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Patch55: rust-lang-llvm-pr55.patch
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Patch57: rust-lang-llvm-pr57.patch
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3638
BuildRequires: cmake
3739
BuildRequires: zlib-devel
@@ -94,6 +96,8 @@ Static libraries for the LLVM compiler infrastructure.
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%patch51 -p1 -b .rust51
9597
%patch53 -p1 -b .rust53
9698
%patch54 -p1 -b .rust54
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%patch55 -p1 -b .rust55
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%patch57 -p1 -b .rust57
97101

98102
%build
99103
mkdir -p _build
@@ -209,6 +213,9 @@ make check-all || :
209213
%{_libdir}/*.a
210214

211215
%changelog
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* Tue Nov 29 2016 Josh Stone <[email protected]> - 3.9.0-7
217+
- Apply backports from rust-lang/llvm#55, #57
218+
212219
* Tue Nov 01 2016 Dave Airlie <[email protected] - 3.9.0-6
213220
- rebuild for new arches
214221

‎rust-lang-llvm-pr55.patch‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
From eff5dc809ed54701f2bb3e15c58d01881299cedf Mon Sep 17 00:00:00 2001
2+
From: David Majnemer <[email protected]>
3+
Date: Tue, 11 Oct 2016 01:00:45 +0000
4+
Subject: [rust-lang/llvm#55] [InstCombine] Transform !range metadata to
5+
!nonnull when combining loads
6+
7+
When combining an integer load with !range metadata that does not include 0 to a pointer load, make sure emit !nonnull metadata on the newly-created pointer load. This prevents the !nonnull metadata from being dropped during a ptrtoint/inttoptr pair.
8+
9+
This fixes PR30597.
10+
11+
Patch by Ariel Ben-Yehuda!
12+
13+
Differential Revision: https://reviews.llvm.org/D25215
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283836 91177308-0d34-0410-b5e6-96231b3b80d8
16+
---
17+
.../InstCombine/InstCombineLoadStoreAlloca.cpp | 12 ++++++--
18+
test/Transforms/InstCombine/PR30597.ll | 32 ++++++++++++++++++++++
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2 files changed, 42 insertions(+), 2 deletions(-)
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create mode 100644 test/Transforms/InstCombine/PR30597.ll
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22+
diff --git a/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
23+
index d312983ed51b..26f4e764501a 100644
24+
--- a/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
25+
+++ b/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
26+
@@ -380,8 +380,16 @@ static LoadInst *combineLoadToNewType(InstCombiner &IC, LoadInst &LI, Type *NewT
27+
break;
28+
case LLVMContext::MD_range:
29+
// FIXME: It would be nice to propagate this in some way, but the type
30+
- // conversions make it hard. If the new type is a pointer, we could
31+
- // translate it to !nonnull metadata.
32+
+ // conversions make it hard.
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+
34+
+ // If it's a pointer now and the range does not contain 0, make it !nonnull.
35+
+ if (NewTy->isPointerTy()) {
36+
+ unsigned BitWidth = IC.getDataLayout().getTypeSizeInBits(NewTy);
37+
+ if (!getConstantRangeFromMetadata(*N).contains(APInt(BitWidth, 0))) {
38+
+ MDNode *NN = MDNode::get(LI.getContext(), None);
39+
+ NewLoad->setMetadata(LLVMContext::MD_nonnull, NN);
40+
+ }
41+
+ }
42+
break;
43+
}
44+
}
45+
diff --git a/test/Transforms/InstCombine/PR30597.ll b/test/Transforms/InstCombine/PR30597.ll
46+
new file mode 100644
47+
index 000000000000..c0803ed71204
48+
--- /dev/null
49+
+++ b/test/Transforms/InstCombine/PR30597.ll
50+
@@ -0,0 +1,32 @@
51+
+; RUN: opt < %s -instcombine -S | FileCheck %s
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+
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+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
54+
+target triple = "x86_64-unknown-linux-gnu"
55+
+
56+
+; Function Attrs: readonly uwtable
57+
+define i1 @dot_ref_s(i32** noalias nocapture readonly dereferenceable(8)) {
58+
+entry-block:
59+
+ %loadedptr = load i32*, i32** %0, align 8, !nonnull !0
60+
+ %ptrtoint = ptrtoint i32* %loadedptr to i64
61+
+ %inttoptr = inttoptr i64 %ptrtoint to i32*
62+
+ %switchtmp = icmp eq i32* %inttoptr, null
63+
+ ret i1 %switchtmp
64+
+
65+
+; CHECK-LABEL: @dot_ref_s
66+
+; CHECK-NEXT: entry-block:
67+
+; CHECK-NEXT: ret i1 false
68+
+}
69+
+
70+
+; Function Attrs: readonly uwtable
71+
+define i64* @function(i64* noalias nocapture readonly dereferenceable(8)) {
72+
+entry-block:
73+
+ %loaded = load i64, i64* %0, align 8, !range !1
74+
+ %inttoptr = inttoptr i64 %loaded to i64*
75+
+ ret i64* %inttoptr
76+
+; CHECK-LABEL: @function
77+
+; CHECK: %{{.+}} = load i64*, i64** %{{.+}}, align 8, !nonnull
78+
+}
79+
+
80+
+
81+
+!0 = !{}
82+
+!1 = !{i64 1, i64 140737488355327}
83+
--
84+
2.9.3
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‎rust-lang-llvm-pr57.patch‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
From 5ac4f80be3e8b5d42475aeaba246455e0016c7ef Mon Sep 17 00:00:00 2001
2+
From: Anthony Ramine <[email protected]>
3+
Date: Sun, 27 Nov 2016 16:28:12 +0100
4+
Subject: [rust-lang/llvm#57] Backport rL277331
5+
6+
---
7+
lib/Target/AArch64/AArch64InstrInfo.cpp | 3 +
8+
.../MIR/AArch64/inst-size-tlsdesc-callseq.mir | 84 ++++++++++++++++++++++
9+
2 files changed, 87 insertions(+)
10+
create mode 100644 test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
11+
12+
diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
13+
index 0aa4708f35ac..d39542a8e4eb 100644
14+
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
15+
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
16+
@@ -56,6 +56,9 @@ unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
17+
case TargetOpcode::IMPLICIT_DEF:
18+
case TargetOpcode::KILL:
19+
return 0;
20+
+ case AArch64::TLSDESC_CALLSEQ:
21+
+ // This gets lowered to an instruction sequence which takes 16 bytes
22+
+ return 16;
23+
}
24+
25+
llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
26+
diff --git a/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
27+
new file mode 100644
28+
index 000000000000..2d966ece768e
29+
--- /dev/null
30+
+++ b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
31+
@@ -0,0 +1,84 @@
32+
+# RUN: llc -mtriple=aarch64-unknown -run-pass aarch64-branch-relax -aarch64-tbz-offset-bits=4 %s -o - | FileCheck %s
33+
+--- |
34+
+ ; ModuleID = 'test.ll'
35+
+ source_filename = "test.ll"
36+
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
37+
+ target triple = "aarch64-unknown"
38+
+
39+
+ @ThreadLocalGlobal = external thread_local local_unnamed_addr global i32, align 8
40+
+
41+
+ define i32 @test_tlsdesc_callseq_length(i32 %in) {
42+
+ %val = and i32 %in, 1
43+
+ %tst = icmp eq i32 %val, 0
44+
+ br i1 %tst, label %true, label %false
45+
+
46+
+ true: ; preds = %0
47+
+ %1 = load i32, i32* @ThreadLocalGlobal, align 8
48+
+ ret i32 %1
49+
+
50+
+ false: ; preds = %0
51+
+ ret i32 0
52+
+ }
53+
+
54+
+...
55+
+---
56+
+# CHECK-LABEL: name:{{.*}}test_tlsdesc_callseq_length
57+
+# If the size of TLSDESC_CALLSEQ is computed correctly, that will push
58+
+# the bb.2.false block too far away from the TBNZW, so the branch will
59+
+# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to
60+
+# constrain the range that can be reached with the TBNZW to something smaller
61+
+# than what TLSDESC_CALLSEQ is lowered to).
62+
+# CHECK: TBZW killed %w0, 0, %bb.1.true
63+
+# CHECK: B %bb.2.false
64+
+name: test_tlsdesc_callseq_length
65+
+alignment: 2
66+
+exposesReturnsTwice: false
67+
+hasInlineAsm: false
68+
+allVRegsAllocated: true
69+
+isSSA: false
70+
+tracksRegLiveness: false
71+
+tracksSubRegLiveness: false
72+
+liveins:
73+
+ - { reg: '%w0' }
74+
+frameInfo:
75+
+ isFrameAddressTaken: false
76+
+ isReturnAddressTaken: false
77+
+ hasStackMap: false
78+
+ hasPatchPoint: false
79+
+ stackSize: 16
80+
+ offsetAdjustment: 0
81+
+ maxAlignment: 16
82+
+ adjustsStack: false
83+
+ hasCalls: true
84+
+ maxCallFrameSize: 0
85+
+ hasOpaqueSPAdjustment: false
86+
+ hasVAStart: false
87+
+ hasMustTailInVarArgFunc: false
88+
+stack:
89+
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%lr' }
90+
+body: |
91+
+ bb.0 (%ir-block.0):
92+
+ successors: %bb.1.true, %bb.2.false
93+
+ liveins: %w0, %lr
94+
+
95+
+ TBNZW killed %w0, 0, %bb.2.false
96+
+
97+
+ bb.1.true:
98+
+ liveins: %lr
99+
+
100+
+ early-clobber %sp = frame-setup STRXpre killed %lr, %sp, -16 :: (store 8 into %stack.0)
101+
+ frame-setup CFI_INSTRUCTION def_cfa_offset 16
102+
+ frame-setup CFI_INSTRUCTION offset %w30, -16
103+
+ TLSDESC_CALLSEQ target-flags(aarch64-tls) @ThreadLocalGlobal, implicit-def dead %lr, implicit-def %x0, implicit-def dead %x1
104+
+ %x8 = MRS 56962
105+
+ %w0 = LDRWroX killed %x8, killed %x0, 0, 0 :: (load 4 from @ThreadLocalGlobal, align 8)
106+
+ early-clobber %sp, %lr = LDRXpost %sp, 16 :: (load 8 from %stack.0)
107+
+ RET killed %lr, implicit killed %w0
108+
+
109+
+ bb.2.false:
110+
+ liveins: %lr
111+
+
112+
+ %w0 = ORRWrs %wzr, %wzr, 0
113+
+ RET killed %lr, implicit killed %w0
114+
+
115+
+...
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--
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2.9.3
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