@@ -64,6 +64,32 @@ enum idpf_rss_hash {
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#define IDPF_TXD_COMPLQ_QID_S 0
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#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)
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+ /* For base mode TX descriptors */
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+
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+ #define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23
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+ #define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)
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+ #define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19
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+ #define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \
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+ (0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S)
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+ #define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12
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+ #define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \
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+ (0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S)
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+ #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11
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+ #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \
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+ BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)
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+ #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \
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+ IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M
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+ #define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9
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+ #define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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+ #define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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+ #define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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+ #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2
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+ #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \
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+ (0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S)
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+ #define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0
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+ #define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \
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+ (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S)
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+
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#define IDPF_TXD_CTX_QW1_MSS_S 50
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#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)
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#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30
@@ -112,6 +138,27 @@ enum idpf_tx_desc_dtype_value {
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IDPF_TX_DESC_DTYPE_DESC_DONE = 15 ,
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};
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+ enum idpf_tx_ctx_desc_cmd_bits {
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+ IDPF_TX_CTX_DESC_TSO = 0x01 ,
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+ IDPF_TX_CTX_DESC_TSYN = 0x02 ,
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+ IDPF_TX_CTX_DESC_IL2TAG2 = 0x04 ,
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+ IDPF_TX_CTX_DESC_RSVD = 0x08 ,
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+ IDPF_TX_CTX_DESC_SWTCH_NOTAG = 0x00 ,
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+ IDPF_TX_CTX_DESC_SWTCH_UPLINK = 0x10 ,
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+ IDPF_TX_CTX_DESC_SWTCH_LOCAL = 0x20 ,
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+ IDPF_TX_CTX_DESC_SWTCH_VSI = 0x30 ,
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+ IDPF_TX_CTX_DESC_FILT_AU_EN = 0x40 ,
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+ IDPF_TX_CTX_DESC_FILT_AU_EVICT = 0x80 ,
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+ IDPF_TX_CTX_DESC_RSVD1 = 0xF00
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+ };
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+
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+ enum idpf_tx_desc_len_fields {
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+ /* Note: These are predefined bit offsets */
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+ IDPF_TX_DESC_LEN_MACLEN_S = 0 , /* 7 BITS */
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+ IDPF_TX_DESC_LEN_IPLEN_S = 7 , /* 7 BITS */
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+ IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
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+ };
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+
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enum idpf_tx_base_desc_cmd_bits {
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IDPF_TX_DESC_CMD_EOP = BIT (0 ),
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IDPF_TX_DESC_CMD_RS = BIT (1 ),
@@ -148,6 +195,16 @@ struct idpf_splitq_tx_compl_desc {
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u8 rsvd ; /* Reserved */
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}; /* writeback used with completion queues */
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+ /* Context descriptors */
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+ struct idpf_base_tx_ctx_desc {
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+ struct {
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+ __le32 tunneling_params ;
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+ __le16 l2tag2 ;
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+ __le16 rsvd1 ;
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+ } qw0 ;
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+ __le64 qw1 ; /* type_cmd_tlen_mss/rt_hint */
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+ };
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+
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/* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */
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enum idpf_tx_flex_desc_cmd_bits {
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IDPF_TX_FLEX_DESC_CMD_EOP = BIT (0 ),
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