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dhananjay-AMDsuperm1
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cpufreq/amd-pstate: Fix the scaling_max_freq setting on shared memory CPPC systems
On shared memory CPPC systems, with amd_pstate=active mode, the change in scaling_max_freq doesn't get written to the shared memory region. Due to this, the writes to the scaling_max_freq sysfs file don't take effect. Fix this by propagating the scaling_max_freq changes to the shared memory region. Fixes: ffa5096 ("cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors") Reported-by: David Arcari <[email protected]> Signed-off-by: Dhananjay Ugwekar <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mario Limonciello <[email protected]>
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drivers/cpufreq/amd-pstate.c

Lines changed: 23 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,26 @@ static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata)
239239
return index;
240240
}
241241

242+
static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
243+
u32 des_perf, u32 max_perf, bool fast_switch)
244+
{
245+
if (fast_switch)
246+
wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
247+
else
248+
wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
249+
READ_ONCE(cpudata->cppc_req_cached));
250+
}
251+
252+
DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
253+
254+
static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
255+
u32 min_perf, u32 des_perf,
256+
u32 max_perf, bool fast_switch)
257+
{
258+
static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,
259+
max_perf, fast_switch);
260+
}
261+
242262
static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
243263
{
244264
int ret;
@@ -255,6 +275,9 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
255275
if (!ret)
256276
cpudata->epp_cached = epp;
257277
} else {
278+
amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U,
279+
cpudata->max_limit_perf, false);
280+
258281
perf_ctrls.energy_perf = epp;
259282
ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
260283
if (ret) {
@@ -442,16 +465,6 @@ static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
442465
return static_call(amd_pstate_init_perf)(cpudata);
443466
}
444467

445-
static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
446-
u32 des_perf, u32 max_perf, bool fast_switch)
447-
{
448-
if (fast_switch)
449-
wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
450-
else
451-
wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
452-
READ_ONCE(cpudata->cppc_req_cached));
453-
}
454-
455468
static void cppc_update_perf(struct amd_cpudata *cpudata,
456469
u32 min_perf, u32 des_perf,
457470
u32 max_perf, bool fast_switch)
@@ -465,16 +478,6 @@ static void cppc_update_perf(struct amd_cpudata *cpudata,
465478
cppc_set_perf(cpudata->cpu, &perf_ctrls);
466479
}
467480

468-
DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
469-
470-
static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
471-
u32 min_perf, u32 des_perf,
472-
u32 max_perf, bool fast_switch)
473-
{
474-
static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,
475-
max_perf, fast_switch);
476-
}
477-
478481
static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
479482
{
480483
u64 aperf, mperf, tsc;

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