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floehopperfloehopper
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Implement Computer.
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4 files changed

+114
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‎projects/05/Computer.hdl

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@@ -19,5 +19,10 @@ CHIP Computer {
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IN reset;
2020

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PARTS:
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// Put your code here:
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ROM32K(address=pc, out=instruction);
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Memory(in=outM, load=writeM, address=addressM, out=inM);
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CPU(
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inM=inM, instruction=instruction, reset=reset,
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outM=outM, writeM=writeM, addressM=addressM, pc=pc
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);
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}

‎projects/05/ComputerAdd.out

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| time |reset|ARegister|DRegister|PC[]|RAM16K[0]|RAM16K[1]|RAM16K[2]|
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| 0 | 0 | 0 | 0 | 0| 0 | 0 | 0 |
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| 1 | 0 | 2 | 0 | 1| 0 | 0 | 0 |
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| 2 | 0 | 2 | 2 | 2| 0 | 0 | 0 |
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| 3 | 0 | 3 | 2 | 3| 0 | 0 | 0 |
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| 4 | 0 | 3 | 5 | 4| 0 | 0 | 0 |
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| 5 | 0 | 0 | 5 | 5| 0 | 0 | 0 |
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| 6 | 0 | 0 | 5 | 6| 5 | 0 | 0 |
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| 7 | 1 | 0 | 5 | 0| 0 | 0 | 0 |
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| 8 | 0 | 2 | 5 | 1| 0 | 0 | 0 |
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| 9 | 0 | 2 | 2 | 2| 0 | 0 | 0 |
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| 10 | 0 | 3 | 2 | 3| 0 | 0 | 0 |
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| 11 | 0 | 3 | 5 | 4| 0 | 0 | 0 |
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| 12 | 0 | 0 | 5 | 5| 0 | 0 | 0 |
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| 13 | 0 | 0 | 5 | 6| 5 | 0 | 0 |

‎projects/05/ComputerMax.out

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| time |reset|ARegister|DRegister|PC[]|RAM16K[0]|RAM16K[1]|RAM16K[2]|
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| 0 | 0 | 0 | 0 | 0| 3 | 5 | 0 |
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| 1 | 0 | 0 | 0 | 1| 3 | 5 | 0 |
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| 2 | 0 | 0 | 3 | 2| 3 | 5 | 0 |
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| 3 | 0 | 1 | 3 | 3| 3 | 5 | 0 |
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| 4 | 0 | 1 | -2 | 4| 3 | 5 | 0 |
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| 5 | 0 | 10 | -2 | 5| 3 | 5 | 0 |
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| 6 | 0 | 10 | -2 | 6| 3 | 5 | 0 |
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| 7 | 0 | 1 | -2 | 7| 3 | 5 | 0 |
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| 8 | 0 | 1 | 5 | 8| 3 | 5 | 0 |
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| 9 | 0 | 12 | 5 | 9| 3 | 5 | 0 |
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| 10 | 0 | 12 | 5 | 12| 3 | 5 | 0 |
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| 11 | 0 | 2 | 5 | 13| 3 | 5 | 0 |
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| 12 | 0 | 2 | 5 | 14| 3 | 5 | 5 |
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| 13 | 0 | 14 | 5 | 15| 3 | 5 | 5 |
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| 14 | 0 | 14 | 5 | 14| 3 | 5 | 5 |
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| 15 | 1 | 14 | 5 | 0| 3 | 5 | 5 |
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| 15 | 0 | 14 | 5 | 0| 23456 | 12345 | 5 |
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| 16 | 0 | 0 | 5 | 1| 23456 | 12345 | 5 |
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| 17 | 0 | 0 | 23456 | 2| 23456 | 12345 | 5 |
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| 18 | 0 | 1 | 23456 | 3| 23456 | 12345 | 5 |
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| 19 | 0 | 1 | 11111 | 4| 23456 | 12345 | 5 |
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| 20 | 0 | 10 | 11111 | 5| 23456 | 12345 | 5 |
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| 21 | 0 | 10 | 11111 | 10| 23456 | 12345 | 5 |
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| 22 | 0 | 0 | 11111 | 11| 23456 | 12345 | 5 |
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| 23 | 0 | 0 | 23456 | 12| 23456 | 12345 | 5 |
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| 24 | 0 | 2 | 23456 | 13| 23456 | 12345 | 5 |
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| 25 | 0 | 2 | 23456 | 14| 23456 | 12345 | 23456 |

‎projects/05/ComputerRect.out

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| time |ARegister|DRegister|PC[]|RAM16K[0]|RAM16K[1]|RAM16K[2]|
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| 0 | 0 | 0 | 0| 4 | 0 | 0 |
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| 1 | 0 | 0 | 1| 4 | 0 | 0 |
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| 2 | 0 | 4 | 2| 4 | 0 | 0 |
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| 3 | 23 | 4 | 3| 4 | 0 | 0 |
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| 4 | 23 | 4 | 4| 4 | 0 | 0 |
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| 5 | 16 | 4 | 5| 4 | 0 | 0 |
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| 6 | 16 | 4 | 6| 4 | 0 | 0 |
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| 7 | 16384 | 4 | 7| 4 | 0 | 0 |
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| 8 | 16384 | 16384 | 8| 4 | 0 | 0 |
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| 9 | 17 | 16384 | 9| 4 | 0 | 0 |
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| 10 | 17 | 16384 | 10| 4 | 0 | 0 |
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| 11 | 17 | 16384 | 11| 4 | 0 | 0 |
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| 12 | 16384 | 16384 | 12| 4 | 0 | 0 |
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| 13 | 16384 | 16384 | 13| 4 | 0 | 0 |
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| 14 | 17 | 16384 | 14| 4 | 0 | 0 |
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| 15 | 17 | 16384 | 15| 4 | 0 | 0 |
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| 16 | 32 | 16384 | 16| 4 | 0 | 0 |
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| 17 | 32 | 16416 | 17| 4 | 0 | 0 |
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| 18 | 17 | 16416 | 18| 4 | 0 | 0 |
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| 19 | 17 | 16416 | 19| 4 | 0 | 0 |
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| 20 | 16 | 16416 | 20| 4 | 0 | 0 |
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| 21 | 16 | 3 | 21| 4 | 0 | 0 |
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| 22 | 10 | 3 | 22| 4 | 0 | 0 |
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| 23 | 10 | 3 | 10| 4 | 0 | 0 |
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| 24 | 17 | 3 | 11| 4 | 0 | 0 |
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| 25 | 16416 | 3 | 12| 4 | 0 | 0 |
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| 26 | 16416 | 3 | 13| 4 | 0 | 0 |
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| 27 | 17 | 3 | 14| 4 | 0 | 0 |
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| 28 | 17 | 16416 | 15| 4 | 0 | 0 |
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| 29 | 32 | 16416 | 16| 4 | 0 | 0 |
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| 30 | 32 | 16448 | 17| 4 | 0 | 0 |
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| 31 | 17 | 16448 | 18| 4 | 0 | 0 |
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| 36 | 10 | 2 | 10| 4 | 0 | 0 |
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| 37 | 17 | 2 | 11| 4 | 0 | 0 |
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| 42 | 32 | 16448 | 16| 4 | 0 | 0 |
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| 43 | 32 | 16480 | 17| 4 | 0 | 0 |
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| 50 | 17 | 1 | 11| 4 | 0 | 0 |
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| 51 | 16480 | 1 | 12| 4 | 0 | 0 |
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| 52 | 16480 | 1 | 13| 4 | 0 | 0 |
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| 53 | 17 | 1 | 14| 4 | 0 | 0 |
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| 54 | 17 | 16480 | 15| 4 | 0 | 0 |
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| 55 | 32 | 16480 | 16| 4 | 0 | 0 |
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| 56 | 32 | 16512 | 17| 4 | 0 | 0 |
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| 57 | 17 | 16512 | 18| 4 | 0 | 0 |
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| 58 | 17 | 16512 | 19| 4 | 0 | 0 |
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| 59 | 16 | 16512 | 20| 4 | 0 | 0 |
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| 60 | 16 | 0 | 21| 4 | 0 | 0 |
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| 61 | 10 | 0 | 22| 4 | 0 | 0 |
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| 62 | 10 | 0 | 23| 4 | 0 | 0 |
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| 63 | 23 | 0 | 24| 4 | 0 | 0 |

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