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vinodkoul
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drm/msm/disp/dpu1: Add support for DSC
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add support by adding hw blocks for DSC Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/480912/ Link: https://lore.kernel.org/r/[email protected] [DB: applied typo noticed by Robert Foss] Signed-off-by: Dmitry Baryshkov <[email protected]>
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‎drivers/gpu/drm/msm/Makefile

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Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
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disp/dpu1/dpu_formats.o \
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disp/dpu1/dpu_hw_catalog.o \
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disp/dpu1/dpu_hw_ctl.o \
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disp/dpu1/dpu_hw_dsc.o \
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disp/dpu1/dpu_hw_interrupts.o \
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disp/dpu1/dpu_hw_intf.o \
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disp/dpu1/dpu_hw_lm.o \

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

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Original file line numberDiff line numberDiff line change
@@ -561,6 +561,16 @@ struct dpu_merge_3d_cfg {
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const struct dpu_merge_3d_sub_blks *sblk;
562562
};
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/**
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* struct dpu_dsc_cfg - information of DSC blocks
566+
* @id enum identifying this block
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* @base register offset of this block
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* @features bit mask identifying sub-blocks/features
569+
*/
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struct dpu_dsc_cfg {
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DPU_HW_BLK_INFO;
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};
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/**
565575
* struct dpu_intf_cfg - information of timing engine blocks
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* @id enum identifying this block
@@ -757,6 +767,9 @@ struct dpu_mdss_cfg {
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u32 merge_3d_count;
758768
const struct dpu_merge_3d_cfg *merge_3d;
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u32 dsc_count;
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struct dpu_dsc_cfg *dsc;
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u32 intf_count;
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const struct dpu_intf_cfg *intf;
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‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,215 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2022, Linaro Limited
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*/
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#include "dpu_kms.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_dsc.h"
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#define DSC_COMMON_MODE 0x000
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#define DSC_ENC 0x004
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#define DSC_PICTURE 0x008
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#define DSC_SLICE 0x00C
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#define DSC_CHUNK_SIZE 0x010
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#define DSC_DELAY 0x014
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#define DSC_SCALE_INITIAL 0x018
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#define DSC_SCALE_DEC_INTERVAL 0x01C
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#define DSC_SCALE_INC_INTERVAL 0x020
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#define DSC_FIRST_LINE_BPG_OFFSET 0x024
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#define DSC_BPG_OFFSET 0x028
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#define DSC_DSC_OFFSET 0x02C
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#define DSC_FLATNESS 0x030
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#define DSC_RC_MODEL_SIZE 0x034
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#define DSC_RC 0x038
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#define DSC_RC_BUF_THRESH 0x03C
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#define DSC_RANGE_MIN_QP 0x074
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#define DSC_RANGE_MAX_QP 0x0B0
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#define DSC_RANGE_BPG_OFFSET 0x0EC
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static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
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{
34+
struct dpu_hw_blk_reg_map *c = &dsc->hw;
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DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
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}
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static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
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struct msm_display_dsc_config *dsc,
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u32 mode,
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u32 initial_lines)
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{
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struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
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u32 data, lsb, bpp;
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u32 slice_last_group_size;
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u32 det_thresh_flatness;
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bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
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DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
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if (is_cmd_mode)
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initial_lines += 1;
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slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
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data = (initial_lines << 20);
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data |= ((slice_last_group_size - 1) << 18);
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/* bpp is 6.4 format, 4 LSBs bits are for fractional part */
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data |= dsc->drm->bits_per_pixel << 12;
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lsb = dsc->drm->bits_per_pixel % 4;
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bpp = dsc->drm->bits_per_pixel / 4;
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bpp *= 4;
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bpp <<= 4;
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bpp |= lsb;
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data |= bpp << 8;
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data |= (dsc->drm->block_pred_enable << 7);
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data |= (dsc->drm->line_buf_depth << 3);
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data |= (dsc->drm->simple_422 << 2);
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data |= (dsc->drm->convert_rgb << 1);
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data |= dsc->drm->bits_per_component;
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DPU_REG_WRITE(c, DSC_ENC, data);
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data = dsc->drm->pic_width << 16;
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data |= dsc->drm->pic_height;
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DPU_REG_WRITE(c, DSC_PICTURE, data);
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data = dsc->drm->slice_width << 16;
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data |= dsc->drm->slice_height;
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DPU_REG_WRITE(c, DSC_SLICE, data);
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data = dsc->drm->slice_chunk_size << 16;
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DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
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data = dsc->drm->initial_dec_delay << 16;
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data |= dsc->drm->initial_xmit_delay;
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DPU_REG_WRITE(c, DSC_DELAY, data);
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90+
data = dsc->drm->initial_scale_value;
91+
DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
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93+
data = dsc->drm->scale_decrement_interval;
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DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
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data = dsc->drm->scale_increment_interval;
97+
DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
98+
99+
data = dsc->drm->first_line_bpg_offset;
100+
DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
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102+
data = dsc->drm->nfl_bpg_offset << 16;
103+
data |= dsc->drm->slice_bpg_offset;
104+
DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
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data = dsc->drm->initial_offset << 16;
107+
data |= dsc->drm->final_offset;
108+
DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
109+
110+
det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
111+
data = det_thresh_flatness << 10;
112+
data |= dsc->drm->flatness_max_qp << 5;
113+
data |= dsc->drm->flatness_min_qp;
114+
DPU_REG_WRITE(c, DSC_FLATNESS, data);
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116+
data = dsc->drm->rc_model_size;
117+
DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
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data = dsc->drm->rc_tgt_offset_low << 18;
120+
data |= dsc->drm->rc_tgt_offset_high << 14;
121+
data |= dsc->drm->rc_quant_incr_limit1 << 9;
122+
data |= dsc->drm->rc_quant_incr_limit0 << 4;
123+
data |= dsc->drm->rc_edge_factor;
124+
DPU_REG_WRITE(c, DSC_RC, data);
125+
}
126+
127+
static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
128+
struct msm_display_dsc_config *dsc)
129+
{
130+
struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
131+
struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
132+
u32 off;
133+
int i;
134+
135+
off = DSC_RC_BUF_THRESH;
136+
for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
137+
DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
138+
off += 4;
139+
}
140+
141+
off = DSC_RANGE_MIN_QP;
142+
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
143+
DPU_REG_WRITE(c, off, rc[i].range_min_qp);
144+
off += 4;
145+
}
146+
147+
off = DSC_RANGE_MAX_QP;
148+
for (i = 0; i < 15; i++) {
149+
DPU_REG_WRITE(c, off, rc[i].range_max_qp);
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off += 4;
151+
}
152+
153+
off = DSC_RANGE_BPG_OFFSET;
154+
for (i = 0; i < 15; i++) {
155+
DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
156+
off += 4;
157+
}
158+
}
159+
160+
static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
161+
struct dpu_mdss_cfg *m,
162+
void __iomem *addr,
163+
struct dpu_hw_blk_reg_map *b)
164+
{
165+
int i;
166+
167+
for (i = 0; i < m->dsc_count; i++) {
168+
if (dsc == m->dsc[i].id) {
169+
b->base_off = addr;
170+
b->blk_off = m->dsc[i].base;
171+
b->length = m->dsc[i].len;
172+
b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_DSC;
174+
return &m->dsc[i];
175+
}
176+
}
177+
178+
return NULL;
179+
}
180+
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static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
182+
unsigned long cap)
183+
{
184+
ops->dsc_disable = dpu_hw_dsc_disable;
185+
ops->dsc_config = dpu_hw_dsc_config;
186+
ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
187+
};
188+
189+
struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
190+
struct dpu_mdss_cfg *m)
191+
{
192+
struct dpu_hw_dsc *c;
193+
struct dpu_dsc_cfg *cfg;
194+
195+
c = kzalloc(sizeof(*c), GFP_KERNEL);
196+
if (!c)
197+
return ERR_PTR(-ENOMEM);
198+
199+
cfg = _dsc_offset(idx, m, addr, &c->hw);
200+
if (IS_ERR_OR_NULL(cfg)) {
201+
kfree(c);
202+
return ERR_PTR(-EINVAL);
203+
}
204+
205+
c->idx = idx;
206+
c->caps = cfg;
207+
_setup_dsc_ops(&c->ops, c->caps->features);
208+
209+
return c;
210+
}
211+
212+
void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
213+
{
214+
kfree(dsc);
215+
}

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
/* Copyright (c) 2020-2022, Linaro Limited */
3+
4+
#ifndef _DPU_HW_DSC_H
5+
#define _DPU_HW_DSC_H
6+
7+
#include <drm/drm_dsc.h>
8+
9+
#define DSC_MODE_SPLIT_PANEL BIT(0)
10+
#define DSC_MODE_MULTIPLEX BIT(1)
11+
#define DSC_MODE_VIDEO BIT(2)
12+
13+
struct dpu_hw_dsc;
14+
15+
/**
16+
* struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
17+
* Assumption is these functions will be called after clocks are enabled
18+
*/
19+
struct dpu_hw_dsc_ops {
20+
/**
21+
* dsc_disable - disable dsc
22+
* @hw_dsc: Pointer to dsc context
23+
*/
24+
void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
25+
26+
/**
27+
* dsc_config - configures dsc encoder
28+
* @hw_dsc: Pointer to dsc context
29+
* @dsc: panel dsc parameters
30+
* @mode: dsc topology mode to be set
31+
* @initial_lines: amount of initial lines to be used
32+
*/
33+
void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
34+
struct msm_display_dsc_config *dsc,
35+
u32 mode,
36+
u32 initial_lines);
37+
38+
/**
39+
* dsc_config_thresh - programs panel thresholds
40+
* @hw_dsc: Pointer to dsc context
41+
* @dsc: panel dsc parameters
42+
*/
43+
void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
44+
struct msm_display_dsc_config *dsc);
45+
};
46+
47+
struct dpu_hw_dsc {
48+
struct dpu_hw_blk base;
49+
struct dpu_hw_blk_reg_map hw;
50+
51+
/* dsc */
52+
enum dpu_dsc idx;
53+
const struct dpu_dsc_cfg *caps;
54+
55+
/* ops */
56+
struct dpu_hw_dsc_ops ops;
57+
};
58+
59+
/**
60+
* dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
61+
* @idx: DSC index for which driver object is required
62+
* @addr: Mapped register io address of MDP
63+
* @m: Pointer to mdss catalog data
64+
* Returns: Error code or allocated dpu_hw_dsc context
65+
*/
66+
struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
67+
struct dpu_mdss_cfg *m);
68+
69+
/**
70+
* dpu_hw_dsc_destroy - destroys dsc driver context
71+
* @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
72+
*/
73+
void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
74+
75+
static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
76+
{
77+
return container_of(hw, struct dpu_hw_dsc, base);
78+
}
79+
80+
#endif /* _DPU_HW_DSC_H */

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
9797
DPU_HW_BLK_WB,
9898
DPU_HW_BLK_DSPP,
9999
DPU_HW_BLK_MERGE_3D,
100+
DPU_HW_BLK_DSC,
100101
DPU_HW_BLK_MAX,
101102
};
102103

@@ -176,6 +177,17 @@ enum dpu_ctl {
176177
CTL_MAX
177178
};
178179

180+
enum dpu_dsc {
181+
DSC_NONE = 0,
182+
DSC_0,
183+
DSC_1,
184+
DSC_2,
185+
DSC_3,
186+
DSC_4,
187+
DSC_5,
188+
DSC_MAX
189+
};
190+
179191
enum dpu_pingpong {
180192
PINGPONG_0 = 1,
181193
PINGPONG_1,
@@ -437,5 +449,6 @@ struct dpu_mdss_color {
437449
#define DPU_DBG_MASK_VBIF (1 << 8)
438450
#define DPU_DBG_MASK_ROT (1 << 9)
439451
#define DPU_DBG_MASK_DSPP (1 << 10)
452+
#define DPU_DBG_MASK_DSC (1 << 11)
440453

441454
#endif /* _DPU_HW_MDSS_H */

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