@@ -231,12 +231,6 @@ NV_STATUS nvos_forward_error_to_cray(struct pci_dev *, NvU32,
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const char * , va_list );
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#endif
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- #if defined(NVCPU_PPC64LE ) && defined(CONFIG_EEH )
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- #include <asm/eeh.h>
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- #define NV_PCI_ERROR_RECOVERY_ENABLED () eeh_enabled()
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- #define NV_PCI_ERROR_RECOVERY
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- #endif
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-
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#if defined(NV_ASM_SET_MEMORY_H_PRESENT )
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#include <asm/set_memory.h>
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#endif
@@ -609,7 +603,7 @@ static NvBool nv_numa_node_has_memory(int node_id)
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#define NV_ALLOC_PAGES_NODE (ptr , nid , order , gfp_mask ) \
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{ \
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- (ptr) = (unsigned long)page_address( alloc_pages_node(nid, gfp_mask, order) ); \
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+ (ptr) = (unsigned long) alloc_pages_node(nid, gfp_mask, order); \
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}
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#define NV_GET_FREE_PAGES (ptr , order , gfp_mask ) \
@@ -881,16 +875,6 @@ typedef void irqreturn_t;
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#define PCI_CAP_ID_EXP 0x10
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#endif
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- /*
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- * On Linux on PPC64LE enable basic support for Linux PCI error recovery (see
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- * Documentation/PCI/pci-error-recovery.txt). Currently RM only supports error
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- * notification and data collection, not actual recovery of the device.
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- */
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- #if defined(NVCPU_PPC64LE ) && defined(CONFIG_EEH )
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- #include <asm/eeh.h>
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- #define NV_PCI_ERROR_RECOVERY
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- #endif
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-
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/*
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* If the host OS has page sizes larger than 4KB, we may have a security
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* problem. Registers are typically grouped in 4KB pages, but if there are
@@ -1419,8 +1403,6 @@ typedef struct nv_dma_map_s {
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0 ? NV_OK : NV_ERR_OPERATING_SYSTEM)
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#endif
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- typedef struct nv_ibmnpu_info nv_ibmnpu_info_t ;
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-
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typedef struct nv_work_s {
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struct work_struct task ;
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void * data ;
@@ -1468,7 +1450,6 @@ struct nv_dma_device {
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} addressable_range ;
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struct device * dev ;
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- NvBool nvlink ;
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};
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/* Properties of the coherent link */
@@ -1517,9 +1498,6 @@ typedef struct nv_linux_state_s {
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struct device * dev ;
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struct pci_dev * pci_dev ;
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- /* IBM-NPU info associated with this GPU */
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- nv_ibmnpu_info_t * npu ;
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-
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/* coherent link information */
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coherent_link_info_t coherent_link_info ;
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@@ -1835,7 +1813,7 @@ static inline int nv_is_control_device(struct inode *inode)
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return (minor ((inode )-> i_rdev ) == NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE );
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}
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- #if defined(NV_DOM0_KERNEL_PRESENT ) || defined(NV_VGPU_KVM_BUILD )
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+ #if defined(NV_DOM0_KERNEL_PRESENT ) || defined(NV_VGPU_KVM_BUILD ) || defined( NV_DEVICE_VM_BUILD )
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#define NV_VGX_HYPER
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#if defined(NV_XEN_IOEMU_INJECT_MSI )
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#include <xen/ioemu.h>
@@ -1872,59 +1850,6 @@ static inline NvBool nv_alloc_release(nv_linux_file_private_t *nvlfp, nv_alloc_t
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#define RB_EMPTY_ROOT (root ) ((root)->rb_node == NULL)
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#endif
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- /*
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- * Starting on Power9 systems, DMA addresses for NVLink are no longer
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- * the same as used over PCIe.
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- *
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- * Power9 supports a 56-bit Real Address. This address range is compressed
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- * when accessed over NVLink to allow the GPU to access all of memory using
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- * its 47-bit Physical address.
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- *
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- * If there is an NPU device present on the system, it implies that NVLink
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- * sysmem links are present and we need to apply the required address
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- * conversion for NVLink within the driver.
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- *
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- * See Bug 1920398 for further background and details.
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- *
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- * Note, a deviation from the documented compression scheme is that the
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- * upper address bits (i.e. bit 56-63) instead of being set to zero are
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- * preserved during NVLink address compression so the orignal PCIe DMA
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- * address can be reconstructed on expansion. These bits can be safely
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- * ignored on NVLink since they are truncated by the GPU.
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- *
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- * Bug 1968345: As a performance enhancement it is the responsibility of
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- * the caller on PowerPC platforms to check for presence of an NPU device
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- * before the address transformation is applied.
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- */
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- static inline NvU64 nv_compress_nvlink_addr (NvU64 addr )
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- {
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- NvU64 addr47 = addr ;
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-
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- #if defined(NVCPU_PPC64LE )
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- addr47 = addr & ((1ULL << 43 ) - 1 );
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- addr47 |= (addr & (0x3ULL << 45 )) >> 2 ;
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- WARN_ON (addr47 & (1ULL << 44 ));
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- addr47 |= (addr & (0x3ULL << 49 )) >> 4 ;
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- addr47 |= addr & ~((1ULL << 56 ) - 1 );
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- #endif
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-
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- return addr47 ;
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- }
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-
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- static inline NvU64 nv_expand_nvlink_addr (NvU64 addr47 )
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- {
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- NvU64 addr = addr47 ;
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-
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- #if defined(NVCPU_PPC64LE )
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- addr = addr47 & ((1ULL << 43 ) - 1 );
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- addr |= (addr47 & (3ULL << 43 )) << 2 ;
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- addr |= (addr47 & (3ULL << 45 )) << 4 ;
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- addr |= addr47 & ~((1ULL << 56 ) - 1 );
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- #endif
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-
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- return addr ;
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- }
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-
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// Default flags for ISRs
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static inline NvU32 nv_default_irq_flags (nv_state_t * nv )
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{
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