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Integrate LLVM@d6e2143b064e
Upgrades dependencies: - LLVM at d6e2143b064e62458eb210394e623bc0abeb266b - Stablehlo at 4c0d4841519aed22e3689c30b72a0e4228051249 - Torch-MLIR at d7e34845a7bbc717c5710769b721698d9cc37a9b GitOrigin-RevId: a64a9dac6b3d58706d0bcf1411021ba1607b1168
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‎mlir-tensorrt/DependencyProvider.cmake‎

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ if("${MLIR_TRT_USE_LLVM}" STREQUAL "prebuilt")
7676
set(MTRT_BUILD_LLVM_FROM_SOURCE OFF)
7777
endif()
7878

79-
set(MLIR_TRT_LLVM_COMMIT "f137c3d592e96330e450a8fd63ef7e8877fc1908")
79+
set(MLIR_TRT_LLVM_COMMIT "d6e2143b064e62458eb210394e623bc0abeb266b")
8080

8181
set(mlir_patch_dir "${CMAKE_CURRENT_LIST_DIR}/build_tools/patches/mlir")
8282

@@ -89,11 +89,12 @@ else()
8989
EXCLUDE_FROM_ALL TRUE
9090
SOURCE_SUBDIR "llvm"
9191
PATCHES
92-
"${mlir_patch_dir}/0005-mlir-memref-Fix-memref.global-overly-constrained-ver.patch"
93-
"${mlir_patch_dir}/0006-mlir-emitc-Fix-two-EmitC-bugs.patch"
94-
"${mlir_patch_dir}/0009-mlir-Support-FileLineColRange-in-LLVM-debug-translat.patch"
95-
"${mlir_patch_dir}/0011-MLIR-Fix-bufferization-interface-for-tensor-reshape.patch"
96-
"${mlir_patch_dir}/0001-NVPTX-Add-support-for-PTX-ISA-v8.8-136639.patch"
92+
"${mlir_patch_dir}/0001-mlir-linalg-don-t-rewrite-DPS-init-operands-in-linal.patch"
93+
"${mlir_patch_dir}/0002-mlir-emitc-Fix-emitc.for-verification-crash-163754.patch"
94+
"${mlir_patch_dir}/0003-mlir-emitc-Unify-API-for-deferred-emission-167532.patch"
95+
"${mlir_patch_dir}/0004-mlir-emitc-Remove-dead-methods-from-emitter-167657.patch"
96+
"${mlir_patch_dir}/0005-mlir-emitc-Fix-ineffective-tests-168197.patch"
97+
"${mlir_patch_dir}/0006-mlir-emitc-Refactor-brackets-in-expressions-168267.patch"
9798
# Set the CPM cache key to the Git hash for easy navigation.
9899
PRE_ADD_HOOK [[
99100
list(APPEND _vap_UNPARSED_ARGUMENTS
@@ -154,8 +155,7 @@ nv_register_package(
154155
# Stablehlo
155156
#-------------------------------------------------------------------------------------
156157
set(stablehlo_patch_dir "${CMAKE_SOURCE_DIR}/build_tools/patches/stablehlo")
157-
set(MLIR_TRT_STABLEHLO_COMMIT "4bf77d23bd9150782a70d85fda9c12a2dec5328c")
158-
158+
set(MLIR_TRT_STABLEHLO_COMMIT "4c0d4841519aed22e3689c30b72a0e4228051249")
159159

160160
nv_register_package(
161161
NAME Stablehlo
@@ -166,12 +166,9 @@ nv_register_package(
166166
"STABLEHLO_BUILD_EMBEDDED ON"
167167
PATCHES
168168
"${stablehlo_patch_dir}/0001-cmake-Update-usage-of-HandleLLVMOptions-and-LLVM_DEF.patch"
169-
"${stablehlo_patch_dir}/0002-Fix-ZeroExtent-condition-in-simplification-pattern.patch"
170-
"${stablehlo_patch_dir}/0003-Remove-explicit-use-of-LLVMSupport.patch"
171-
"${stablehlo_patch_dir}/0004-Fix-circular-dependence-between-StablehloPasses-and-.patch"
172-
"${stablehlo_patch_dir}/0005-Modernize-the-stablehlo-convert-to-signless-pass.patch"
173-
"${stablehlo_patch_dir}/0006-Add-additional-support-for-stablehlo-chlo-ops-to-lin.patch"
174-
"${stablehlo_patch_dir}/0007-Fix-stablehlo-convert-to-signless-pass-to-handle-sta.patch"
169+
"${stablehlo_patch_dir}/0002-Modernize-the-stablehlo-convert-to-signless-pass.patch"
170+
"${stablehlo_patch_dir}/0003-Add-additional-support-for-stablehlo-chlo-ops-to-lin.patch"
171+
"${stablehlo_patch_dir}/0004-Fix-stablehlo-convert-to-signless-pass-to-handle-sta.patch"
175172

176173
POST_ADD_HOOK [[
177174
# Mimic what a StablehloConfig.cmake file would do.
@@ -288,7 +285,7 @@ nv_register_package(
288285
#-------------------------------------------------------------------------------------
289286
# Torch-MLIR
290287
#-------------------------------------------------------------------------------------
291-
set(MLIR_TRT_TORCH_MLIR_COMMIT "9f2ba5abaa85cefd95cc85579fafd0c53c1101e8")
288+
set(MLIR_TRT_TORCH_MLIR_COMMIT "d7e34845a7bbc717c5710769b721698d9cc37a9b")
292289
nv_register_package(
293290
NAME torch_mlir
294291
URL "https://github.com/llvm/torch-mlir/archive/${MLIR_TRT_TORCH_MLIR_COMMIT}.zip"

‎mlir-tensorrt/build_tools/patches/mlir/0001-NVPTX-Add-support-for-PTX-ISA-v8.8-136639.patch‎

Lines changed: 0 additions & 127 deletions
This file was deleted.

‎mlir-tensorrt/build_tools/patches/mlir/0001-mlir-linalg-don-t-rewrite-DPS-init-operands-in-linal.patch‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
From b01ef27862dc0b10119712d539e0ff513d3989fb Mon Sep 17 00:00:00 2001
2+
From: Christopher Bate <[email protected]>
3+
Date: Mon, 10 Mar 2025 22:03:05 +0000
4+
Subject: [PATCH 1/6] [mlir][linalg] don't rewrite DPS init operands in
5+
`linalg-fold-unit-extent-dims` if they are block arguments
6+
7+
---
8+
mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp | 7 ++++---
9+
1 file changed, 4 insertions(+), 3 deletions(-)
10+
11+
diff --git a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
12+
index 22690daa4f9e..05b09824605c 100644
13+
--- a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
14+
+++ b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
15+
@@ -91,6 +91,8 @@ struct MoveInitOperandsToInput : public OpRewritePattern<GenericOp> {
16+
for (OpOperand &op : outputOperands) {
17+
if (genericOp.getMatchingBlockArgument(&op).use_empty())
18+
continue;
19+
+ if (isa<BlockArgument>(op.get()))
20+
+ continue;
21+
candidates.insert(&op);
22+
}
23+
24+
@@ -117,11 +119,10 @@ struct MoveInitOperandsToInput : public OpRewritePattern<GenericOp> {
25+
for (OpOperand *op : candidates) {
26+
OpBuilder::InsertionGuard guard(rewriter);
27+
rewriter.setInsertionPointAfterValue(op->get());
28+
- auto elemType = cast<ShapedType>(op->get().getType()).getElementType();
29+
+ auto tensorType = cast<RankedTensorType>(op->get().getType());
30+
auto empty = tensor::EmptyOp::create(
31+
rewriter, loc, tensor::getMixedSizes(rewriter, loc, op->get()),
32+
- elemType);
33+
-
34+
+ tensorType.getElementType(), tensorType.getEncoding());
35+
unsigned start = genericOp.getDpsInits().getBeginOperandIndex();
36+
newOutputOperands[op->getOperandNumber() - start] = empty.getResult();
37+
}
38+
--
39+
2.52.0
40+

‎mlir-tensorrt/build_tools/patches/mlir/0002-mlir-emitc-Fix-emitc.for-verification-crash-163754.patch‎

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
From ee9f5144b93538ed8045b314973d82ae2fded391 Mon Sep 17 00:00:00 2001
2+
From: Longsheng Mou <[email protected]>
3+
Date: Mon, 3 Nov 2025 09:47:34 +0800
4+
Subject: [PATCH 2/6] [mlir][emitc] Fix emitc.for verification crash (#163754)
5+
6+
This PR adds block arguments check to prevent a crash in `emitc.for`
7+
verifier. Fixes #159950.
8+
---
9+
mlir/lib/Dialect/EmitC/IR/EmitC.cpp | 4 +++
10+
mlir/test/Dialect/EmitC/invalid_ops.mlir | 38 ++++++++++++++++++++++++
11+
2 files changed, 42 insertions(+)
12+
13+
diff --git a/mlir/lib/Dialect/EmitC/IR/EmitC.cpp b/mlir/lib/Dialect/EmitC/IR/EmitC.cpp
14+
index 4754f0bfe895..e3cdc1e08d36 100644
15+
--- a/mlir/lib/Dialect/EmitC/IR/EmitC.cpp
16+
+++ b/mlir/lib/Dialect/EmitC/IR/EmitC.cpp
17+
@@ -584,6 +584,10 @@ void ForOp::print(OpAsmPrinter &p) {
18+
LogicalResult ForOp::verifyRegions() {
19+
// Check that the body defines as single block argument for the induction
20+
// variable.
21+
+ if (getBody()->getNumArguments() != 1)
22+
+ return emitOpError("expected body to have a single block argument for the "
23+
+ "induction variable");
24+
+
25+
if (getInductionVar().getType() != getLowerBound().getType())
26+
return emitOpError(
27+
"expected induction variable to be same type as bounds and step");
28+
diff --git a/mlir/test/Dialect/EmitC/invalid_ops.mlir b/mlir/test/Dialect/EmitC/invalid_ops.mlir
29+
index 5f594fb08c43..f285196d466c 100644
30+
--- a/mlir/test/Dialect/EmitC/invalid_ops.mlir
31+
+++ b/mlir/test/Dialect/EmitC/invalid_ops.mlir
32+
@@ -876,3 +876,41 @@ func.func @test_do(%arg0 : !emitc.ptr<i32>) {
33+
34+
return
35+
}
36+
+
37+
+// -----
38+
+
39+
+func.func @test_for_none_block_argument(%arg0: index) {
40+
+ // expected-error@+1 {{expected body to have a single block argument for the induction variable}}
41+
+ "emitc.for"(%arg0, %arg0, %arg0) (
42+
+ {
43+
+ emitc.yield
44+
+ }
45+
+ ) : (index, index, index) -> ()
46+
+ return
47+
+}
48+
+
49+
+// -----
50+
+
51+
+func.func @test_for_more_than_one_block_argument(%arg0: index) {
52+
+ // expected-error@+1 {{expected body to have a single block argument for the induction variable}}
53+
+ "emitc.for"(%arg0, %arg0, %arg0) (
54+
+ {
55+
+ ^bb0(%i0 : index, %i1 : index):
56+
+ emitc.yield
57+
+ }
58+
+ ) : (index, index, index) -> ()
59+
+ return
60+
+}
61+
+
62+
+// -----
63+
+
64+
+func.func @test_for_unmatch_type(%arg0: index) {
65+
+ // expected-error@+1 {{expected induction variable to be same type as bounds}}
66+
+ "emitc.for"(%arg0, %arg0, %arg0) (
67+
+ {
68+
+ ^bb0(%i0 : f32):
69+
+ emitc.yield
70+
+ }
71+
+ ) : (index, index, index) -> ()
72+
+ return
73+
+}
74+
--
75+
2.52.0
76+

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