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jakubcabaljakubcabal
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Merge branch 'cabal_mfb_switch' into 'devel'
feat(mfb_tools): add new MFB_SWITCH_SIMPLE module See merge request ndk/ndk-fpga!254
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‎comp/mfb_tools/flow/metadata_extractor/metadata_extractor.vhd

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generic map(
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ITEMS => MVB_ITEMS ,
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ITEM_WIDTH => MFB_META_WIDTH,
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FAKE_PIPE => (not OUT_MFB_PIPE_EN),
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FAKE_PIPE => (not OUT_MVB_PIPE_EN),
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USE_DST_RDY => true ,
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OPT => "SRL" ,
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DEVICE => DEVICE

‎comp/mfb_tools/flow/switch_simple/Modules.tcl

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# Modules.tcl: Components include script
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# Copyright (C) 2025 CESNET
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# Author(s): Jakub Cabal <[email protected]>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# Set paths
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set MFB_FIFOX_BASE "$OFM_PATH/comp/mfb_tools/storage/fifox"
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set MFB_SPLITTER_BASE "$OFM_PATH/comp/mfb_tools/flow/splitter_simple"
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set MFB_MERGER_BASE "$OFM_PATH/comp/mfb_tools/flow/merger_simple"
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# Packages
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lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
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lappend PACKAGES "$OFM_PATH/comp/base/pkg/type_pack.vhd"
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# Components
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lappend COMPONENTS [ list "MFB_FIFOX" $MFB_FIFOX_BASE "FULL" ]
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lappend COMPONENTS [ list "MFB_SPLITTER" $MFB_SPLITTER_BASE "FULL" ]
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lappend COMPONENTS [ list "MFB_MERGER" $MFB_MERGER_BASE "FULL" ]
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# Files
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lappend MOD "$ENTITY_BASE/mfb_switch_simple.vhd"

‎comp/mfb_tools/flow/switch_simple/mfb_switch_simple.vhd

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-- mfb_switch_simple.vhd:
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-- Copyright (C) 2025 CESNET z. s. p. o.
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-- Author(s): Jakub Cabal <[email protected]>
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--
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-- SPDX-License-Identifier: BSD-3-Clause
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.type_pack.all;
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use work.math_pack.all;
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entity MFB_SWITCH_SIMPLE is
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generic (
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PORTS : natural := 2;
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REGIONS : natural := 4;
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REGION_SIZE : natural := 8;
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BLOCK_SIZE : natural := 8;
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ITEM_WIDTH : natural := 8;
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META_WIDTH : natural := 1;
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FIFO_DEPTH : natural := 512;
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-- Enable masking SOF and EOF due to switch to the other input.
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MASKING_EN : boolean := True;
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-- Maximum amount of clock periods with destination ready before
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-- it tries to switch to the other input.
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CNT_MAX : integer := 64;
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-- FPGA device name: ULTRASCALE, STRATIX10, AGILEX, ...
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DEVICE : string := "AGILEX"
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);
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port (
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-- =====================================================================
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-- Clock and Reset
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-- =====================================================================
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CLK : in std_logic;
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RESET : in std_logic;
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-- =====================================================================
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-- Multiple input MFB interfaces
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-- =====================================================================
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RX_MFB_SEL : in slv_array_t(PORTS-1 downto 0)(REGIONS*max(1,log2(PORTS))-1 downto 0); -- valid with SOF
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RX_MFB_META : in slv_array_t(PORTS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0);
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RX_MFB_DATA : in slv_array_t(PORTS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
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RX_MFB_SOF : in slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0);
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RX_MFB_EOF : in slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0);
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RX_MFB_SOF_POS : in slv_array_t(PORTS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0);
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RX_MFB_EOF_POS : in slv_array_t(PORTS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0);
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RX_MFB_SRC_RDY : in std_logic_vector(PORTS-1 downto 0);
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RX_MFB_DST_RDY : out std_logic_vector(PORTS-1 downto 0);
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-- =====================================================================
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-- Multiple output MFB interfaces
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-- =====================================================================
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TX_MFB_META : out slv_array_t(PORTS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0);
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TX_MFB_DATA : out slv_array_t(PORTS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
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TX_MFB_SOF : out slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0);
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TX_MFB_EOF : out slv_array_t(PORTS-1 downto 0)(REGIONS-1 downto 0);
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TX_MFB_SOF_POS : out slv_array_t(PORTS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0);
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TX_MFB_EOF_POS : out slv_array_t(PORTS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0);
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TX_MFB_SRC_RDY : out std_logic_vector(PORTS-1 downto 0);
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TX_MFB_DST_RDY : in std_logic_vector(PORTS-1 downto 0)
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);
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end entity;
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architecture FULL of MFB_SWITCH_SIMPLE is
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constant SW_PATHS : natural := 2**PORTS;
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signal sw_mfb_meta_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0);
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signal sw_mfb_data_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
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signal sw_mfb_sof_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS-1 downto 0);
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signal sw_mfb_eof_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS-1 downto 0);
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signal sw_mfb_sof_pos_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0);
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signal sw_mfb_eof_pos_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0);
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signal sw_mfb_src_rdy_arr : std_logic_vector(SW_PATHS-1 downto 0);
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signal sw_mfb_dst_rdy_arr : std_logic_vector(SW_PATHS-1 downto 0);
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signal fo_mfb_meta_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0);
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signal fo_mfb_data_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
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signal fo_mfb_sof_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS-1 downto 0);
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signal fo_mfb_eof_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS-1 downto 0);
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signal fo_mfb_sof_pos_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0);
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signal fo_mfb_eof_pos_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0);
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signal fo_mfb_src_rdy_arr : std_logic_vector(SW_PATHS-1 downto 0);
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signal fo_mfb_dst_rdy_arr : std_logic_vector(SW_PATHS-1 downto 0);
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signal mx_mfb_meta_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0);
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signal mx_mfb_data_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
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signal mx_mfb_sof_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS-1 downto 0);
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signal mx_mfb_eof_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS-1 downto 0);
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signal mx_mfb_sof_pos_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*max(1, log2(REGION_SIZE))-1 downto 0);
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signal mx_mfb_eof_pos_arr : slv_array_t(SW_PATHS-1 downto 0)(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0);
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signal mx_mfb_src_rdy_arr : std_logic_vector(SW_PATHS-1 downto 0);
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signal mx_mfb_dst_rdy_arr : std_logic_vector(SW_PATHS-1 downto 0);
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begin
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en_g: if PORTS > 1 generate
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input_g : for ii in 0 to PORTS-1 generate
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split_i : entity work.MFB_SPLITTER_SIMPLE_GEN
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generic map (
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SPLITTER_OUTPUTS => PORTS,
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REGIONS => REGIONS,
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REGION_SIZE => REGION_SIZE,
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BLOCK_SIZE => BLOCK_SIZE,
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ITEM_WIDTH => ITEM_WIDTH,
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META_WIDTH => META_WIDTH,
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DEVICE => DEVICE
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)
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port map (
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CLK => CLK,
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RESET => RESET,
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RX_MFB_SEL => RX_MFB_SEL(ii),
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RX_MFB_META => RX_MFB_META(ii),
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RX_MFB_DATA => RX_MFB_DATA(ii),
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RX_MFB_SOF => RX_MFB_SOF(ii),
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RX_MFB_EOF => RX_MFB_EOF(ii),
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RX_MFB_SOF_POS => RX_MFB_SOF_POS(ii),
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RX_MFB_EOF_POS => RX_MFB_EOF_POS(ii),
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RX_MFB_SRC_RDY => RX_MFB_SRC_RDY(ii),
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RX_MFB_DST_RDY => RX_MFB_DST_RDY(ii),
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TX_MFB_META => sw_mfb_meta_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_DATA => sw_mfb_data_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_SOF => sw_mfb_sof_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_EOF => sw_mfb_eof_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_SOF_POS => sw_mfb_sof_pos_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_EOF_POS => sw_mfb_eof_pos_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_SRC_RDY => sw_mfb_src_rdy_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_DST_RDY => sw_mfb_dst_rdy_arr((ii+1)*PORTS-1 downto ii*PORTS)
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);
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end generate;
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fifo_g : for ii in 0 to SW_PATHS-1 generate
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fifo_i : entity work.MFB_FIFOX
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generic map (
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REGIONS => REGIONS,
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REGION_SIZE => REGION_SIZE,
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BLOCK_SIZE => BLOCK_SIZE,
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ITEM_WIDTH => ITEM_WIDTH,
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META_WIDTH => META_WIDTH,
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FIFO_DEPTH => FIFO_DEPTH,
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RAM_TYPE => "AUTO",
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DEVICE => DEVICE
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)
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port map (
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CLK => CLK,
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RST => RESET,
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RX_DATA => sw_mfb_data_arr(ii),
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RX_META => sw_mfb_meta_arr(ii),
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RX_SOF_POS => sw_mfb_sof_pos_arr(ii),
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RX_EOF_POS => sw_mfb_eof_pos_arr(ii),
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RX_SOF => sw_mfb_sof_arr(ii),
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RX_EOF => sw_mfb_eof_arr(ii),
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RX_SRC_RDY => sw_mfb_src_rdy_arr(ii),
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RX_DST_RDY => sw_mfb_dst_rdy_arr(ii),
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TX_DATA => fo_mfb_data_arr(ii),
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TX_META => fo_mfb_meta_arr(ii),
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TX_SOF_POS => fo_mfb_sof_pos_arr(ii),
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TX_EOF_POS => fo_mfb_eof_pos_arr(ii),
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TX_SOF => fo_mfb_sof_arr(ii),
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TX_EOF => fo_mfb_eof_arr(ii),
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TX_SRC_RDY => fo_mfb_src_rdy_arr(ii),
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TX_DST_RDY => fo_mfb_dst_rdy_arr(ii)
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);
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end generate;
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matrix_g : for ii in 0 to PORTS-1 generate
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matrix_g2 : for jj in 0 to PORTS-1 generate
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mx_mfb_data_arr(ii*PORTS+jj) <= fo_mfb_data_arr(jj*PORTS+ii);
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mx_mfb_meta_arr(ii*PORTS+jj) <= fo_mfb_meta_arr(jj*PORTS+ii);
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mx_mfb_sof_pos_arr(ii*PORTS+jj) <= fo_mfb_sof_pos_arr(jj*PORTS+ii);
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mx_mfb_eof_pos_arr(ii*PORTS+jj) <= fo_mfb_eof_pos_arr(jj*PORTS+ii);
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mx_mfb_sof_arr(ii*PORTS+jj) <= fo_mfb_sof_arr(jj*PORTS+ii);
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mx_mfb_eof_arr(ii*PORTS+jj) <= fo_mfb_eof_arr(jj*PORTS+ii);
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mx_mfb_src_rdy_arr(ii*PORTS+jj) <= fo_mfb_src_rdy_arr(jj*PORTS+ii);
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fo_mfb_dst_rdy_arr(jj*PORTS+ii) <= mx_mfb_dst_rdy_arr(ii*PORTS+jj);
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end generate;
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end generate;
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output_g : for ii in 0 to PORTS-1 generate
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merge_i : entity work.MFB_MERGER_SIMPLE_GEN
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generic map (
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MERGER_INPUTS => PORTS,
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MFB_REGIONS => REGIONS,
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MFB_REGION_SIZE => REGION_SIZE,
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MFB_BLOCK_SIZE => BLOCK_SIZE,
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MFB_ITEM_WIDTH => ITEM_WIDTH,
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MFB_META_WIDTH => META_WIDTH,
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MASKING_EN => MASKING_EN,
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CNT_MAX => CNT_MAX
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)
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port map (
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CLK => CLK,
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RST => RESET,
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RX_MFB_META => mx_mfb_meta_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_DATA => mx_mfb_data_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_SOF => mx_mfb_sof_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_EOF => mx_mfb_eof_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_SOF_POS => mx_mfb_sof_pos_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_EOF_POS => mx_mfb_eof_pos_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_SRC_RDY => mx_mfb_src_rdy_arr((ii+1)*PORTS-1 downto ii*PORTS),
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RX_MFB_DST_RDY => mx_mfb_dst_rdy_arr((ii+1)*PORTS-1 downto ii*PORTS),
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TX_MFB_META => TX_MFB_META(ii),
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TX_MFB_DATA => TX_MFB_DATA(ii),
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TX_MFB_SOF => TX_MFB_SOF(ii),
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TX_MFB_EOF => TX_MFB_EOF(ii),
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TX_MFB_SOF_POS => TX_MFB_SOF_POS(ii),
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TX_MFB_EOF_POS => TX_MFB_EOF_POS(ii),
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TX_MFB_SRC_RDY => TX_MFB_SRC_RDY(ii),
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TX_MFB_DST_RDY => TX_MFB_DST_RDY(ii)
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);
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end generate;
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else generate
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TX_MFB_META <= RX_MFB_META;
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TX_MFB_DATA <= RX_MFB_DATA;
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TX_MFB_SOF <= RX_MFB_SOF;
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TX_MFB_EOF <= RX_MFB_EOF;
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TX_MFB_SOF_POS <= RX_MFB_SOF_POS;
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TX_MFB_EOF_POS <= RX_MFB_EOF_POS;
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TX_MFB_SRC_RDY <= RX_MFB_SRC_RDY;
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RX_MFB_DST_RDY <= TX_MFB_DST_RDY;
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end generate;
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end architecture;

‎comp/mfb_tools/flow/switch_simple/synth/Makefile

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# Makefile: Makefile to compile module
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# Copyright (C) 2025 CESNET z. s. p. o.
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# Author(s): Jakub Cabal <[email protected]>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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TOP_LEVEL_ENT=MFB_SWITCH_SIMPLE
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SYNTH=quartus
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.PHONY: all
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all: comp
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include ../../../../../build/Makefile

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