diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h new file mode 100644 index 00000000000..f985d4b2f26 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h @@ -0,0 +1,371 @@ +/*! + \file gd32f30x_adc.h + \brief definitions for the ADC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_ADC_H +#define GD32F30X_ADC_H + +#include "gd32f30x.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x400U) +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define ADC2 (ADC_BASE + 0x1800U) +#endif + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */ + + +/* constants definitions */ +/* adc_stat register value */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + +#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* adc_ctl1 register value */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< timer 2 CC0 event select */ +#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< timer 1 CC2 event select */ +#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< timer 7 CC0 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< timer 7 TRGO event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< timer 4 CC0 event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ + +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ +#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< timer 1 CC0 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< timer 2 CC3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< timer 3 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< timer 7 CC3 event select */ +#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ +#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< timer 3 CC2 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< timer 7 CC1 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< timer 7 CC3 event select */ +#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< timer 4 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< timer 4 CC3 event select */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* adc_ovsampctl register value */ +#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ +#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ + +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ + +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); + +/* configure the ADC mode */ +void adc_mode_config(uint32_t mode); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); + +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); + +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); + +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); +#endif /* GD32F30X_ADC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h new file mode 100644 index 00000000000..5fb2b6f11c4 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h @@ -0,0 +1,218 @@ +/*! + \file gd32f30x_bkp.h + \brief definitions for the BKP +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#ifndef GD32F30X_BKP_H +#define GD32F30X_BKP_H + +#include "gd32f30x.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ +#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ +#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ +#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ +#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ +#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ +#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ +#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ +#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ +#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ +#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ +#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ +#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ +#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ +#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ +#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ +#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ +#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ +#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ +#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ +#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ +#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ +#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ +#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ +#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ +#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ +#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ +#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ +#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ +#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ +#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ +#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ +#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ +#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ +#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */ +#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) +#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* RTC clock output selection */ +#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */ +#define RTC_CLOCK_DIV_1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */ + +/* RTC clock calibration direction */ +#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ +#define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ + +/* BKP data register number */ +typedef enum +{ + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ + BKP_DATA_10, /*!< BKP data register 10 */ + BKP_DATA_11, /*!< BKP data register 11 */ + BKP_DATA_12, /*!< BKP data register 12 */ + BKP_DATA_13, /*!< BKP data register 13 */ + BKP_DATA_14, /*!< BKP data register 14 */ + BKP_DATA_15, /*!< BKP data register 15 */ + BKP_DATA_16, /*!< BKP data register 16 */ + BKP_DATA_17, /*!< BKP data register 17 */ + BKP_DATA_18, /*!< BKP data register 18 */ + BKP_DATA_19, /*!< BKP data register 19 */ + BKP_DATA_20, /*!< BKP data register 20 */ + BKP_DATA_21, /*!< BKP data register 21 */ + BKP_DATA_22, /*!< BKP data register 22 */ + BKP_DATA_23, /*!< BKP data register 23 */ + BKP_DATA_24, /*!< BKP data register 24 */ + BKP_DATA_25, /*!< BKP data register 25 */ + BKP_DATA_26, /*!< BKP data register 26 */ + BKP_DATA_27, /*!< BKP data register 27 */ + BKP_DATA_28, /*!< BKP data register 28 */ + BKP_DATA_29, /*!< BKP data register 29 */ + BKP_DATA_30, /*!< BKP data register 30 */ + BKP_DATA_31, /*!< BKP data register 31 */ + BKP_DATA_32, /*!< BKP data register 32 */ + BKP_DATA_33, /*!< BKP data register 33 */ + BKP_DATA_34, /*!< BKP data register 34 */ + BKP_DATA_35, /*!< BKP data register 35 */ + BKP_DATA_36, /*!< BKP data register 36 */ + BKP_DATA_37, /*!< BKP data register 37 */ + BKP_DATA_38, /*!< BKP data register 38 */ + BKP_DATA_39, /*!< BKP data register 39 */ + BKP_DATA_40, /*!< BKP data register 40 */ + BKP_DATA_41, /*!< BKP data register 41 */ +}bkp_data_register_enum; + +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_write_data(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_read_data(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* RTC output selection */ +void bkp_rtc_output_select(uint16_t outputsel); +/* RTC clock output selection */ +void bkp_rtc_clock_output_select(uint16_t clocksel); +/* RTC clock calibration direction */ +void bkp_rtc_clock_calibration_direction(uint16_t direction); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); +/* enable tamper pin interrupt */ +void bkp_tamper_interrupt_enable(void); +/* disable tamper pin interrupt */ +void bkp_tamper_interrupt_disable(void); + +/* flag functions */ +/* get BKP flag state */ +FlagStatus bkp_flag_get(uint16_t flag); +/* clear BKP flag state */ +void bkp_flag_clear(uint16_t flag); +/* get BKP interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(uint16_t flag); +/* clear BKP interrupt flag state */ +void bkp_interrupt_flag_clear(uint16_t flag); + +#endif /* GD32F30X_BKP_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h new file mode 100644 index 00000000000..c000ee38f56 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h @@ -0,0 +1,684 @@ +/*! + \file gd32f30x_can.h + \brief definitions for the CAN +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_CAN_H +#define GD32F30X_CAN_H + +#include "gd32f30x.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive fifo mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD BITS(0,31) /*!< filter data */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum +{ + /* flags in TSTAT register */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +}can_flag_enum; + +/* CAN interrupt flags */ +typedef enum +{ + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ +}can_interrupt_flag_enum; + +/* CAN initiliaze parameters struct */ +typedef struct +{ + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus auto_retrans; /*!< automatic retransmission mode */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +}can_parameter_struct; + +/* CAN transmit message struct */ +typedef struct +{ + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +}can_trasnmit_message_struct; + +/* CAN receive message struct */ +typedef struct +{ + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters struct */ +typedef struct +{ + uint16_t filter_list_high; /*!< filter list number high bits*/ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +}can_filter_parameter_struct; + +/* CAN errors */ +typedef enum +{ + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +}can_error_enum; + +/* transmit states */ +typedef enum +{ + CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ +}can_transmit_state_enum; + +/* CAN baudrate prescaler*/ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1*/ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2*/ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width*/ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode*/ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number*/ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier*/ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier*/ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier*/ +#define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) + +/* receive mailbox standrad identifier*/ +#define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) + +/* receive data length */ +#define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) + +/* the index of the filter by which the frame is passed */ +#define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 0 */ +#define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 1 */ +#define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 2 */ +#define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 3 */ +#define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* receive data byte 4 */ +#define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 5 */ +#define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 6 */ +#define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 7 */ +#define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive fifo */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive fifo */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN */ +#ifdef GD_MBED_USED +ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); +#else +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); +#endif +/* CAN filter init */ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); + +/* set can1 fliter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time triggle mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time triggle mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); +/* CAN release fifo */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32F30X_CAN_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h new file mode 100644 index 00000000000..15996710f5e --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h @@ -0,0 +1,55 @@ +/*! + \file gd32f30x_crc.h + \brief definitions for the CRC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_CRC_H +#define GD32F30X_CRC_H + +#include "gd32f30x.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register to the value of initializaiton data register */ +void crc_data_register_reset(void); +/* read the data register */ +uint32_t crc_data_register_read(void); + +/* read the free data register */ +uint8_t crc_free_data_register_read(void); +/* write the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* CRC calculate a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* CRC calculate a 32-bit data array */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F30X_CRC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h new file mode 100644 index 00000000000..7b629592ce6 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h @@ -0,0 +1,161 @@ +/*! + \file gd32f30x_ctc.h + \brief definitions for the CTC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_CTC_H +#define GD32F30X_CTC_H + +#include "gd32f30x.h" + +/* CTC definitions */ +#define CTC CTC_BASE + +/* registers definitions */ +#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ +#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ +#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ +#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ + +/* bits definitions */ +/* CTC_CTL0 */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ +#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ +#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ +#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ +#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ +#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ + +/* CTC_CTL1 */ +#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ +#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + +/* CTC_STAT */ +#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ +#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ +#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ +#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ +#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ +#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ +#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ +#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + +/* CTC_INTC */ +#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ +#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ +#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ +#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ + +/* constants definitions */ +/* hardware automatically trim mode definitions */ +#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ +#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ + +/* reference signal source polarity definitions */ +#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ +#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + +/* reference signal source selection definitions */ +#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ +#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ +#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBDSOF or USBFSSOF selected */ + +/* reference signal source prescaler definitions */ +#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ +#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ +#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ +#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ +#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ +#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ +#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ +#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ + +/* CTC interrupt enable definitions */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ + +/* CTC interrupt source definitions */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ + +/* CTC flag definitions */ +#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ +#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ +#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ +#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ +#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ + +/* function declarations */ +/* reset ctc clock trim controller */ +void ctc_deinit(void); + +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t ctc_interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t ctc_interrupt); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t ctc_interrupt); + +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t ctc_flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t ctc_flag); + +/* configure the IRC48M trim value */ +void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value); +/* generate software reference source sync pulse */ +void ctc_software_refsource_pulse_generate(void); +/* configure hardware automatically trim mode */ +void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode); + +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); + +/* configure reference signal source polarity */ +void ctc_refsource_polarity_config(uint32_t ctc_polarity); +/* select reference signal source */ +void ctc_refsource_signal_select(uint32_t ctc_refs); +/* configure reference signal source prescaler */ +void ctc_refsource_prescaler_config(uint32_t ctc_prescaler); +/* configure clock trim base limit value */ +void ctc_clock_limit_value_config(uint8_t ctc_limit_value); +/* configure CTC counter reload value */ +void ctc_counter_reload_value_config(uint16_t ctc_reload_value); + +/* read CTC counter capture value when reference sync pulse occurred */ +uint16_t ctc_counter_capture_value_read(void); +/* read CTC trim counter direction when reference sync pulse occurred */ +FlagStatus ctc_counter_direction_read(void); +/* read CTC counter reload value */ +uint16_t ctc_counter_reload_value_read(void); +/* read the IRC48M trim value */ +uint8_t ctc_irc48m_trim_value_read(void); + +#endif /* GD32F30X_CTC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h new file mode 100644 index 00000000000..1def29f25f2 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h @@ -0,0 +1,220 @@ +/*! + \file gd32f30x_dac.h + \brief definitions for the DAC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_DAC_H +#define GD32F30X_DAC_H + +#include "gd32f30x.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#elif defined(GD32F30X_CL) +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ + +/* function declarations */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); + +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); + +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); + +#endif /* GD32F30X_DAC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h new file mode 100644 index 00000000000..60a38f705e6 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h @@ -0,0 +1,119 @@ +/*! + \file gd32f30x_dbg.h + \brief definitions for the DBG +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_DBG_H +#define GD32F30X_DBG_H + +#include "gd32f30x.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ +#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ +#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL0_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL0_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL0_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL0_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL0_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL0_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F30X_CL +#define DBG_CTL0_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD +#define DBG_CTL0_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ +#define DBG_CTL0_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ +#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ +#define DBG_CTL0_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ +#define DBG_CTL0_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ +#define DBG_CTL0_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F30X_HD */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +typedef enum +{ + DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F30X_CL + DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD + DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F30X_HD */ +}dbg_periph_enum; + +#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) +#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ +#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ +#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ +#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ + +/* function declarations */ +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +/* enable trace pin assignment */ +void dbg_trace_pin_enable(void); +/* disable trace pin assignment */ +void dbg_trace_pin_disable(void); +/* set trace pin mode */ +void dbg_trace_pin_mode_set(uint32_t trace_mode); + +#endif /* GD32F30X_DBG_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h new file mode 100644 index 00000000000..d80444706f8 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h @@ -0,0 +1,265 @@ +/*! + \file gd32f30x_dma.h + \brief definitions for the DMA +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_DMA_H +#define GD32F30X_DMA_H + +#include "gd32f30x.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL, x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT,x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR,x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6 /*!< DMA Channel6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + +} dma_parameter_struct; + +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ +/* circular mode */ +#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ +#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ + +/* memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) +#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + + + +/* function declarations */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +#ifdef GD_MBED_USED +/* initialize DMA channel */ +void dma_para_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct); +#else +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct); +#endif +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA Memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); + +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); + +#endif /* GD32F30X_DMA_H */ + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h new file mode 100644 index 00000000000..1dabb1599a1 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h @@ -0,0 +1,1669 @@ +/*! + \file gd32f30x_enet.h + \brief definitions for the ENET +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_ENET_H +#define GD32F30X_ENET_H + +#include "gd32f30x.h" +#include + +#define IF_USE_EXTERNPHY_LIB 0 +#if (1 == IF_USE_EXTERNPHY_LIB) +#include "phy.h" +#endif + +#ifndef ENET_RXBUF_NUM +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ +#endif + +#ifndef ENET_TXBUF_NUM +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ +#endif + +#ifndef ENET_RXBUF_SIZE +#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ +#endif + +#ifndef ENET_TXBUF_SIZE +#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ +#endif + +/* #define SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* #define USE_DELAY */ + +#ifndef _PHY_H_ +#define DP83848 0 +#define LAN8700 1 +#define PHY_TYPE DP83848 + +#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ + +/* PHY read write timeouts */ +#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ +#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ + +/* PHY delay */ +#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ +#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ + +/* PHY register address */ +#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ +#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ + +/* PHY basic control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ + +#if(PHY_TYPE == LAN8700) +#define PHY_SR 31U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#elif(PHY_TYPE == DP83848) +#define PHY_SR 16U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#endif /* PHY_TYPE */ + +#endif /* _PHY_H_ */ + + +/* ENET definitions */ +#define ENET ENET_BASE + +/* registers definitions */ +#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_DBG REG32((ENET) + 0x34U) /*!< ethernet MAC debug register */ +#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ +#define ENET_PTP_TSF REG32((ENET) + 0x728U) /*!< ethernet PTP time stamp flag register */ +#define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU) /*!< ethernet PTP PPS control register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ + +/* bits definitions */ +/* ENET_MAC_CFG */ +#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ +#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ +#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ +#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ +#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ +#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ +#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ +#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ +#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ +#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ +#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ +#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ +#define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ + +/* ENET_MAC_FRMF */ +#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ +#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + +/* ENET_MAC_HLH */ +#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ + +/* ENET_MAC_HLL */ +#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ + +/* ENET_MAC_PHY_CTL */ +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + +/* ENET_MAC_PHY_DATA */ +#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ + +/* ENET_MAC_FCTL */ +#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ +#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ +#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ +#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ + +/* ENET_MAC_VLT */ +#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ +#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + +/* ENET_MAC_RWFF */ +#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ + +/* ENET_MAC_WUM */ +#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ +#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ +#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ +#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ +#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ +#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ +#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ + +/* ENET_MAC_DBG */ +#define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ +#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ +#define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ +#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ +#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ +#define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ +#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ +#define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ +#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ +#define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ +#define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ +#define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ + +/* ENET_MAC_INTF */ +#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ +#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ +#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ +#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ +#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ + +/* ENET_MAC_INTMSK */ +#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ +#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + +/* ENET_MAC_ADDR0H */ +#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ +#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + +/* ENET_MAC_ADDR0L */ +#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ + +/* ENET_MAC_ADDR1H */ +#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR1L */ +#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ + +/* ENET_MAC_ADDR2H */ +#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR2L */ +#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ + +/* ENET_MAC_ADDR3H */ +#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR3L */ +#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ + +/* ENET_MAC_FCTH */ +#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ + +/* ENET_MSC_CTL */ +#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ +#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ +#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ +#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ +#define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ +#define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ + +/* ENET_MSC_RINTF */ +#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ +#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ +#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ + +/* ENET_MSC_TINTF */ +#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ +#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ +#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ + +/* ENET_MSC_RINTMSK */ +#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ +#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ +#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ + +/* ENET_MSC_TINTMSK */ +#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + +/* ENET_MSC_SCCNT */ +#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ + +/* ENET_MSC_MSCCNT */ +#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ + +/* ENET_MSC_TGFCNT */ +#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ + +/* ENET_MSC_RFCECNT */ +#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ + +/* ENET_MSC_RFAECNT */ +#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ + +/* ENET_MSC_RGUFCNT */ +#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ + +/* ENET_PTP_TSCTL */ +#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ +#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ +#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ +#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ +#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ +#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ +#define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ +#define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ +#define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ +#define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ +#define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ +#define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ +#define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ +#define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ +#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ +#define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ + +/* ENET_PTP_SSINC */ +#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ + +/* ENET_PTP_TSH */ +#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ + +/* ENET_PTP_TSL */ +#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ +#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + +/* ENET_PTP_TSUH */ +#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ + +/* ENET_PTP_TSUL */ +#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ +#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + +/* ENET_PTP_TSADDEND */ +#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ + +/* ENET_PTP_ETH */ +#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ + +/* ENET_PTP_ETL */ +#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ + +/* ENET_PTP_TSF */ +#define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ +#define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ + +/* ENET_PTP_PPSCTL */ +#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ + +/* ENET_DMA_BCTL */ +#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ +#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ +#define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ +#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ +#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ +#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ +#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ +#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ +#define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ + +/* ENET_DMA_TPEN */ +#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ + +/* ENET_DMA_RPEN */ +#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ + +/* ENET_DMA_RDTADDR */ +#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ + +/* ENET_DMA_TDTADDR */ +#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ + +/* ENET_DMA_STAT */ +#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ +#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ +#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ +#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ +#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ +#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ +#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ +#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ +#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ +#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ +#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ +#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ +#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ +#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ +#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ +#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ +#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ +#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + +/* ENET_DMA_CTL */ +#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ +#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ +#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ +#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ +#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ +#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ +#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ +#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ +#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ +#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ + +/* ENET_DMA_INTEN */ +#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ +#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ +#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ +#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ +#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ +#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ +#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ +#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ +#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ +#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ +#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ +#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ +#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + +/* ENET_DMA_MFBOCNT */ +#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ + +/* ENET_DMA_RSWDC */ +#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ + +/* ENET_DMA_CTDADDR */ +#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ + +/* ENET_DMA_CRDADDR */ +#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ + +/* ENET_DMA_CTBADDR */ +#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ + +/* ENET_DMA_CRBADDR */ +#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ + +/* ENET DMA Tx descriptor TDES0 */ +#define ENET_TDES0_DB BIT(0) /*!< deferred */ +#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ +#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ +#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ +#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ +#define ENET_TDES0_LCO BIT(9) /*!< late collision */ +#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ +#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ +#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ +#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ +#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ +#define ENET_TDES0_ES BIT(15) /*!< error summary */ +#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ +#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ +#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ +#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ +#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ +#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ +#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ +#define ENET_TDES0_FSG BIT(28) /*!< first segment */ +#define ENET_TDES0_LSG BIT(29) /*!< last segment */ +#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ +#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + +/* ENET DMA Tx descriptor TDES1 */ +#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ + +/* ENET DMA Tx descriptor TDES2 */ +#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES3 */ +#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Tx descriptor TDES6 */ +#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES7 */ +#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* ENET DMA Rx descriptor RDES0 */ +#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ +#define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ +#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ +#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ +#define ENET_RDES0_RERR BIT(3) /*!< receive error */ +#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ +#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ +#define ENET_RDES0_LCO BIT(6) /*!< late collision */ +#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ +#define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ +#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ +#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ +#define ENET_RDES0_LERR BIT(12) /*!< length error */ +#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ +#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ +#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ +#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ +#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + +/* ENET DMA Rx descriptor RDES1 */ +#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ +#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ +#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ +#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + +/* ENET DMA Rx descriptor RDES2 */ +#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + +/* ENET DMA Rx descriptor RDES3 */ +#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Rx descriptor RDES4 */ +#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ +#define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ +#define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ +#define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ +#define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ +#define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ +#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ +#define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ +#define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ + +/* ENET DMA Rx descriptor RDES6 */ +#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ + +/* ENET DMA Rx descriptor RDES7 */ +#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* constants definitions */ +/* define bit position and its register index offset */ +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* ENET clock range judgement */ +#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) + +/* define MAC address configuration and reference address */ +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x40U) +#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) + +/* register offset */ +#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ + +#define PTP_TSF_REG_OFFSET 0x0728U /*!< PTP time stamp flag register offset */ + +#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ + +/* ENET status flag get */ +typedef enum +{ + /* ENET_MAC_WUM register */ + ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + /* ENET_MAC_FCTL register */ + ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ + /* ENET_MAC_INTF register */ + ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_PTP_TSF register */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ + ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ + ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ + ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_flag_enum; + +/* ENET stutus flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_flag_clear_enum; + +/* ENET interrupt enable/disable */ +typedef enum +{ + /* ENET_MAC_INTMSK register */ + ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ + ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ + /* ENET_MSC_RINTMSK register */ + ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ + ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ + ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ + /* ENET_MSC_TINTMSK register */ + ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ + ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ + ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ + /* ENET_DMA_INTEN register */ + ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ + ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ + ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ + ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ + ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ + ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ + ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ + ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ + ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ + ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ + ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ + ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ + ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ + ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ +}enet_int_enum; + +/* ENET interrupt flag get */ +typedef enum +{ + /* ENET_MAC_INTF register */ + ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +}enet_int_flag_enum; + +/* ENET interrupt flag clear */ +typedef enum +{ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +}enet_int_flag_clear_enum; + +/* current RX/TX descriptor/buffer/descriptor table address get */ +typedef enum +{ + ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ + ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ + ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ + ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ + ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ + ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ +}enet_desc_reg_enum; + +/* MAC statistics counter get */ +typedef enum +{ + ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ + ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ + ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ + ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ + ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ + ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ +}enet_msc_counter_enum; + +/* function option, used for ENET initialization */ +typedef enum +{ + FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ + DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ + DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ + DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ + STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ + DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ + VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ + FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ + HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ + HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ + FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ + HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ + TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ + INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ +}enet_option_enum; + +/* phy mode and mac loopback configurations */ +typedef enum +{ + ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ + ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ + ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ + ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ + ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ +}enet_mediamode_enum; + +/* IP frame checksum function */ +typedef enum +{ + ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ + ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped */ +}enet_chksumconf_enum; + +/* received frame filter function */ +typedef enum +{ + ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ + ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ +}enet_frmrecept_enum; + +/* register group value get */ +typedef enum +{ + ALL_MAC_REG = 0, /*!< MAC register group */ + ALL_MSC_REG = 22, /*!< MSC register group */ + ALL_PTP_REG = 33, /*!< PTP register group */ + ALL_DMA_REG = 44, /*!< DMA register group */ +}enet_registers_type_enum; + +/* dma direction select */ +typedef enum +{ + ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ + ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ +}enet_dmadirection_enum; + +/* PHY operation direction select */ +typedef enum +{ + ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ + ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ +}enet_phydirection_enum; + +/* register operation direction select */ +typedef enum +{ + ENET_REG_READ, /*!< read register */ + ENET_REG_WRITE /*!< write register */ +}enet_regdirection_enum; + +/* ENET MAC addresses */ +typedef enum +{ + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ +}enet_macaddress_enum; + +/* descriptor information */ +typedef enum +{ + TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ + TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ + RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ + RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ + RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ + RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ +}enet_descstate_enum; + +/* MSC counters preset mode */ +typedef enum +{ + ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ + ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ + ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ +}enet_msc_preset_enum; + +/* structure for initialization of the ENET */ +typedef struct +{ + uint32_t option_enable; /*!< select which function to configure */ + uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ + uint32_t dma_maxburst; /*!< DMA max burst related parameters */ + uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ + uint32_t store_forward_mode; /*!< store forward mode related parameters */ + uint32_t dma_function; /*!< DMA control related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t flow_control; /*!< flow control related parameters */ + uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ + uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ + uint32_t framesfilter_mode; /*!< frame filter control related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t timer_config; /*!< frame timer related parameters */ + uint32_t interframegap; /*!< inter frame gap related parameters */ +}enet_initpara_struct; + +/* structure for ENET DMA desciptors */ +typedef struct +{ + uint32_t status; /*!< status */ + uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ + uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ + uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + uint32_t extended_status; /*!< extended status */ + uint32_t reserved; /*!< reserved */ + uint32_t timestamp_low; /*!< timestamp low */ + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +} enet_descriptors_struct; + +/* structure of PTP system time */ +typedef struct +{ + uint32_t second; /*!< second of system time */ + uint32_t nanosecond; /*!< nanosecond of system time */ + uint32_t sign; /*!< sign of system time */ +}enet_ptp_systime_struct; + +/* mac_cfg register value */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ +#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ +#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ +#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ +#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ +#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ + +#define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ + +#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ +#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ + +#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ +#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ + +#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ +#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ + +#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ +#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ + +#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ +#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ + +#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ +#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ + +#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ +#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ + +#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ +#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ + +#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ +#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ + +#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ +#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ +#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ + +#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ +#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + +/* mac_frmf register value */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ +#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ +#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ +#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ + +#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ +#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ + +#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ +#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ +#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ +#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ +#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ + +#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ +#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ + +#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ + +#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ +#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ + +#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ +#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ +#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ +#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ +#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ +#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ +#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ + +#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ +#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ +#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ +#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + +/* mac_phy_ctl register value */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ +#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ + +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + +/* mac_phy_data register value */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + +/* mac_fctl register value */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ +#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ +#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ + +#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ + +#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ +#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ + +#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ +#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ +#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ + +#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ + +#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ +/* mac_vlt register value */ +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + +#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ +#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + +/* mac_wum register value */ +#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ +#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ +#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + +/* mac_dbg register value */ +#define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ +#define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ +#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ +#define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ +#define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ +#define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ +#define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ +#define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ +#define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ +#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ +#define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ +#define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ + +#define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ + +#define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ + +#define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ + +#define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ + +#define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ + +/* mac_addr0h register value */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + +/* mac_addrxh register value, x = 1,2,3 */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + +#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ +#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ +#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ +#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ + +#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + +/* mac_fcth register value */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ +#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ +#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ +#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ +#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ +#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ +#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ +#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ +#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ + +/* msc_ctl register value */ +#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ +#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ +#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + +/* ptp_tsctl register value */ +#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ + +#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ +#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ +#define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ +#define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ +#define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ +#define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ +#define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ + +/* ptp_ssinc register value */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + +/* ptp_tsl register value */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + +/* ptp_tsul register value */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + +/* ptp_ppsctl register value */ +#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ +#define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ +#define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ +#define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ +#define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ +#define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ +#define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ +#define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ +#define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ +#define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ +#define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ +#define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ +#define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ +#define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ +#define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ +#define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ +#define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ + +/* dma_bctl register value */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ +#define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ + +#define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ +#define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ + +/* dma_stat register value */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ +#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ +#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ +#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ +#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ + +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ +#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ +#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ +#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ +#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ + +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ +#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ +#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + +/* dma_ctl register value */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ +#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ +#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ +#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ +#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ +#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ +#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ +#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ +#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ + +#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ + +#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ + +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ + +#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ + +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ + +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ + +#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ + +/* dma_mfbocnt register value */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ + +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + +/* dma_rswdc register value */ +#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ + +/* dma tx descriptor tdes0 register value */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + +/* dma tx descriptor tdes1 register value */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + +/* dma rx descriptor rdes0 register value */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + +/* dma rx descriptor rdes1 register value */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ + +#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ + +#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + +/* dma rx descriptor rdes4 register value */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + +/* ENET register mask value */ +#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ +#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ +#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ +#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ +#define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */ +#define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */ +#else +#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + +typedef enum{ + ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ + ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ + ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ + ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ + ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ + ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ + ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ + ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ + ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ + ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ + ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ + ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ + ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ +}enet_ptp_function_enum; + + +/* ENET remote wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ + +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ + +/* ENET delay timeout */ +#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ +#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ + + + +/* function declarations */ +/* main function */ +/* deinitialize the ENET, and reset structure parameters for ENET initialization */ +void enet_deinit(void); +/* configure the parameters which are usually less cared for initialization */ +void enet_initpara_config(enet_option_enum option, uint32_t para); +/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); +/* reset all core internal registers located in CLK_TX and CLK_RX */ +ErrStatus enet_software_reset(void); +/* check receive frame valid and return frame size */ +uint32_t enet_rxframe_size_get(void); +/* initialize the dma tx/rx descriptors's parameters in chain mode */ +void enet_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma tx/rx descriptors's parameters in ring mode */ +void enet_descriptors_ring_init(enet_dmadirection_enum direction); +/* handle current received frame data to application buffer */ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); +/* handle current received frame but without data copy to application buffer */ +#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) +/* handle application buffer data to transmit it */ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); +/* handle current transmit frame but without data copy from application buffer */ +#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) +/* configure the transmit IP frame checksum offload calculation and insertion */ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); +/* ENET Tx and Rx function enable (include MAC and DMA module) */ +void enet_enable(void); +/* ENET Tx and Rx function disable (include MAC and DMA module) */ +void enet_disable(void); +/* configure MAC address */ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); +/* get MAC address */ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); + +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + +/* MAC function */ +/* ENET Tx function enable (include MAC and DMA module) */ +void enet_tx_enable(void); +/* ENET Tx function disable (include MAC and DMA module) */ +void enet_tx_disable(void); +/* ENET Rx function enable (include MAC and DMA module) */ +void enet_rx_enable(void); +/* ENET Rx function disable (include MAC and DMA module) */ +void enet_rx_disable(void); +/* put registers value into the application buffer */ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); +/* get the enet debug status from the debug register */ +uint32_t enet_debug_status_get(uint32_t mac_debug); +/* enable the MAC address filter */ +void enet_address_filter_enable(enet_macaddress_enum mac_addr); +/* disable the MAC address filter */ +void enet_address_filter_disable(enet_macaddress_enum mac_addr); +/* configure the MAC address filter */ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); +/* PHY interface configuration (configure SMI clock and reset PHY chip) */ +ErrStatus enet_phy_config(void); +/* write to/read from a PHY register */ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); +/* enable the loopback function of phy chip */ +ErrStatus enet_phyloopback_enable(void); +/* disable the loopback function of phy chip */ +ErrStatus enet_phyloopback_disable(void); +/* enable ENET forward feature */ +void enet_forward_feature_enable(uint32_t feature); +/* disable ENET forward feature */ +void enet_forward_feature_disable(uint32_t feature); +/* enable ENET fliter feature */ +void enet_fliter_feature_enable(uint32_t feature); +/* disable ENET fliter feature */ +void enet_fliter_feature_disable(uint32_t feature); + +/* flow control function */ +/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ +ErrStatus enet_pauseframe_generate(void); +/* configure the pause frame detect type */ +void enet_pauseframe_detect_config(uint32_t detect); +/* configure the pause frame parameters */ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); +/* configure the threshold of the flow control(deactive and active threshold) */ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); +/* enable ENET flow control feature */ +void enet_flowcontrol_feature_enable(uint32_t feature); +/* disable ENET flow control feature */ +void enet_flowcontrol_feature_disable(uint32_t feature); + +/* DMA function */ +/* get the dma transmit/receive process state */ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +/* poll the dma transmission/reception enable */ +void enet_dmaprocess_resume(enet_dmadirection_enum direction); +/* check and recover the Rx process */ +void enet_rxprocess_check_recovery(void); +/* flush the ENET transmit fifo, and wait until the flush operation completes */ +ErrStatus enet_txfifo_flush(void); +/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); +/* get the Tx or Rx descriptor information */ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); +/* get the number of missed frames during receiving */ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); + +/* descriptor function */ +/* get the bit flag of ENET dma descriptor */ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); +/* set the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); +/* clear the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); +/* drop current receive frame */ +void enet_rxframe_drop(void); +/* enable DMA feature */ +void enet_dma_feature_enable(uint32_t feature); +/* disable DMA feature */ +void enet_dma_feature_disable(uint32_t feature); + + +/* special enhanced mode function */ +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* get the bit of extended status flag in ENET DMA descriptor */ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); +/* configure descriptor to work in enhanced mode */ +void enet_desc_select_enhanced_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); +/* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) + +#else + +/* configure descriptor to work in normal mode */ +void enet_desc_select_normal_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* WUM function */ +/* wakeup frame filter register pointer reset */ +void enet_wum_filter_register_pointer_reset(void); +/* set the remote wakeup frame registers */ +void enet_wum_filter_config(uint32_t pdata[]); +/* enable wakeup management features */ +void enet_wum_feature_enable(uint32_t feature); +/* disable wakeup management features */ +void enet_wum_feature_disable(uint32_t feature); + +/* MSC function */ +/* reset the MAC statistics counters */ +void enet_msc_counters_reset(void); +/* enable the MAC statistics counter features */ +void enet_msc_feature_enable(uint32_t feature); +/* disable the MAC statistics counter features */ +void enet_msc_feature_disable(uint32_t feature); +/* configure MAC statistics counters preset mode */ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode); +/* get MAC statistics counter */ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); + +/* PTP function */ +/* change subsecond to nanosecond */ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); +/* change nanosecond to subsecond */ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); +/* enable the PTP features */ +void enet_ptp_feature_enable(uint32_t feature); +/* disable the PTP features */ +void enet_ptp_feature_disable(uint32_t feature); +/* configure the PTP timestamp function */ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); +/* configure the PTP system time subsecond increment value */ +void enet_ptp_subsecond_increment_config(uint32_t subsecond); +/* adjusting the PTP clock frequency only in fine update mode */ +void enet_ptp_timestamp_addend_config(uint32_t add); +/* initializing or adding/subtracting to second of the PTP system time */ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); +/* configure the PTP expected target time */ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); +/* get the PTP current system time */ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); +/* configure the PPS output frequency */ +void enet_ptp_pps_output_frequency_config(uint32_t freq); +/* configure and start PTP timestamp counter */ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); +/* adjust frequency in fine method by configure addend register */ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); +/* update system time in coarse method */ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); +/* set system time in fine method */ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); +/* get the ptp flag status */ +FlagStatus enet_ptp_flag_get(uint32_t flag); + +/* internal function */ +/* reset the ENET initpara struct, call it before using enet_initpara_config() */ +void enet_initpara_reset(void); + +#endif /* GD32F30X_ENET_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h new file mode 100644 index 00000000000..7b76cf2a4ba --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h @@ -0,0 +1,420 @@ +/*! + \file gd32f30x_exmc.h + \brief definitions for the EXMC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#ifndef GD32F30X_EXMC_H +#define GD32F30X_EXMC_H + +#include "gd32f30x.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ + +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ + +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ + +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ + +/* NAND/PC card */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ + +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ + +/* bits definitions */ +/* EXMC_SNCTLx,x=0..3 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ +#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ + +/* EXMC_SNTCFGx,x=0..3 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_SNWTCFGx,x=0..3 */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_NPCTLx,x=1..3 */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ + +/* EXMC_NPINTENx,x=1..3 */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + +/* EXMC_NPCTCFGx,x=1..3 */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ + +/* EXMC_NPATCFGx,x=1..3 */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ + +/* EXMC_PIOTCFG3 */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ + +/* EXMC_NECCx,x=1,2 */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize struct */ +typedef struct +{ + uint32_t asyn_access_mode; /*!< asynchronous access mode */ + uint32_t syn_data_latency; /*!< configure the data latency */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize struct */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing + parameters for read if the extended mode is used */ + exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ +}exmc_norsram_parameter_struct; + +/* EXMC NAND/PC card timing initialize struct */ +typedef struct +{ + uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ + uint32_t waittime; /*!< configure the minimum wait time */ + uint32_t setuptime; /*!< configure the address setup time */ +}exmc_nand_pccard_timing_parameter_struct; + +/* EXMC NAND initialize struct */ +typedef struct +{ + uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ + uint32_t databus_width; /*!< the NAND flash databus width */ + uint32_t wait_feature; /*!< enables or disables the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +}exmc_nand_parameter_struct; + +/* EXMC PC card initialize struct */ +typedef struct +{ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t wait_feature; /*!< enables or disables the Wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ +}exmc_pccard_parameter_struct;; + + +/* EXMC_register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ + +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ + +/* CRAM page size */ +#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ +#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ +#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ +#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ +#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* asynchronous access mode */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + +/* data latency for NOR flash */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ + +/* synchronous clock divide ratio */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + +/* ECC size */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ + +/* ALE to RE delay */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + +/* CLE to RE delay */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + +/* NAND bank memory data bus width */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ + +/* EXMC NOR/SRAM write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ + +/* EXMC NWAIT signal configuration */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ + +/* EXMC NAND/PC card bank definition */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ + +/* EXMC flag bits */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ + +/* EXMC interrupt enable bits */ +#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ +#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ +#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ + +/* EXMC interrupt flag bits */ +#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ +#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ +#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ + +/* function declarations */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t exmc_norsram_region); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* CRAM page size configure */ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); +/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_enable(uint32_t exmc_norsram_region); +/* EXMC NOR/SRAM bank disable */ +void exmc_norsram_disable(uint32_t exmc_norsram_region); + + +/* deinitialize EXMC NAND bank */ +void exmc_nand_deinit(uint32_t exmc_nand_bank); +/* initialize EXMC NAND bank */ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* EXMC NAND bank enable */ +void exmc_nand_enable(uint32_t exmc_nand_bank); +/* EXMC NAND bank disable */ +void exmc_nand_disable(uint32_t exmc_nand_bank); +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); + +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* exmc_pccard_parameter_struct parameter initialize */ +void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); +/* EXMC PC card bank enable */ +void exmc_pccard_enable(void); +/* EXMC PC card bank disable */ +void exmc_pccard_disable(void); + +/* check EXMC flag is set or not */ +FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); +/* clear EXMC flag */ +void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); +/* check EXMC flag is set or not */ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source); +/* clear EXMC flag */ +void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source); +/* enable EXMC interrupt */ +void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source); +/* disable EXMC interrupt */ +void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source); + +#endif /* GD32F30X_EXMC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h new file mode 100644 index 00000000000..ec9ff47dae8 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h @@ -0,0 +1,229 @@ +/*! + \file gd32f30x_exti.h + \brief definitions for the EXTI +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_EXTI_H +#define GD32F30X_EXTI_H + +#include "gd32f30x.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum +{ + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ +}exti_line_enum; + +/* external interrupt and event */ +typedef enum +{ + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +}exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum +{ + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ +}exti_trig_type_enum; + +/* function declarations */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); + +#endif /* GD32F30X_EXTI_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h new file mode 100644 index 00000000000..0018bbd2938 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h @@ -0,0 +1,343 @@ +/*! + \file gd32f30x_fmc.h + \brief definitions for the FMC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_FMC_H +#define GD32F30X_FMC_H + +#include "gd32f30x.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ +#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ +#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ +#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ +#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ +#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ +#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ +#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY0 */ +#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT0 */ +#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL0 */ +#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ +#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ +#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ +#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ +#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR0 */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ +#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ + +/* FMC_KEY1 */ +#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ + +/* FMC_STAT1 */ +#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL1 */ +#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ +#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ +#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ +#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ +#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR1 */ +#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) +#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) + +/* configuration register */ +#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ +#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ +#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ +#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ +#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ + +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ +}fmc_state_enum; + +/* FMC interrupt enable */ +typedef enum +{ + FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ + FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ + FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ + FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ +}fmc_int_enum; + +/* FMC flags */ +typedef enum +{ + FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ + FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ + FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ + FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ + FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ + FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ + FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ + FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ +}fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum +{ + FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ + FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ +}fmc_interrupt_flag_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* FMC wait state counter */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ + +/* option bytes boot bank value */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ +#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ + +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ + +/* OB_SPC */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ + +/* OB_USER */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ + +/* OB_WP0 */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ + +/* OB_WP1 */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ + +/* OB_WP2 */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ + +/* OB_WP3 */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ + +/* FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ + +/* FMC BANK address */ +#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ +#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* unlock the FMC bank0 operation */ +void fmc_bank0_unlock(void); +/* unlock the FMC bank1 operation */ +void fmc_bank1_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* lock the bank0 FMC operation */ +void fmc_bank0_lock(void); +/* lock the bank1 FMC operation */ +void fmc_bank1_lock(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC erase whole bank0 */ +fmc_state_enum fmc_bank0_erase(void); +/* FMC erase whole bank1 */ +fmc_state_enum fmc_bank1_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* erase the option byte */ +fmc_state_enum ob_erase(void); +/* enable write protect */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure the option byte security protection */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* write the FMC option byte */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); +/* program option bytes data */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get the FMC option byte user */ +uint8_t ob_user_get(void); +/* get OB_DATA in register FMC_OBSTAT */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get option byte security protection code value */ +FlagStatus ob_spc_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* check flag is set or not */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC flag */ +void fmc_flag_clear(uint32_t flag); +/* get FMC interrupt flag state */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +/* clear FMC interrupt flag state */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); +/* return the FMC bank0 state */ +fmc_state_enum fmc_bank0_state_get(void); +/* return the FMC bank1 state */ +fmc_state_enum fmc_bank1_state_get(void); +/* check FMC bank0 ready or not */ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); +/* check FMC bank1 ready or not */ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); + +#endif /* GD32F30X_FMC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h new file mode 100644 index 00000000000..e6500bd4753 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h @@ -0,0 +1,79 @@ +/*! + \file gd32f30x_fwdgt.h + \brief definitions for the FWDGT +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_FWDGT_H +#define GD32F30X_FWDGT_H + +#include "gd32f30x.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* function declarations */ +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F30X_FWDGT_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h new file mode 100644 index 00000000000..147b47df724 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h @@ -0,0 +1,507 @@ +/*! + \file gd32f30x_gpio.h + \brief definitions for the GPIO +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_GPIO_H +#define GD32F30X_GPIO_H + +#include "gd32f30x.h" + +/* GPIOx(x=A,B,C,D,E,F,G) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) +#define GPIOF (GPIO_BASE + 0x00001400U) +#define GPIOG (GPIO_BASE + 0x00001800U) + +/* AFIO definitions */ +#define AFIO AFIO_BASE + +/* registers definitions */ +/* GPIO registers definitions */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ +#define GPIOx_SPD(gpiox) REG32((gpiox) + 0x3CU) /*!< GPIO port bit speed register */ + +/* AFIO registers definitions */ +#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ +#define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register */ + +/* bits definitions */ +/* GPIO_CTL0 */ +#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ +#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ +#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ +#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ +#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ +#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ +#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ +#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ +#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ +#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ +#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ +#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ +#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ +#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ +#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ + +/* GPIO_CTL1 */ +#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ +#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ +#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ +#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ +#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ +#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ +#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ +#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ +#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ +#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ +#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ +#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ +#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ +#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ +#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* GPIO_SPD */ +#define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ + +/* AFIO_EC */ +#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ +#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ +#define AFIO_EC_EOE BIT(7) /*!< event output enable */ + +/* AFIO_PCF0 */ +#ifdef GD32F30X_CL +/* memory map and bit definitions for GD32F30X_CL devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ +#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ +#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ +#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ +#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ +#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ + +#else +/* memory map and bit definitions for GD32F30X_HD devices and GD32F30X_XD devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ +#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#endif /* GD32F30X_CL */ + +/* AFIO_EXTISS0 */ +#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ +#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ +#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ +#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ + +/* AFIO_EXTISS1 */ +#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ +#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ +#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ +#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ + +/* AFIO_EXTISS2 */ +#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ +#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ +#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ +#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ + +/* AFIO_EXTISS3 */ +#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ +#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ +#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ +#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ + +/* AFIO_PCF1 */ +#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ +#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ +#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ +#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ +#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ +#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ +#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ + +/* AFIO_CPSCTL */ +#define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ +#define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* GPIO mode values set */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) +#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) + +/* GPIO mode definitions */ +#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ +#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ +#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ +#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ +#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ +#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ +#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ +#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ +#define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */ + +/* GPIO event output port definitions */ +#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ +#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ +#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ +#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ +#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ + +/* GPIO output port source definitions */ +#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ +#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ +#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ +#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ +#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ +#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ +#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ + +/* GPIO event output pin definitions */ +#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ +#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ +#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ +#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ +#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ +#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ +#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ +#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ +#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ +#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ +#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ +#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ +#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ +#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ +#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ +#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ + +/* GPIO output pin source definitions */ +#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ +#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ +#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ +#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ +#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ +#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ +#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ +#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ +#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ +#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ +#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ +#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ +#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ +#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ +#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ +#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO remap definitions */ +#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ +#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ +#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ +#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ +#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ +#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ +#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ +#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ +#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ +#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ +#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ +#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#endif /* GD32F30X_HD||GD32F30X_XD */ +#if (defined(GD32F30X_CL) || defined(GD32F30X_HD)) +#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F30X_CL devices and GD32F30X_HD devices) */ +#endif /* GD32F30X_CL||GD32F30X_HD */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#endif /* GD32F30X_HD||GD32F30X_XD */ +#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ +#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ +#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ +#ifdef GD32F30X_CL +#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F30X_CL devices) */ +#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F30X_CL devices) */ +#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F30X_CL devices) */ +#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F30X_CL devices) */ +#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F30X_CL devices) */ +#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) */ +#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F30X_CL devices) */ +#endif /* GD32F30X_CL */ +#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ +#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ +#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ +#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ +#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ +#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ +#define GPIO_CTC_REMAP0 ((uint32_t)0x801B0800U) /*!< CTC remapping(PD15)*/ +#define GPIO_CTC_REMAP1 ((uint32_t)0x801B1000U) /*!< CTC remapping(PF0) */ + +#ifdef GD32F30X_CL +/* ethernet MII or RMII PHY selection */ +#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ +#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ +#endif /* GD32F30X_CL */ + +/* I/O compensation cell enable/disable */ +#define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */ +#define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* reset alternate function I/O(AFIO) */ +void gpio_afio_deinit(void); +#ifdef GD_MBED_USED +/* GPIO parameter initialization */ +void gpio_para_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); +#else +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); +#endif +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* configure GPIO pin event output */ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); +/* enable GPIO pin event output */ +void gpio_event_output_enable(void); +/* disable GPIO pin event output */ +void gpio_event_output_disable(void); + +/* select GPIO pin exti sources */ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); + +#ifdef GD32F30X_CL +/* select ethernet MII or RMII PHY */ +void gpio_ethernet_phy_select(uint32_t enet_sel); +#endif /* GD32F30X_CL */ + +/* configure GPIO pin remap */ +void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue); + +/* configure the I/O compensation cell */ +void gpio_compensation_config(uint32_t compensation); +/* check the I/O compensation cell is ready or not */ +FlagStatus gpio_compensation_flag_get(void); + +#endif /* GD32F30X_GPIO_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h new file mode 100644 index 00000000000..a90a88caef3 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h @@ -0,0 +1,340 @@ +/*! + \file gd32f30x_i2c.h + \brief definitions for the I2C +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_I2C_H +#define GD32F30X_I2C_H + +#include "gd32f30x.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* I2C dual-address mode switch */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C flag definitions */ +#define I2C_FLAG_SBSEND BIT(0) /*!< start condition sent out in master mode */ +#define I2C_FLAG_ADDSEND BIT(1) /*!< address is sent in master mode or received and matches in slave mode */ +#define I2C_FLAG_BTC BIT(2) /*!< byte transmission finishes */ +#define I2C_FLAG_ADD10SEND BIT(3) /*!< header of 10-bit address is sent in master mode */ +#define I2C_FLAG_STPDET BIT(4) /*!< etop condition detected in slave mode */ +#define I2C_FLAG_RBNE BIT(6) /*!< I2C_DATA is not Empty during receiving */ +#define I2C_FLAG_TBE BIT(7) /*!< I2C_DATA is empty during transmitting */ +#define I2C_FLAG_BERR BIT(8) /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ +#define I2C_FLAG_LOSTARB BIT(9) /*!< arbitration lost in master mode */ +#define I2C_FLAG_AERR BIT(10) /*!< acknowledge error */ +#define I2C_FLAG_OUERR BIT(11) /*!< over-run or under-run situation occurs in slave mode */ +#define I2C_FLAG_PECERR BIT(12) /*!< PEC error when receiving data */ +#define I2C_FLAG_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_FLAG_SMBALT BIT(15) /*!< SMBus alert status */ +#define I2C_FLAG_MASTER (BIT(0)|BIT(31)) /*!< a flag indicating whether I2C block is in master or slave mode */ +#define I2C_FLAG_I2CBSY (BIT(1)|BIT(31)) /*!< busy flag */ +#define I2C_FLAG_TRS (BIT(2)|BIT(31)) /*!< whether the I2C is a transmitter or a receiver */ +#define I2C_FLAG_RXGC (BIT(4)|BIT(31)) /*!< general call address (00h) received */ +#define I2C_FLAG_DEFSMB (BIT(5)|BIT(31)) /*!< default address of SMBus device */ +#define I2C_FLAG_HSTSMB (BIT(6)|BIT(31)) /*!< SMBus host header detected in slave mode */ +#define I2C_FLAG_DUMOD (BIT(7)|BIT(31)) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + +/* I2C interrupt flags */ +#define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND /*!< start condition sent out in master mode interrupt flag */ +#define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ +#define I2C_INT_FLAG_BTC I2C_FLAG_BTC /*!< byte transmission finishes */ +#define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND /*!< header of 10-bit address is sent in master mode interrupt flag */ +#define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET /*!< stop condition detected in slave mode interrupt flag */ +#define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE /*!< I2C_DATA is not Empty during receiving interrupt flag */ +#define I2C_INT_FLAG_TBE I2C_FLAG_TBE /*!< I2C_DATA is empty during transmitting interrupt flag */ +#define I2C_INT_FLAG_BERR I2C_FLAG_BERR /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ +#define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB /*!< arbitration lost in master mode interrupt flag */ +#define I2C_INT_FLAG_AERR I2C_FLAG_AERR /*!< acknowledge error interrupt flag */ +#define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR /*!< over-run or under-run situation occurs in slave mode interrupt flag */ +#define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR /*!< PEC error when receiving data interrupt flag */ +#define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO /*!< timeout signal in SMBus mode interrupt flag */ +#define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT /*!< SMBus Alert status interrupt flag */ + +/* I2C interrupt enable bit */ +#define I2C_INT_ERR I2C_CTL1_ERRIE /*!< error interrupt enable */ +#define I2C_INT_EV I2C_CTL1_EVIE /*!< event interrupt enable */ +#define I2C_INT_BUF I2C_CTL1_BUFIE /*!< buffer interrupt enable */ + +/* I2C duty cycle in fast mode or fast mode plus */ +#define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14)) +#define I2C_DTCY_2 CKCFG_DTCY(0) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 CKCFG_DTCY(1) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1) /*!< address:10 bits */ + +#ifdef GD_MBED_USED +#define SLAVE10_FIRST_BYTE(addr10) ((0xF0) | (uint8_t)((addr10 & 0x0300)>>7)) +#define SLAVE10_SECOND_BYTE(addr10) ((uint8_t)(addr10 & 0x00FF)) + +typedef enum +{ + I2C_MODE_NONE = 0x00U, /*!< I2C device is idle */ + I2C_MODE_MASTER = 0x10U, /*!< I2C device is in Master Mode */ + I2C_MODE_SLAVE = 0x20U /*!< I2C device is in Slave Mode */ +}i2c_mode_enum; + +/* I2C state definitions */ +#define I2C_STATE_MSK ((uint32_t)((OP_STATE_BUSY_TX | OP_STATE_BUSY_RX) & (~(uint32_t)OP_STATE_BUSY))) +#define I2C_STATE_NONE ((uint32_t)(I2C_MODE_NONE)) +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((OP_STATE_BUSY_TX & I2C_STATE_MSK) | I2C_MODE_MASTER)) +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((OP_STATE_BUSY_RX & I2C_STATE_MSK) | I2C_MODE_MASTER)) +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((OP_STATE_BUSY_TX & I2C_STATE_MSK) | I2C_MODE_SLAVE)) +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((OP_STATE_BUSY_RX & I2C_STATE_MSK) | I2C_MODE_SLAVE)) + +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_NEXT_FRAME 0x00000002U +#define I2C_FIRST_AND_LAST_FRAME 0x00000004U +#define I2C_LAST_FRAME 0x00000008U +#define I2C_NO_OPTION_FRAME 0xFFFF0000U + +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U + +#define I2C_ERROR_NONE 0x00000000U /*!< no error */ +#define I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define I2C_ERROR_LOSTARB 0x00000002U /*!< LOSTARB error */ +#define I2C_ERROR_AERR 0x00000004U /*!< AERR error */ +#define I2C_ERROR_OUERR 0x00000008U /*!< OUERR error */ +#define I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define I2C_ERROR_TIMEOUT 0x00000020U /*!< timeout Error */ + +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< timeout 25 ms */ +#endif + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master send slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* dual-address mode switch */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); + +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* I2C DMA mode enable */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* flag indicating DMA last transfer */ +void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara ); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,uint32_t intflag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph,uint32_t intflag); + +/* I2C PEC calculation on or off */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +#endif /* GD32F30X_I2C_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h new file mode 100644 index 00000000000..63bb8ff790b --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h @@ -0,0 +1,68 @@ +/*! + \file gd32f30x_misc.h + \brief definitions for the MISC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_MISC_H +#define GD32F30X_MISC_H + +#include "gd32f30x.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F30X_MISC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h new file mode 100644 index 00000000000..3621e7db41d --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h @@ -0,0 +1,160 @@ +/*! + \file gd32f30x_pmu.h + \brief definitions for the PMU +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_PMU_H +#define GD32F30X_PMU_H + +#include "gd32f30x.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + +/* PMU high-driver mode switch */ +#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) +#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ + +/* PMU low-driver mode when use low power LDO */ +#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) +#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU low-driver mode when use normal power LDO */ +#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) +#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* functions of low-driver mode and high-driver mode in deep-sleep mode */ +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* enable high-driver mode */ +void pmu_highdriver_mode_enable(void); +/* disable high-driver mode */ +void pmu_highdriver_mode_disable(void); +/* enable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_disable(void); +/* in deep-sleep mode, driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); + +/* set PMU mode */ +/* PMU work at sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work at deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work at standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* enable backup domain write */ +void pmu_backup_write_enable(void); +/* disable backup domain write */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_reset); +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); + +#endif /* GD32F30X_PMU_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h new file mode 100644 index 00000000000..b5baa88892e --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h @@ -0,0 +1,1027 @@ +/*! + \file gd32f30x_rcu.h + \brief definitions for the RCU +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_RCU_H +#define GD32F30X_RCU_H + +#include "gd32f30x.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ +#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ +#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ +#elif defined(GD32F30X_CL) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ +#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ +#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* bits definitions */ +/* RCU_CTL */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#elif defined(GD32F30X_CL) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ +#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ +#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ +#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_CFG0 */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ +#define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ +#elif defined(GD32F30X_CL) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ +#define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_INT */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#elif defined(GD32F30X_CL) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ +#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ +#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ +#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ +#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ +#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ +#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ +#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ +#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ +#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ +#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#ifndef GD32F30X_CL +#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD +#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ +#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ +#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ +#endif /* GD32F30X_HD */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#ifndef GD32F30X_HD +#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ +#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ +#endif /* GD32F30X_HD */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#ifdef GD32F30X_CL +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#endif /* GD32F30X_CL */ +#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ +#elif defined(GD32F30X_CL) +#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ +#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ +#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ +#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ +#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ +#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ +#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ +#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ +#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ +#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ +#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#ifndef GD32F30X_CL +#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD +#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ +#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ +#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ +#endif /* GD32F30X_HD */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#ifndef GD32F30X_HD +#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ +#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ +#endif /* GD32F30X_HD */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#ifdef GD32F30X_CL +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#endif /* GD32F30X_CL */ +#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +#ifdef GD32F30X_CL +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ +#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ +#endif /* GD32F30X_CL */ + +/* RCU_CFG1 */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ +#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ +#elif defined(GD32F30X_CL) +#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ +#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ +#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ +#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ +#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ +#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ +#define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ + +/* RCU_ADDCTL */ +#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ +#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ +#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ +#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ + +/* RCU_ADDINT */ +#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ +#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ +#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ + +/* RCU_ADDAPB1RST */ +#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ + +/* RCU_ADDAPB1EN */ +#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ + + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ +#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ +#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ +#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ +#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ +#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum +{ + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ +#elif defined(GD32F30X_CL) + RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ + RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ + RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ + RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ +#ifndef GD32F30X_HD + RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ +#endif /* GD32F30X_HD */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ +#ifdef GD32F30X_CL + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ +#endif /* GD32F30X_CL */ + RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ + + /* APB2 peripherals */ + RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ + RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ + RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ +#ifndef GD32F30X_CL + RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD + RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ + RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ + RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ +#endif /* GD32F30X_HD */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB peripherals */ +#ifdef GD32F30X_CL + RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ +#endif /* GD32F30X_CL */ + + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ +#ifndef GD32F30X_HD + RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ + RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ +#endif /* GD32F30X_HD */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ +#ifdef GD32F30X_CL + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ +#endif /* GD32F30X_CL */ + RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */ + + /* APB2 peripherals */ + RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ + RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ +#ifndef GD32F30X_CL + RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD + RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ + RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ + RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ +#endif /* GD32F30X_HD */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ +#ifdef GD32F30X_CL + RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ + RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ +#endif /* GD32F30X_CL */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ + RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ + /* reset source flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ +#ifdef GD32F30X_CL + RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ + RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ +#endif /* GD32F30X_CL */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ + RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ +#ifdef GD32F30X_CL + RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ +#endif /* GD32F30X_CL */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ + RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ +#ifdef GD32F30X_CL + RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ + RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ +#endif /* GD32F30X_CL */ + RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ +}rcu_int_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ +#ifdef GD32F30X_CL + RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ + RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ +#endif /* GD32F30X_CL */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +}rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC prescaler select */ +#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ +#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ +#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ +#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ +#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ +#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ +#define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */ +#define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */ +#define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */ +#define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ +#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ +#define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ +#define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ + +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#elif defined(GD32F30X_CL) +#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ +#define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */ +#define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */ +#define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */ +#define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */ +#define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */ +#define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */ +#define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */ +#define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */ +#define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */ +#define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */ +#define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */ +#define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */ +#define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */ +#define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */ +#define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */ +#define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */ +#define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */ +#define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */ +#define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */ +#define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */ +#define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */ +#define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */ +#define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */ +#define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */ +#define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */ +#define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */ +#define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */ +#define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */ +#define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */ +#define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */ +#define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */ + +#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define USBPSC_2 RCU_CFG0_USBDPSC_2 +#elif defined(GD32F30X_CL) +#define USBPSC_2 RCU_CFG0_USBFSPSC_2 +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* USBD/USBFS prescaler select */ +#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ +#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ +#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ +#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ +#define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBD/USBFS prescaler select CK_PLL/3.5 */ +#define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBD/USBFS prescaler select CK_PLL/3 */ +#define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */ + +/* CKOUT0 Clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ +#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ +#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ +#ifdef GD32F30X_CL +#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ +#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ +#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ +#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ +#endif /* GD32F30X_CL */ + +/* LXTAL drive capability */ +#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ +#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ +#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ +#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + +/* PREDV0 division factor */ +#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ +#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ +#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ +#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ +#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ +#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ +#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ +#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ +#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ +#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ +#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ +#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ +#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ +#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ +#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ +#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + +/* PREDV1 division factor */ +#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ +#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ +#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ +#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ +#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ +#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ +#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ +#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ +#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ +#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ +#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ +#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ +#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ +#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ +#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ +#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + +/* PLL1 clock multiplication factor */ +#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ +#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ +#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ +#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ +#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ +#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ +#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ +#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ +#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ +#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + +/* PLL2 clock multiplication factor */ +#define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ + +#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) +#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ +#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ +#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ +#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ +#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ +#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ +#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ +#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ +#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ +#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ +#define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */ +#define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */ +#define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */ +#define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */ +#define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */ +#define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */ +#define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */ +#define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */ +#define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */ +#define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */ +#define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */ +#define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */ +#define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */ +#define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */ +#define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */ + +#ifdef GD32F30X_CL +/* PREDV0 input clock source selection */ +#define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ +#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ + +/* I2S1 clock source selection */ +#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ +#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ + +/* I2S2 clock source selection */ +#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ +#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ +#endif /* GD32F30X_CL */ + +/* PLL input clock source selection */ +#define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ +#define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ + +/* 48MHz clock selection */ +#define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */ +#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */ + +/* function declarations */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP domain */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain reset */ +void rcu_bkp_reset_disable(void); + +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +/* configure the PLL clock source preselection */ +void rcu_pllpresel_config(uint32_t pll_presel); +#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_div); +#elif defined(GD32F30X_CL) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); +/* configure the PREDV1 division factor */ +void rcu_predv1_config(uint32_t predv1_div); +/* configure the PLL1 clock */ +void rcu_pll1_config(uint32_t pll_mul); +/* configure the PLL2 clock */ +void rcu_pll2_config(uint32_t pll_mul); +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the USBD/USBFS prescaler factor */ +void rcu_usb_clock_config(uint32_t usb_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +#ifdef GD32F30X_CL +/* configure the I2S1 clock source selection */ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source); +/* configure the I2S2 clock source selection */ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source); +#endif /* GD32F30X_CL */ +/* configure the CK48M clock selection */ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); + + +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); + +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32F30X_RCU_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h new file mode 100644 index 00000000000..5292df31596 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h @@ -0,0 +1,111 @@ +/*! + \file gd32f30x_rtc.h + \brief definitions for the RTC +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_RTC_H +#define GD32F30X_RTC_H + +#include "gd32f30x.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSC */ +#define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ +#define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ + +/* RTC_DIV */ +#define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ +#define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ + +/* RTC_CNT */ +#define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ +#define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ + +/* RTC_ALRM */ +#define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ +#define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ + +/* constants definitions */ +#define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ +#define RTC_LOW_VALUE 0x0000FFFFU /*!< RTC low value */ + +/* RTC interrupt enable or disable definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); + +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); + +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); + +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); + +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); + +#endif /* GD32F30X_RTC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h new file mode 100644 index 00000000000..78150eb742a --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h @@ -0,0 +1,404 @@ +/*! + \file gd32f30x_sdio.h + \brief definitions for the SDIO +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_SDIO_H +#define GD32F30X_SDIO_H + +#include "gd32f30x.h" + +/* SDIO definitions */ +#define SDIO SDIO_BASE + +/* registers definitions */ +#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ + +/* bits definitions */ +/* SDIO_PWRCTL */ +#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ + +/* SDIO_CLKCTL */ +#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ +#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ +#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ +#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ +#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ +#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ + +/* SDIO_CMDAGMT */ +#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ + +/* SDIO_CMDCTL */ +#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ +#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ +#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ +#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ +#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ +#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ +#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ +#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + +/* SDIO_DATATO */ +#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ + +/* SDIO_DATALEN */ +#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ + +/* SDIO_DATACTL */ +#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ +#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ +#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ +#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ +#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ +#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ +#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ +#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ + +/* SDIO_STAT */ +#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ +#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ +#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ +#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ +#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ +#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ +#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ +#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ +#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ +#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ +#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ +#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ +#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ +#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ +#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ +#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ +#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ +#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ +#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ +#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ +#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ +#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ +#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ +#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ + +/* SDIO_INTC */ +#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ +#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ +#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ +#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ +#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ +#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ +#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ +#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ +#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ +#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ +#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ +#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ +#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ + +/* SDIO_INTEN */ +#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ +#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ +#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ +#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ +#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ +#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ +#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ +#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ +#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ +#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ +#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ +#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ +#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ +#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ +#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ +#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ +#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ +#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ +#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ +#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ +#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ +#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + +/* SDIO_FIFO */ +#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + +/* constants definitions */ +/* SDIO flags */ +#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ +#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ +#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ +#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ +#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ +#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ +#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ +#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ +#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ +#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ +#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ +#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ +#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ +#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ +#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ +#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ +#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ +#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ +#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ +#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ +#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ +#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ +#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ +#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ + +/* SDIO interrupt enable or disable */ +#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO power control */ +#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ +#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + +/* SDIO card bus mode control */ +#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ +#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ +#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + +/* SDIO_CLK clock edge selection */ +#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ +#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ + +/* clock bypass enable or disable */ +#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */ +#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ + +/* SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */ +#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + +/* SDIO command response type */ +#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ +#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ +#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + +/* command state machine wait type */ +#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */ +#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ +#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ + +#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */ +#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */ +#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */ +#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ + +/* SDIO data block size */ +#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ +#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ +#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ +#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ +#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ +#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ +#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ +#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ +#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ +#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ +#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ +#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ +#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ +#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ +#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ + +/* SDIO data transfer mode */ +#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */ +#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ + +/* SDIO data transfer direction */ +#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */ +#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ + +/* SDIO read wait type */ +#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */ +#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ + +/* function declarations */ +/* deinitialize the SDIO */ +void sdio_deinit(void); +/* configure the SDIO clock */ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); +/* enable hardware clock control */ +void sdio_hardware_clock_enable(void); +/* disable hardware clock control */ +void sdio_hardware_clock_disable(void); +/* set different SDIO card bus mode */ +void sdio_bus_mode_set(uint32_t bus_mode); +/* set the SDIO power state */ +void sdio_power_state_set(uint32_t power_state); +/* get the SDIO power state */ +uint32_t sdio_power_state_get(void); +/* enable SDIO_CLK clock output */ +void sdio_clock_enable(void); +/* disable SDIO_CLK clock output */ +void sdio_clock_disable(void); + +/* configure the command index, argument, response type, wait type and CSM to send command */ +/* configure the command and response */ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); +/* set the command state machine wait type */ +void sdio_wait_type_set(uint32_t wait_type); +/* enable the CSM(command state machine) */ +void sdio_csm_enable(void); +/* disable the CSM(command state machine) */ +void sdio_csm_disable(void); +/* get the last response command index */ +uint8_t sdio_command_index_get(void); +/* get the response for the last received command */ +uint32_t sdio_response_get(uint32_t responsex); + +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ +/* configure the data timeout, data length and data block size */ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); +/* configure the data transfer mode and direction */ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); +/* enable the DSM(data state machine) for data transfer */ +void sdio_dsm_enable(void); +/* disable the DSM(data state machine) */ +void sdio_dsm_disable(void); +/* write data(one word) to the transmit FIFO */ +void sdio_data_write(uint32_t data); +/* read data(one word) from the receive FIFO */ +uint32_t sdio_data_read(void); +/* get the number of remaining data bytes to be transferred to card */ +uint32_t sdio_data_counter_get(void); +/* get the number of words remaining to be written or read from FIFO */ +uint32_t sdio_fifo_counter_get(void); +/* enable the DMA request for SDIO */ +void sdio_dma_enable(void); +/* disable the DMA request for SDIO */ +void sdio_dma_disable(void); + +/* get the flags state of SDIO */ +FlagStatus sdio_flag_get(uint32_t flag); +/* clear the pending flags of SDIO */ +void sdio_flag_clear(uint32_t flag); +/* enable the SDIO interrupt */ +void sdio_interrupt_enable(uint32_t int_flag); +/* disable the SDIO interrupt */ +void sdio_interrupt_disable(uint32_t int_flag); +/* get the interrupt flags state of SDIO */ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); +/* clear the interrupt pending flags of SDIO */ +void sdio_interrupt_flag_clear(uint32_t int_flag); + +/* enable the read wait mode(SD I/O only) */ +void sdio_readwait_enable(void); +/* disable the read wait mode(SD I/O only) */ +void sdio_readwait_disable(void); +/* enable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_enable(void); +/* disable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_disable(void); +/* set the read wait type(SD I/O only) */ +void sdio_readwait_type_set(uint32_t readwait_type); +/* enable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_enable(void); +/* disable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_disable(void); +/* enable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_enable(void); +/* disable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_disable(void); + +/* enable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_enable(void); +/* disable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_disable(void); +/* enable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_enable(void); +/* disable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_disable(void); +/* enable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_enable(void); +/* disable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_disable(void); + +#endif /* GD32F30X_SDIO_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h new file mode 100644 index 00000000000..08b8954d45b --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h @@ -0,0 +1,332 @@ +/*! + \file gd32f30x_spi.h + \brief definitions for the SPI +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_SPI_H +#define GD32F30X_SPI_H + +#include "gd32f30x.h" + +/* SPIx(x=0,1,2) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI0) */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_QCTL(only for SPI0) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ + +/* function declarations */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); + #ifdef GD_MBED_USED +/* initialize SPI parameter */ +void spi_para_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +#else +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +#endif +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); + +/* enable quad wire SPI */ +void qspi_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void qspi_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void qspi_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void qspi_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_disable(uint32_t spi_periph); + +#endif /* GD32F30X_SPI_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h new file mode 100644 index 00000000000..a0845fa5591 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h @@ -0,0 +1,716 @@ +/*! + \file gd32f30x_timer.h + \brief definitions for the TIMER +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#ifndef GD32F30X_TIMER_H +#define GD32F30X_TIMER_H + +#include "gd32f30x.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) +#define TIMER7 (TIMER_BASE + 0x00013400U) +#define TIMER8 (TIMER_BASE + 0x00014C00U) +#define TIMER9 (TIMER_BASE + 0x00015000U) +#define TIMER10 (TIMER_BASE + 0x00015400U) +#define TIMER11 (TIMER_BASE + 0x00001800U) +#define TIMER12 (TIMER_BASE + 0x00001C00U) +#define TIMER13 (TIMER_BASE + 0x00002000U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< channel control update DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint32_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint32_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */ +#define TIMER_INT_CH0 ((uint32_t)0x00000002U) /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 ((uint32_t)0x00000004U) /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 ((uint32_t)0x00000008U) /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 ((uint32_t)0x00000010U) /*!< channel 3 interrupt */ +#define TIMER_INT_CMT ((uint32_t)0x00000020U) /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG ((uint32_t)0x00000040U) /*!< trigger interrupt */ +#define TIMER_INT_BRK ((uint32_t)0x00000080U) /*!< break interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK + +/* TIMER flag */ +#define TIMER_FLAG_UP ((uint32_t)0x00000001U) /*!< update flag */ +#define TIMER_FLAG_CH0 ((uint32_t)0x00000002U) /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 ((uint32_t)0x00000004U) /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 ((uint32_t)0x00000008U) /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 ((uint32_t)0x00000010U) /*!< channel 3 flag */ +#define TIMER_FLAG_CMT ((uint32_t)0x00000020U) /*!< channel control update flag */ +#define TIMER_FLAG_TRG ((uint32_t)0x00000040U) /*!< trigger flag */ +#define TIMER_FLAG_BRK ((uint32_t)0x00000080U) /*!< break flag */ +#define TIMER_FLAG_CH0O ((uint32_t)0x00000200U) /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O ((uint32_t)0x00000400U) /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O ((uint32_t)0x00000800U) /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O ((uint32_t)0x00001000U) /*!< channel 3 overcapture flag */ + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)0x0100U) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)0x0200U) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)0x0400U) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)0x0800U) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)0x1000U) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)0x2000U) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)0x4000U) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel y(y=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable. */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge(not for timer1..6) */ + +/* timer input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ + +/* timerx(x=0,1,2,13,14,15,16) write cc register selection */ +#define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U) /*!< write CC register selection disable */ +#define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U) /*!< write CC register selection enable */ + +/* the output value selection */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint8_t update); + +/* TIMER interrupt and flag */ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +/* timer DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* timer channel complementary protection */ +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* configure TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* channel capture/compare control shadow register enable */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +#endif /* GD32F30X_TIMER_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h new file mode 100644 index 00000000000..267dfbb8ed0 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h @@ -0,0 +1,433 @@ +/*! + \file gd32f30x_usart.h + \brief definitions for GD32F30x +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_USART_H +#define GD32F30X_USART_H + +#include "gd32f30x.h" + +/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ +#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ +#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ +#define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ + +/* registers definitions */ +#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ +#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ +#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ +#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ +#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ + +/* bits definitions */ +/* USARTx_STAT0 */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_CTL3 */ +#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_STAT1 */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ + +/* USART flags */ +typedef enum +{ + /* flags in STAT0 register */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in STAT1 register */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ + /* interrupt flags in CTL3 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in CTL3 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ +}usart_interrupt_enum; + +/* USART invert configure */ +typedef enum +{ + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ +}usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ + +#ifdef GD_MBED_USED +/* USART error code */ +#define USART_ERROR_CODE_NONE 0U /*!< no error */ +#define USART_ERROR_CODE_PERR BIT(0) /*!< parity error */ +#define USART_ERROR_CODE_NERR BIT(1) /*!< noise error */ +#define USART_ERROR_CODE_FERR BIT(2) /*!< frame error */ +#define USART_ERROR_CODE_ORERR BIT(3) /*!< overrun error */ + +/* USART hardware control configuration */ +#define USART_HWCONTROL_NONE 0U +#define USART_HWCONTROL_RTS USART_RTS_ENABLE +#define USART_HWCONTROL_CTS USART_CTS_ENABLE +#define USART_HWCONTROL_RTS_CTS (USART_RTS_ENABLE | USART_CTS_ENABLE) +#endif + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); + +/* USART normal mode communication */ +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* LIN mode enable */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* LIN mode disable */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* half-duplex enable */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* half-duplex disable */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* clock enable */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* clock disable */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* guard time value configure in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph,uint32_t guat); +/* smartcard mode enable */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* smartcard mode disable */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* NACK enable in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* NACK disable in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* smartcard auto-retry number configure */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* block length configure */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag functions */ +/* get flag in STAT0/STAT1 register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT0/STAT1 register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); + +/* interrupt functions */ +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +/* clear interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); +#endif /* GD32F30x_USART_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h new file mode 100644 index 00000000000..7e6437674ee --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h @@ -0,0 +1,63 @@ +/*! + \file gd32f30x_wwdgt.h + \brief definitions for the WWDGT +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_WWDGT_H +#define GD32F30X_WWDGT_H + +#include "gd32f30x.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32F30X_WWDGT_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c new file mode 100644 index 00000000000..0b7a8564772 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c @@ -0,0 +1,915 @@ +/*! + \file gd32f30x_adc.c + \brief ADC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#include "gd32f30x_adc.h" + +/*! + \brief reset ADC + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_deinit(uint32_t adc_periph) +{ + switch(adc_periph){ + case ADC0: + rcu_periph_reset_enable(RCU_ADC0RST); + rcu_periph_reset_disable(RCU_ADC0RST); + break; + case ADC1: + rcu_periph_reset_enable(RCU_ADC1RST); + rcu_periph_reset_disable(RCU_ADC1RST); + break; +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + case ADC2: + rcu_periph_reset_enable(RCU_ADC2RST); + rcu_periph_reset_disable(RCU_ADC2RST); + break; +#endif + default: + break; + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC1 calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] resolution: ADC resolution + only one among these parameters can be selected + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + only one among these parameters can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel ,the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U)); + + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] mode: ADC mode + only one among these parameters can be selected + \arg ADC_MODE_FREE: all the ADCs work independently + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only + \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \param[out] none + \retval none +*/ +void adc_mode_config(uint32_t mode) +{ + ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); + ADC_CTL0(ADC0) |= mode; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] function: the function to config + one or more parameters can be selected below + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (function & ADC_SCAN_MODE)){ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + }else{ + if(0U != (function & ADC_SCAN_MODE)){ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] data_alignment: data alignment select + only one parameter can be selected + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + }else{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + only one parameter can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); + + break; + case ADC_INSERTED_CHANNEL: + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U)); + + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one among these parameters can be selected + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +{ + uint32_t rsq,sampt; + + /* ADC regular sequence config */ + if(rank < 6U){ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); + rsq |= ((uint32_t)adc_channel << (5U*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < 12U){ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); + rsq |= ((uint32_t)adc_channel << (5U*(rank-6U))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < 16U){ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); + rsq |= ((uint32_t)adc_channel << (5U*(rank-12U))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* ADC sampling time config */ + if(adc_channel < 10U){ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); + sampt |= (uint32_t)(sample_time << (3U*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < 18U){ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); + sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one among these parameters can be selected + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq,sampt; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U))); + isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U)); + ADC_ISQ(adc_periph) = isq; + + /* ADC sampling time config */ + if(adc_channel < 10U){ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); + sampt |= (uint32_t) sample_time << (3U*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel < 18U){ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); + sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] inserted_channel : insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset : the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + num = 3U - (inserted_length - inserted_channel); + + if(num <= 3U){ + /* calculate the offset of the register */ + num = num * 4U; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief enable ADC external trigger + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; + } + }else{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + only one parameter can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected + for regular channel: + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select + \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select + \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11 + \arg ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select + \arg ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select + \arg ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select + \arg ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select + \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select + \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select + \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select + \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select + \arg ADC2_EXTTRIG_INSERTED_T3_CH2: timer 3 CC2 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH1: timer 7 CC1 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select + \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: timer 4 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T4_CH3: timer 4 CC3 event select + \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +{ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) +{ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; + } + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] inserted_channel : insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief read the last ADC0 and ADC1 conversion result data in sync mode + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint32_t adc_sync_mode_convert_value_read(void) +{ + /* return conversion value */ + return ADC_RDATA(ADC0); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_flag: the adc flag bits + only one parameter can be selected + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag){ + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_flag: the adc flag bits + one or more parameters can be selected + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc interrupt bits + only oneparameter can be selected + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt){ + case ADC_INT_FLAG_WDE: + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc status flag + one or more parameters can be selected + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc interrupt + one or more parameters can be selected + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) +{ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + } + + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + } + + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc interrupt flag + one or more parameters can be selected + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + if(0U != (adc_interrupt & ADC_INT_WDE)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; + } + + if(0U != (adc_interrupt & ADC_INT_EOC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; + } + + if(0U != (adc_interrupt & ADC_INT_EOIC)){ + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief configure ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel: the selected ADC channel + only one among these parameters can be selected + \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + /* select the group */ + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) +{ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] mode: ADC oversampling mode + only oneparameter can be selected + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only oneparameter can be selected + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only oneparameter can be selected + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) +{ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + }else{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + /* config the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c new file mode 100644 index 00000000000..187916c9123 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c @@ -0,0 +1,302 @@ +/*! + \file gd32f30x_bkp.c + \brief BKP driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#include "gd32f30x_bkp.h" + +#define TAMPER_FLAG_SHIFT ((uint8_t)8U) + +/*! + \brief reset BKP registers + \param[in] none + \param[out] none + \retval none +*/ +void bkp_deinit(void) +{ + /* reset BKP domain register*/ + rcu_bkp_reset_enable(); + rcu_bkp_reset_disable(); +} + +/*! + \brief write BKP data register + \param[in] register_number: refer to bkp_data_register_enum, only one parameter can be selected + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[in] data: the data to be write in BKP data register + \param[out] none + \retval none +*/ +void bkp_write_data(bkp_data_register_enum register_number, uint16_t data) +{ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + BKP_DATA10_41(register_number-1U) = data; + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + BKP_DATA0_9(register_number-1U) = data; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief read BKP data register + \param[in] register_number: refer to bkp_data_register_enum, only one parameter can be selected + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[out] none + \retval data of BKP data register +*/ +uint16_t bkp_read_data(bkp_data_register_enum register_number) +{ + uint16_t data = 0U; + + /* get the data from the BKP data register */ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + data = BKP_DATA10_41(register_number-1U); + }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + data = BKP_DATA0_9(register_number-1U); + }else{ + /* illegal parameters */ + } + return data; +} + +/*! + \brief enable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; +} + +/*! + \brief disable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; +} + +/*! + \brief enable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; +} + +/*! + \brief disable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; +} + +/*! + \brief select RTC output + \param[in] outputsel: RTC output selection + \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output + \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output + \param[out] none + \retval none +*/ +void bkp_rtc_output_select(uint16_t outputsel) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_ROSEL; + ctl |= outputsel; + BKP_OCTL = ctl; +} + +/*! + \brief select RTC clock output + \param[in] clocksel: RTC clock output selection + \arg RTC_CLOCK_DIV_64: RTC clock div 64 + \arg RTC_CLOCK_DIV_1: RTC clock + \param[out] none + \retval none +*/ +void bkp_rtc_clock_output_select(uint16_t clocksel) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_CCOSEL; + ctl |= clocksel; + BKP_OCTL = ctl; +} + +/*! + \brief RTC clock calibration direction + \param[in] direction: RTC clock calibration direction + \arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down + \arg RTC_CLOCK_SPEED_UP: RTC clock speed up + \param[out] none + \retval none +*/ +void bkp_rtc_clock_calibration_direction(uint16_t direction) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_CALDIR; + ctl |= direction; + BKP_OCTL = ctl; +} + +/*! + \brief set RTC clock calibration value + \param[in] value: RTC clock calibration value + \arg 0x00 - 0x7F + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_value_set(uint8_t value) +{ + uint16_t ctl; + + ctl = BKP_OCTL; + ctl &= (uint16_t)OCTL_RCCV(0); + ctl |= (uint16_t)OCTL_RCCV(value); + BKP_OCTL = ctl; +} + +/*! + \brief enable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_enable(void) +{ + BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; +} + +/*! + \brief disable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_disable(void) +{ + BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; +} + +/*! + \brief set tamper pin active level + \param[in] level: tamper active level + \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high + \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low + \param[out] none + \retval none +*/ +void bkp_tamper_active_level_set(uint16_t level) +{ + uint16_t ctl = 0U; + + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_TPAL; + ctl |= level; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_enable(void) +{ + BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; +} + +/*! + \brief disable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_disable(void) +{ + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; +} + +/*! + \brief get bkp flag state + \param[in] flag + \arg BKP_FLAG_TAMPER: tamper event flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_flag_get(uint16_t flag) +{ + if(RESET != (BKP_TPCS & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear bkp flag state + \param[in] flag + \arg BKP_FLAG_TAMPER: tamper event flag + \param[out] none + \retval none +*/ +void bkp_flag_clear(uint16_t flag) +{ + BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); +} + +/*! + \brief get bkp interrupt flag state + \param[in] flag + \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_interrupt_flag_get(uint16_t flag) +{ + if(RESET != (BKP_TPCS & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear bkp interrupt flag state + \param[in] flag + \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag + \param[out] none + \retval none +*/ +void bkp_interrupt_flag_clear(uint16_t flag) +{ + BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); +} + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c new file mode 100644 index 00000000000..d373f9d2aef --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c @@ -0,0 +1,850 @@ +/*! + \file gd32f30x_can.c + \brief CAN driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_can.h" + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ +#ifdef GD32F30X_CL + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + }else{ + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +#else + if(CAN0 == can_periph){ + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } +#endif +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0001 - 0x03FF + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +#ifdef GD_MBED_USED +ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +#else +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +#endif +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ + timeout--; + } + /* check initialize working success */ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + /* time trigger communication mode */ + if(ENABLE == can_parameter_init->time_triggered){ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off managment */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if(ENABLE == can_parameter_init->auto_wake_up){ + CAN_CTL(can_periph) |= CAN_CTL_AWU; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode */ + if(ENABLE == can_parameter_init->auto_retrans){ + CAN_CTL(can_periph) |= CAN_CTL_ARD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } + /* receive fifo overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite){ + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } + /* transmit fifo order */ + if(ENABLE == can_parameter_init->trans_fifo_order){ + CAN_CTL(can_periph) |= CAN_CTL_TFO; + }else{ + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ + timeout--; + } + /* check exit initialize mode */ + if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = SUCCESS; + } + } + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + }else{ + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + }else{ + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if(ENABLE == can_filter_parameter_init->filter_enable){ + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 fliter start bank number + \param[in] start_bank: CAN1 start bank number + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enaable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; +#ifdef GD32F30X_CL + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + }else{ + dbg_periph_enable(DBG_CAN1_HOLD); + } +#else + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; +#ifdef GD32F30X_CL + if(CAN0 == can_periph){ + dbg_periph_disable(DBG_CAN0_HOLD); + }else{ + dbg_periph_disable(DBG_CAN1_HOLD); + } +#else + if(CAN0 == can_periph){ + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the tcc mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TCC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlenc: 1 - 7 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + mailbox_number = CAN_MAILBOX0; + }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + mailbox_number = CAN_MAILBOX1; + }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + mailbox_number = CAN_MAILBOX2; + }else{ + mailbox_number = CAN_NOMAILBOX; + } + if(CAN_NOMAILBOX == mailbox_number){ + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff){ + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + }else{ + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] mailbox_number + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + switch(mailbox_number){ + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + switch(val){ + /* transmit pending */ + case (CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* transmit succeeded */ + case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if(CAN_MAILBOX0 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + }else if(CAN_MAILBOX1 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + }else if(CAN_MAILBOX2 == mailbox_number){ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlenc: 1 - 7 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if(CAN_FF_STANDARD == receive_message->rx_ff){ + /* get standard identifier */ + receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + }else{ + /* get extended identifier */ + receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* get recevie data length */ + receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + /* filtering index */ + receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else{ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO0 + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if(CAN_FIFO0 == fifo_number){ + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + }else if(CAN_FIFO1 == fifo_number){ + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + }else{ + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if(CAN_FIFO0 == fifo_number){ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + }else if(CAN_FIFO1 == fifo_number){ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + }else{ + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] can_working_mode + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode){ + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_NORMAL == working_mode){ + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + timeout--; + } + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else if(CAN_MODE_SLEEP == working_mode){ + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + timeout--; + } + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + }else{ + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + timeout--; + } + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + flag = ERROR; + }else{ + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval can_error_enum +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U); + return val; +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] interrupt + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] interrupt + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c new file mode 100644 index 00000000000..ccd520fe2c9 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c @@ -0,0 +1,101 @@ +/*! + \file gd32f30x_crc.c + \brief CRC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_crc.h" + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = (uint32_t)0xFFFFFFFFU; + CRC_FDATA = (uint32_t)0x00000000U; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief CRC calculate a 32-bit data + \param[in] sdata: specify 32-bit data + \param[out] none + \retval 32-bit CRC calculate value +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief CRC calculate a 32-bit data array + \param[in] array: pointer to an array of 32 bit data words + \param[in] size: size of the array + \param[out] none + \retval 32-bit CRC calculate value +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for(index = 0U; index < size; index++){ + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c new file mode 100644 index 00000000000..82f80eda406 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c @@ -0,0 +1,344 @@ +/*! + \file gd32f30x_ctc.c + \brief CTC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_ctc.h" + +#define CTC_FLAG_MASK ((uint32_t)0x00000700U) + +/*! + \brief reset CTC clock trim controller + \param[in] none + \param[out] none + \retval none +*/ +void ctc_deinit(void) +{ + /* reset CTC */ + rcu_periph_reset_enable(RCU_CTCRST); + rcu_periph_reset_disable(RCU_CTCRST); +} + +/*! + \brief configure the IRC48M trim value + \param[in] ctc_trim_value: 8-bit IRC48M trim value + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value) +{ + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= ((uint32_t)ctc_trim_value << 8); +} + +/*! + \brief generate software reference source sync pulse + \param[in] none + \param[out] none + \retval none +*/ +void ctc_software_refsource_pulse_generate(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; +} + +/*! + \brief configure hardware automatically trim mode + \param[in] ctc_hardmode: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \param[out] none + \retval none +*/ +void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)ctc_hardmode; +} + +/*! + \brief enable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure reference signal source polarity + \param[in] ctc_polarity: + \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge + \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge + \param[out] none + \retval none +*/ +void ctc_refsource_polarity_config(uint32_t ctc_polarity) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); + CTC_CTL1 |= (uint32_t)ctc_polarity; +} + +/*! + \brief select reference signal source + \param[in] ctc_refs: + \arg CTC_REFSOURCE_GPIO: GPIO is selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected + \arg CTC_REFSOURCE_USBSOF: USBSOF is selected + \param[out] none + \retval none +*/ +void ctc_refsource_signal_select(uint32_t ctc_refs) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); + CTC_CTL1 |= (uint32_t)ctc_refs; +} + +/*! + \brief configure reference signal source prescaler + \param[in] ctc_prescaler: + \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided + \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 + \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 + \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 + \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 + \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 + \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 + \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 + \param[out] none + \retval none +*/ +void ctc_refsource_prescaler_config(uint32_t ctc_prescaler) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); + CTC_CTL1 |= (uint32_t)ctc_prescaler; +} + +/*! + \brief configure clock trim base limit value + \param[in] ctc_limit_value: 8-bit clock trim base limit value + \param[out] none + \retval none +*/ +void ctc_clock_limit_value_config(uint8_t ctc_limit_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); + CTC_CTL1 |= (uint32_t)((uint32_t)ctc_limit_value << 16); +} + +/*! + \brief configure CTC counter reload value + \param[in] ctc_reload_value: 16-bit CTC counter reload value + \param[out] none + \retval none +*/ +void ctc_counter_reload_value_config(uint16_t ctc_reload_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); + CTC_CTL1 |= (uint32_t)ctc_reload_value; +} + +/*! + \brief read CTC counter capture value when reference sync pulse occurred + \param[in] none + \param[out] none + \retval the 16-bit CTC counter capture value +*/ +uint16_t ctc_counter_capture_value_read(void) +{ + uint16_t capture_value = 0U; + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> 16); + return (capture_value); +} + +/*! + \brief read CTC trim counter direction when reference sync pulse occurred + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + \arg SET: CTC trim counter direction is down-counting + \arg RESET: CTC trim counter direction is up-counting +*/ +FlagStatus ctc_counter_direction_read(void) +{ + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief read CTC counter reload value + \param[in] none + \param[out] none + \retval the 16-bit CTC counter reload value +*/ +uint16_t ctc_counter_reload_value_read(void) +{ + uint16_t reload_value = 0U; + reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); + return (reload_value); +} + +/*! + \brief read the IRC48M trim value + \param[in] none + \param[out] none + \retval the 8-bit IRC48M trim value +*/ +uint8_t ctc_irc48m_trim_value_read(void) +{ + uint8_t trim_value = 0U; + trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> 8); + return (trim_value); +} + +/*! + \brief enable the CTC interrupt + \param[in] ctc_interrupt: CTC interrupt enable + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_enable(uint32_t ctc_interrupt) +{ + CTC_CTL0 |= (uint32_t)ctc_interrupt; +} + +/*! + \brief disable the CTC interrupt + \param[in] ctc_interrupt: CTC interrupt enable source + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_disable(uint32_t ctc_interrupt) +{ + CTC_CTL0 &= (uint32_t)(~ctc_interrupt); +} + +/*! + \brief get CTC interrupt flag + \param[in] ctc_interrupt: the CTC interrupt flag + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) +{ + uint32_t interrupt = 0U, intenable = 0U; + + if(ctc_interrupt & CTC_FLAG_MASK){ + intenable = CTC_CTL0 & CTC_CTL0_ERRIE; + }else{ + intenable = CTC_CTL0 & ctc_interrupt; + } + interrupt = CTC_STAT & ctc_interrupt; + + if(interrupt && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CTC interrupt flag + \param[in] ctc_interrupt: the CTC interrupt flag + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval none +*/ +void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) +{ + if(ctc_interrupt & CTC_FLAG_MASK){ + CTC_INTC |= CTC_INTC_ERRIC; + }else{ + CTC_INTC |= ctc_interrupt; + } +} + +/*! + \brief get CTC flag + \param[in] ctc_flag: the CTC flag + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_flag_get(uint32_t ctc_flag) +{ + if(RESET != (CTC_STAT & ctc_flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CTC flag + \param[in] ctc_flag: the CTC flag + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval none +*/ +void ctc_flag_clear(uint32_t ctc_flag) +{ + if(ctc_flag & CTC_FLAG_MASK){ + CTC_INTC |= CTC_INTC_ERRIC; + }else{ + CTC_INTC |= ctc_flag; + } +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c new file mode 100644 index 00000000000..7f83159b9bc --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c @@ -0,0 +1,508 @@ +/*! + \file gd32f30x_dac.c + \brief DAC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_dac.h" + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DEN0; + }else{ + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DDMAEN0; + }else{ + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DDMAEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DBOFF0; + }else{ + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DBOFF0; + }else{ + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL |= DAC_CTL_DTEN0; + }else{ + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DTEN0; + }else{ + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT |= DAC_SWT_SWTR0; + }else{ + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph){ + DAC_SWT &= ~DAC_SWT_SWTR0; + }else{ + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph + \arg DACx(x =0,1) + \param[in] triggersource: external triggers of DAC + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F30X_CL) + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F30X_HD and GD32F30X_XD) + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + }else{ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << 16); + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] wave_mode + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + }else{ + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= wave_mode << 16; + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] bit_width + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + }else{ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= bit_width << 16; + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] unmask_bits + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + }else{ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= unmask_bits << 16; + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] amplitude + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + }else{ + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= amplitude << 16; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if(DAC0 == dac_periph){ + data = (uint16_t)DAC0_DO; + }else{ + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] dac_align + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if(DAC0 == dac_periph){ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + }else{ + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << 16) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << 16) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << 8) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c new file mode 100644 index 00000000000..eb9da382e27 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c @@ -0,0 +1,125 @@ +/*! + \file gd32f30x_dbg.c + \brief DBG driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_dbg.h" + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_CTL0 |= (uint32_t)dbg_periph; +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_CTL0 &= ~(uint32_t)dbg_periph; +} + +/*! + \brief enable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_enable(void) +{ + DBG_CTL0 |= DBG_CTL0_TRACE_IOEN; +} + +/*! + \brief disable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_disable(void) +{ + DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; +} + +/*! + \brief trace pin mode selection + \param[in] trace_mode: + \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 + \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 + \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 + \param[out] none + \retval none +*/ +void dbg_trace_pin_mode_set(uint32_t trace_mode) +{ + DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE; + DBG_CTL0 |= trace_mode; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c new file mode 100644 index 00000000000..ccd942e2956 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c @@ -0,0 +1,655 @@ +/*! + \file gd32f30x_dma.c + \brief DMA driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_dma.h" + +#define DMA_WRONG_HANDLE while(1){} + +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +#ifdef GD_MBED_USED +void dma_para_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct) +#else +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct) +#endif +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width, */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + }else{ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + }else{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set memory base address + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHMADDR(dma_periph, channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] priority: priority Level of this channel + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] mwidth: transfer data width of memory + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] pwidth: transfer data width of peripheral + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] direction: specify the direction of data transfer + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + if(DMA_PERIPHERAL_TO_MEMORY == direction){ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ + reval = SET; + }else{ + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag){ + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + DMA_WRONG_HANDLE + } + + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~source; +} + +/*! + \brief check whether peripheral and channels match + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) +{ + ErrStatus val = SUCCESS; + + if(DMA1 == dma_periph){ + if(channelx > DMA_CH4){ + val = ERROR; + } + } + + return val; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c new file mode 100644 index 00000000000..f307e9ea234 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c @@ -0,0 +1,3638 @@ +/*! + \file gd32f30x_enet.c + \brief ENET driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#include "gd32f30x_enet.h" + +#ifdef GD32F30X_CL + +#if defined (__CC_ARM) /*!< ARM compiler */ +__align(4) +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +__align(4) +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +__align(4) +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +__align(4) +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined ( __ICCARM__ ) /*!< IAR compiler */ +#pragma data_alignment=4 +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +#pragma data_alignment=4 +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +#pragma data_alignment=4 +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +#pragma data_alignment=4 +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined (__GNUC__) /* GNU Compiler */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ + +#endif /* __CC_ARM */ + +/* global transmit and receive descriptors pointers */ +enet_descriptors_struct *dma_current_txdesc; +enet_descriptors_struct *dma_current_rxdesc; + +/* structure pointer of ptp descriptor for normal mode */ +enet_descriptors_struct *dma_current_ptp_txdesc = NULL; +enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; + +/* init structure parameters for ENET initialization */ +static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + +static uint32_t enet_unknow_err = 0; +/* array of register offset for debug information get */ +static const uint16_t enet_reg_tab[] = { +0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, +0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + +0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + +0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + +0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, +0x104C, 0x1050, 0x1054}; + +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + +/*! + \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \param[in] none + \param[out] none + \retval none +*/ +void enet_deinit(void) +{ + rcu_periph_reset_enable(RCU_ENETRST); + rcu_periph_reset_disable(RCU_ENETRST); + enet_initpara_reset(); +} + +/*! + \brief configure the parameters which are usually less cared for initialization + note -- this function must be called before enet_init(), otherwise + configuration will be no effect + \param[in] option: different function option, which is related to several parameters, + only one parameter can be selected which is shown as below, refer to enet_option_enum + \arg FORWARD_OPTION: choose to configure the frame forward related parameters + \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters + \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters + \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters + \arg STORE_OPTION: choose to configure the store forward mode related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg VLAN_OPTION: choose to configure vlan related parameters + \arg FLOWCTL_OPTION: choose to configure flow control related parameters + \arg HASHH_OPTION: choose to configure hash high + \arg HASHL_OPTION: choose to configure hash low + \arg FILTER_OPTION: choose to configure frame filter related parameters + \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters + \arg TIMER_OPTION: choose to configure time counter related parameters + \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below + FORWARD_OPTION related parameters: + - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; + - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; + - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; + - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . + DMABUS_OPTION related parameters: + - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; + - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + DMA_MAXBURST_OPTION related parameters: + - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ + ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ + ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ + ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ + ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; + - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ + ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ + ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ + ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ + ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; + - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; + DMA_ARBITRATION_OPTION related parameters: + - ENET_ARBITRATION_RXPRIORTX + - ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ + ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. + STORE_OPTION related parameters: + - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; + - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; + - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ + ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; + - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ + ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ + ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ + ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . + DMA_OPTION related parameters: + - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; + - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE ; + - ENET_ENHANCED_DESCRIPTOR/ ENET_NORMAL_DESCRIPTOR . + VLAN_OPTION related parameters: + - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; + - MAC_VLT_VLTI(regval) . + FLOWCTL_OPTION related parameters: + - MAC_FCTL_PTM(regval) ; + - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; + - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; + - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . + HASHH_OPTION related parameters: + - 0x0~0xFFFF FFFFU + HASHL_OPTION related parameters: + - 0x0~0xFFFF FFFFU + FILTER_OPTION related parameters: + - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ + ENET_SRC_FILTER_DISABLE ; + - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; + - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ + ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; + - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ + ENET_UNICAST_FILTER_PERFECT ; + - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + HALFDUPLEX_OPTION related parameters: + - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; + - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; + - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; + - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ + ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; + - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . + TIMER_OPTION related parameters: + - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; + - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; + INTERFRAMEGAP_OPTION related parameters: + - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ + ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ + ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ + ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . + \param[out] none + \retval none +*/ +void enet_initpara_config(enet_option_enum option, uint32_t para) +{ + switch(option){ + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + +#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE + para &= ~ENET_ENHANCED_DESCRIPTOR; +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared + parameters + \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation + \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex + \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex + \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex + \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex + \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII + \param[in] checksum: IP frame checksum offload function, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function + \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function + \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped + \param[in] recept: frame filter function, only one parameter can be selected + which is shown as below, refer to enet_frmrecept_enum + \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled + \arg ENET_RECEIVEALL: all received frame are forwarded to application + \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames + \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +{ + uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t media_temp = 0U; + uint32_t timeout = 0U; + uint16_t phy_value = 0U; + ErrStatus phy_state= ERROR, enet_state = ERROR; + + /* PHY interface configuration, configure SMI clock and reset PHY chip */ + if(ERROR == enet_phy_config()){ + _ENET_DELAY_(PHY_RESETDELAY); + if(ERROR == enet_phy_config()){ + return enet_state; + } + } + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ + /* wait for PHY_LINKED_STATUS bit be set */ + do{ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + }while((RESET == phy_value) && (timeout < PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout){ + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state){ + /* return ERROR due to write timeout */ + return enet_state; + } + + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do{ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* return ERROR due to timeout */ + if(PHY_READ_TO == timeout){ + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + /* configure the duplex mode of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ + media_temp = ENET_MODE_FULLDUPLEX; + }else{ + media_temp = ENET_MODE_HALFDUPLEX; + } + /* configure the communication speed of MAC following the auto-negotiation result */ + if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ + media_temp |= ENET_SPEEDMODE_10M; + }else{ + media_temp |= ENET_SPEEDMODE_100M; + } + }else{ + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state){ + /* return ERROR due to write timeout */ + return enet_state; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); + } + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; + + + /* 2st, configure checksum */ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; + } + + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD)); + temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } + + /* configure dmabus_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ + temp = enet_initpara.dmabus_mode; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_maxburst related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + temp = enet_initpara.dma_maxburst; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_arbitration related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + temp = enet_initpara.dma_arbitration; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure store_forward_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + temp = enet_initpara.store_forward_mode; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } + + /* configure dma_function related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); + temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + + reg_value = ENET_DMA_BCTL; + temp = reg_temp; + /* configure ENET_DMA_BCTL register */ + reg_value &= (~ENET_DMA_BCTL_DFM); + temp &= ENET_DMA_BCTL_DFM; + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure vlan_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + reg_temp = enet_initpara.vlan_config; + + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } + + /* configure flow_control related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } + + /* configure hashtable_high related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + ENET_MAC_HLH = enet_initpara.hashtable_high; + } + + /* configure hashtable_low related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + ENET_MAC_HLL = enet_initpara.hashtable_low; + } + + /* configure framesfilter_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } + + /* configure halfduplex_param related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + reg_temp = enet_initpara.halfduplex_param; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure timer_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + reg_temp = enet_initpara.timer_config; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure interframegap related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + reg_temp = enet_initpara.interframegap; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + enet_state = SUCCESS; + return enet_state; +} + +/*! + \brief reset all core internal registers located in CLK_TX and CLK_RX + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_software_reset(void) +{ + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + uint32_t dma_flag; + + /* reset all core internal registers located in CLK_TX and CLK_RX */ + ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; + + /* wait for reset operation complete */ + do{ + dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); + timeout++; + }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief check receive frame valid and return frame size + \param[in] none + \param[out] none + \retval size of received frame: 0x0 - 0x3FFF +*/ +uint32_t enet_rxframe_size_get(void) +{ + uint32_t size = 0U; + uint32_t status; + + /* get rdes0 information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + + /* if the desciptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ + return 0U; + } + + /* if has any error, or the frame uses two or more descriptors */ + if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#else + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#endif + /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + /* get the size of the received data including CRC */ + size = GET_RDES0_FRML(status); + /* substract the CRC size */ + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ + size = size + 4U; + } + }else{ + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; + } + + /* return packet size */ + return size; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode */ + desc_status = ENET_TDES0_TCHM; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief handle current received frame data to application buffer + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the received frame data + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offsetbuffer1_addr) + offset)); + } + + }else{ + /* return ERROR */ + return ERROR; + } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief handle application buffer data to transmit it + \param[in] buffer: pointer to the frame data to be transmitted, + note -- if the input is NULL, user should handle the data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) +{ + uint32_t offset = 0U; + uint32_t dma_tbu_flag, dma_tu_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++){ + (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief configure the transmit IP frame checksum offload calculation and insertion + \param[in] desc: the descriptor pointer which users want to configure + \param[in] checksum: IP frame checksum configuration + only one parameter can be selected which is shown as below + \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled + \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled + \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header + \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated + \param[out] none + \retval none +*/ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) +{ + desc->status &= ~ENET_TDES0_CM; + desc->status |= checksum; +} + +/*! + \brief ENET Tx and Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_enable(void) +{ + enet_tx_enable(); + enet_rx_enable(); +} + +/*! + \brief ENET Tx and Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_disable(void) +{ + enet_tx_disable(); + enet_rx_disable(); +} + +/*! + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: set MAC address 0 filter + \arg ENET_MAC_ADDRESS1: set MAC address 1 filter + \arg ENET_MAC_ADDRESS2: set MAC address 2 filter + \arg ENET_MAC_ADDRESS3: set MAC address 3 filter + \param[in] paddr: the buffer pointer which stores the MAC address + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \param[out] none + \retval none +*/ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); + REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); +} + +/*! + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: get MAC address 0 filter + \arg ENET_MAC_ADDRESS1: get MAC address 1 filter + \arg ENET_MAC_ADDRESS2: get MAC address 2 filter + \arg ENET_MAC_ADDRESS3: get MAC address 3 filter + \param[out] paddr: the buffer pointer which is stored the MAC address + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \retval none +*/ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); + paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); + paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); + paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); + paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); + paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); +} + +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + }else{ + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + }else{ + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + +/*! + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; +} + +/*! + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; +} + +/*! + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; +} + +/*! + \brief ENET Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; + ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; +} + +/*! + \brief put registers value into the application buffer + \param[in] type: register type which will be get, refer to enet_registers_type_enum, + only one parameter can be selected which is shown as below + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT + \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL + \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR + \param[in] num: the number of registers that the user want to get + \param[out] preg: the application buffer pointer for storing the register value + \retval none +*/ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) +{ + uint32_t offset = 0U, max = 0U, limit = 0U; + + offset = (uint32_t)type; + max = (uint32_t)type + num; + limit = sizeof(enet_reg_tab)/sizeof(uint16_t); + + /* prevent element in this array is out of range */ + if(max > limit){ + max = limit; + } + + for(; offset < max; offset++){ + /* get value of the corresponding register */ + *preg = REG32((ENET) + enet_reg_tab[offset]); + preg++; + } +} + +/*! + \brief get the enet debug status from the debug register + \param[in] mac_debug: enet debug status, + only one parameter can be selected which is shown as below + \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state + \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status + \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation + \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status + \arg ENET_RXFIFO_STATE: RxFIFO state + \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state + \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter + \arg ENET_PAUSE_CONDITION_STATUS: pause condition status + \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status + \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation + \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty + \arg ENET_TXFIFO_FULL: TxFIFO is full + \param[out] none + \retval value of the status users want to get +*/ +uint32_t enet_debug_status_get(uint32_t mac_debug) +{ + uint32_t temp_state = 0U; + + switch(mac_debug){ + case ENET_RX_ASYNCHRONOUS_FIFO_STATE: + temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_STATE: + temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); + break; + case ENET_MAC_TRANSMITTER_STATUS: + temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); + break; + case ENET_TXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); + break; + default: + if(RESET != (ENET_MAC_DBG & mac_debug)){ + temp_state = 0x1U; + } + break; + } + return temp_state; +} + +/*! + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable + \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_enable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_disable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter + \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter + \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter + \param[in] addr_mask: select which MAC address bytes will be mask, + one or more parameters can be selected which are shown as below + \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits + \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits + \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits + \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits + \param[in] filter_type: select which MAC address filter type will be selected, + only one parameter can be selected which is shown as below + \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame + \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame + \param[out] none + \retval none +*/ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +{ + uint32_t reg; + + /* get the address filter register value which is to be configured */ + reg = REG32(ENET_ADDRH_BASE + mac_addr); + + /* clear and configure the address filter register */ + reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); + reg |= (addr_mask | filter_type); + REG32(ENET_ADDRH_BASE + mac_addr) = reg; +} + +/*! + \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_config(void) +{ + uint32_t ahbclk; + uint32_t reg; + uint16_t phy_value; + ErrStatus enet_state = ERROR; + + /* clear the previous MDC clock */ + reg = ENET_MAC_PHY_CTL; + reg &= ~ENET_MAC_PHY_CTL_CLR; + + /* get the HCLK frequency */ + ahbclk = rcu_clock_freq_get(CK_AHB); + + /* configure MDC clock according to HCLK frequency range */ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + reg |= ENET_MDC_HCLK_DIV16; + }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + reg |= ENET_MDC_HCLK_DIV26; + }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ + reg |= ENET_MDC_HCLK_DIV42; + }else if((ENET_RANGE(ahbclk, 100000000U, 120000000U))||(120000000U == ahbclk)){ + reg |= ENET_MDC_HCLK_DIV62; + }else{ + return enet_state; + } + ENET_MAC_PHY_CTL = reg; + + /* reset PHY */ + phy_value = PHY_RESET; + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + return enet_state; + } + /* PHY reset need some time */ + _ENET_DELAY_(ENET_DELAY_TO); + + /* check whether PHY reset is complete */ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + return enet_state; + } + + /* PHY reset complete */ + if(RESET == (phy_value & PHY_RESET)){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief write to / read from a PHY register + \param[in] direction: only one parameter can be selected which is shown as below + \arg ENET_PHY_WRITE: write data to phy register + \arg ENET_PHY_READ: read data from phy register + \param[in] phy_address: 0x0 - 0x1F + \param[in] phy_reg: 0x0 - 0x1F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +{ + uint32_t reg, phy_flag; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* configure ENET_MAC_PHY_CTL with write/read operation */ + reg = ENET_MAC_PHY_CTL; + reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + + /* if do the write operation, write value to the register */ + if(ENET_PHY_WRITE == direction){ + ENET_MAC_PHY_DATA = *pvalue; + } + + /* do PHY write/read operation, and wait the operation complete */ + ENET_MAC_PHY_CTL = reg; + do{ + phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); + timeout++; + } + while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + enet_state = SUCCESS; + } + + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction){ + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + } + + return enet_state; +} + +/*! + \brief enable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_enable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* enable the PHY loopback mode */ + temp_phy |= PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief disable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_disable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* disable the PHY loopback mode */ + temp_phy &= (uint16_t)~PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief enable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_enable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG |= mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL |= (mask >> 2); +} + +/*! + \brief disable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function + \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC + \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_forward_feature_disable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG &= ~mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL &= ~(mask >> 2); +} + +/*! + \brief enable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_enable(uint32_t feature) +{ + ENET_MAC_FRMF |= feature; +} + +/*! + \brief disable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_disable(uint32_t feature) +{ + ENET_MAC_FRMF &= ~feature; +} + +/*! + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + this function only use in full-dulex mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state =ERROR; + uint32_t temp = 0U; + + /* in full-duplex mode, must make sure this bit is 0 before writing register */ + temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; + if(RESET == temp){ + ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; + enet_state = SUCCESS; + } + return enet_state; +} + +/*! + \brief configure the pause frame detect type + \param[in] detect: pause frame detect type, + only one parameter can be selected which is shown as below + \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also + use the MAC0 address to detecting pause frame + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + in IEEE802.3 can be detected + \param[out] none + \retval none +*/ +void enet_pauseframe_detect_config(uint32_t detect) +{ + ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; + ENET_MAC_FCTL |= detect; +} + +/*! + \brief configure the pause frame parameters + \param[in] pausetime: pause time in transmit pause control frame + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, + this value must make sure to be less than configured pause time, only one parameter can be + selected which is shown as below + \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times + \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times + \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times + \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times + \param[out] none + \retval none +*/ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) +{ + ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); + ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); +} + +/*! + \brief configure the threshold of the flow control(deactive and active threshold) + \param[in] deactive: the threshold of the deactive flow control, this value + should always be less than active flow control value, only one + parameter can be selected which is shown as below + \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[in] active: the threshold of the active flow control, only one parameter + can be selected which is shown as below + \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[out] none + \retval none +*/ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) +{ + ENET_MAC_FCTH = ((deactive | active) >> 8); +} + +/*! + \brief enable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_enable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL |= feature; +} + +/*! + \brief disable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_disable(uint32_t feature) +{ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL &= ~feature; +} + +/*! + \brief get the dma transmit/receive process state + \param[in] direction: choose the direction of dma process which users want to check, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: dma transmit process + \arg ENET_DMA_RX: dma receive process + \param[out] none + \retval state of dma process, the value range shows below: + ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, + ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, + ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, + ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING +*/ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) +{ + uint32_t reval; + reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); + return reval; +} + +/*! + \brief poll the DMA transmission/reception enable by writing any value to the + ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception + \param[in] direction: choose the direction of DMA process which users want to resume, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA transmit process + \arg ENET_DMA_RX: DMA receive process + \param[out] none + \retval none +*/ +void enet_dmaprocess_resume(enet_dmadirection_enum direction) +{ + if(ENET_DMA_TX == direction){ + ENET_DMA_TPEN = 0U; + }else{ + ENET_DMA_RPEN = 0U; + } +} + +/*! + \brief check and recover the Rx process + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxprocess_check_recovery(void) +{ + uint32_t status; + + /* get DAV information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + status &= ENET_RDES0_DAV; + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with + receive descriptor address pointer updated by RxDMA controller */ + if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && + (ENET_RDES0_DAV == status)){ + dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + } +} + +/*! + \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_txfifo_flush(void) +{ + uint32_t flush_state; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* set the FTF bit for flushing transmit FIFO */ + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + /* wait until the flush operation completes */ + do{ + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + timeout++; + }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(RESET == flush_state){ + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, + only one parameter can be selected which is shown as below + \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table + \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by + the RxDMA controller + \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller + \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table + \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by + the TxDMA controller + \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller + \param[out] none + \retval address value +*/ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) +{ + uint32_t reval = 0U; + + reval = REG32((ENET) +(uint32_t)addr_get); + return reval; +} + +/*! + \brief get the Tx or Rx descriptor information + \param[in] desc: the descriptor pointer which users want to get information + \param[in] info_get: the descriptor information type which is selected, + only one parameter can be selected which is shown as below + \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size + \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size + \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer + \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted + \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame + \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame + \param[out] none + \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter +*/ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch(info_get){ + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ + reval = reval + 4U; + } + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; + } + return reval; +} + +/*! + \brief get the number of missed frames during receiving + \param[in] none + \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO + \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller + \retval none +*/ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) +{ + uint32_t temp_counter = 0U; + + temp_counter = ENET_DMA_MFBOCNT; + *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); + *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); +} + +/*! + \brief get the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_UFE: underflow error + \arg ENET_TDES0_EXD: excessive deferral + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_ECO: excessive collision + \arg ENET_TDES0_LCO: late collision + \arg ENET_TDES0_NCA: no carrier + \arg ENET_TDES0_LCA: loss of carrier + \arg ENET_TDES0_IPPE: IP payload error + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_JT: jabber timeout + \arg ENET_TDES0_ES: error summary + \arg ENET_TDES0_IPHE: IP header error + \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + + \arg ENET_RDES0_PCERR: payload checksum error + \arg ENET_RDES0_EXSV: extended status valid + \arg ENET_RDES0_CERR: CRC error + \arg ENET_RDES0_DBERR: dribble bit error + \arg ENET_RDES0_RERR: receive error + \arg ENET_RDES0_RWDT: receive watchdog timeout + \arg ENET_RDES0_FRMT: frame type + \arg ENET_RDES0_LCO: late collision + \arg ENET_RDES0_IPHERR: IP frame header error + \arg ENET_RDES0_TSV: timestamp valid + \arg ENET_RDES0_LDES: last descriptor + \arg ENET_RDES0_FDES: first descriptor + \arg ENET_RDES0_VTAG: VLAN tag + \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_LERR: length error + \arg ENET_RDES0_SAFF: SA filter fail + \arg ENET_RDES0_DERR: descriptor error + \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_DAFF: destination address filter fail + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + FlagStatus enet_flag = RESET; + + if ((uint32_t)RESET != (desc->status & desc_flag)){ + enet_flag = SET; + } + + return enet_flag; +} + +/*! + \brief set the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to set flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status |= desc_flag; +} + +/*! + \brief clear the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to clear flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status &= ~desc_flag; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc) +{ + desc->control_buffer_size &= ~ENET_RDES1_DINTC; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \param[in] desc: the descriptor pointer which users want to configure + \param[in] delay_time: delay a time of 256*delay_time HCLK, this value must be between 0 and 0xFF + \param[out] none + \retval none +*/ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) +{ + desc->control_buffer_size |= ENET_RDES1_DINTC; + ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); +} + +/*! + \brief drop current receive frame + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxframe_drop(void) +{ + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } + + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc){ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + } + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc){ + dma_current_ptp_rxdesc++; + } + } + } +} + +/*! + \brief enable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_enable(uint32_t feature) +{ + ENET_DMA_CTL |= feature; +} + +/*! + \brief disable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_disable(uint32_t feature) +{ + ENET_DMA_CTL &= ~feature; +} + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/*! + \brief get the bit of extended status flag in ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get the extended status flag + \param[in] desc_status: the extended status want to get, + only one parameter can be selected which is shown as below + \arg ENET_RDES4_IPPLDT: IP frame payload type + \arg ENET_RDES4_IPHERR: IP frame header error + \arg ENET_RDES4_IPPLDERR: IP frame payload error + \arg ENET_RDES4_IPCKSB: IP frame checksum bypassed + \arg ENET_RDES4_IPF4: IP frame in version 4 + \arg ENET_RDES4_IPF6: IP frame in version 6 + \arg ENET_RDES4_PTPMT: PTP message type + \arg ENET_RDES4_PTPOEF: PTP on ethernet frame + \arg ENET_RDES4_PTPVF: PTP version format + \param[out] none + \retval value of extended status +*/ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch (desc_status){ + case ENET_RDES4_IPPLDT: + reval = GET_RDES4_IPPLDT(desc->extended_status); + break; + case ENET_RDES4_PTPMT: + reval = GET_RDES4_PTPMT(desc->extended_status); + break; + default: + if ((uint32_t)RESET != (desc->extended_status & desc_status)){ + reval = 1U; + }else{ + reval = 0U; + } + } + + return reval; +} + +/*! + \brief configure descriptor to work in enhanced mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_enhanced_mode(void) +{ + ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configuration each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configure each descriptor */ + for(num=0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + uint32_t timeout = 0U; + uint32_t rdes0_tsv_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0; offset < size; offset++){ + (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); + } + }else{ + return ERROR; + } + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp){ + /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and + write to the RDES6 and RDES7 */ + do{ + rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); + timeout++; + }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + return ERROR; + } + + /* clear the ENET_RDES0_TSV flag */ + dma_current_rxdesc->status &= ~ENET_RDES0_TSV; + /* get the timestamp value of the received frame */ + timestamp[0] = dma_current_rxdesc->timestamp_low; + timestamp[1] = dma_current_rxdesc->timestamp_high; + } + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* Clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0; + uint32_t dma_tbu_flag, dma_tu_flag; + uint32_t tdes0_ttmss_flag; + uint32_t timeout = 0; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0; offset < length; offset++){ + (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* Clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp){ + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do{ + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->timestamp_low; + timestamp[1] = dma_current_txdesc->timestamp_high; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +#else + +/*! + \brief configure descriptor to work in normal mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_normal_mode(void) +{ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if(num < (count - 1U)){ + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + }else{ + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction){ + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + }else{ + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive ring mode and set buffer1 size */ + desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for(num = 0U; num < count; num++){ + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if(num == (count - 1U)){ + if (ENET_DMA_TX == direction){ + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + }else{ + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] timestamp: pointer to the table which stores the timestamp high and low + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer){ + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize){ + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++){ + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + + }else{ + return ERROR; + } + } + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0U, timeout = 0U; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + + /* the descriptor is busy due to own by the DMA */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if(length > ENET_MAX_FRAME_SIZE){ + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer){ + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++){ + (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp){ + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do{ + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_txdesc->status){ + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); + }else{ + /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + }else{ + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); + }else{ + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } + } + return SUCCESS; +} + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/*! + \brief wakeup frame filter register pointer reset + \param[in] none + \param[out] none + \retval none +*/ +void enet_wum_filter_register_pointer_reset(void) +{ + ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; +} + +/*! + \brief set the remote wakeup frame registers + \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) + \param[out] none + \retval none +*/ +void enet_wum_filter_config(uint32_t pdata[]) +{ + uint32_t num = 0U; + + /* configure ENET_MAC_RWFF register */ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + ENET_MAC_RWFF = pdata[num]; + } +} + +/*! + \brief enable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_POWER_DOWN: power down mode + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_enable(uint32_t feature) +{ + ENET_MAC_WUM |= feature; +} + +/*! + \brief disable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_disable(uint32_t feature) +{ + ENET_MAC_WUM &= (~feature); +} + +/*! + \brief reset the MAC statistics counters + \param[in] none + \param[out] none + \retval none +*/ +void enet_msc_counters_reset(void) +{ + /* reset all counters */ + ENET_MSC_CTL |= ENET_MSC_CTL_CTR; +} + +/*! + \brief enable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_enable(uint32_t feature) +{ + ENET_MSC_CTL |= feature; +} + +/*! + \brief disable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_disable(uint32_t feature) +{ + ENET_MSC_CTL &= (~feature); +} + +/*! + \brief configure MAC statistics counters preset mode + \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum, + only one parameter can be selected which is shown as below + \arg ENET_MSC_PRESET_NONE: do not preset MSC counter + \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value + \arg ENET_MSC_PRESET_FULL: preset all MSC counters to almost-full(0xFFFF FFF0) value + \param[out] none + \retval none +*/ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode) +{ + ENET_MSC_CTL &= ENET_MSC_PRESET_MASK; + ENET_MSC_CTL |= (uint32_t)mode; +} + +/*! + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, + only one parameter can be selected which is shown as below + \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter + \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter + \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter + \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter + \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter + \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter + \param[out] none + \retval the MSC counter value +*/ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) +{ + uint32_t reval; + + reval = REG32((ENET + (uint32_t)counter)); + + return reval; +} + +/*! + \brief change subsecond to nanosecond + \param[in] subsecond: subsecond value + \param[out] none + \retval the nanosecond value +*/ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) +{ + uint64_t val = subsecond * 1000000000Ull; + val >>= 31; + return (uint32_t)val; +} + +/*! + \brief change nanosecond to subsecond + \param[in] nanosecond: nanosecond value + \param[out] none + \retval the subsecond value +*/ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) +{ + uint64_t val = nanosecond * 0x80000000Ull; + val /= 1000000000U; + return (uint32_t)val; +} + +/*! + \brief enable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_enable(uint32_t feature) +{ + ENET_PTP_TSCTL |= feature; +} + +/*! + \brief disable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_disable(uint32_t feature) +{ + ENET_PTP_TSCTL &= ~feature; +} + +/*! + \brief configure the PTP timestamp function + \param[in] func: only one parameter can be selected which is shown as below + \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp + \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp + \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp + \arg ENET_CKNT_PEER_TO_PEER: type of peer-to-peer transparent clock node type for timestamp + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating + \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating + \arg ENET_SUBSECOND_DIGITAL_ROLLOVER: digital rollover mode + \arg ENET_SUBSECOND_BINARY_ROLLOVER: binary rollover mode + \arg ENET_SNOOPING_PTP_VERSION_2: version 2 + \arg ENET_SNOOPING_PTP_VERSION_1: version 1 + \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + management and signaling message + \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message + \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) +{ + uint32_t temp_config = 0U, temp_state = 0U; + uint32_t timeout = 0U; + ErrStatus enet_state = SUCCESS; + + switch(func){ + case ENET_CKNT_ORDINARY: + case ENET_CKNT_BOUNDARY: + case ENET_CKNT_END_TO_END: + case ENET_CKNT_PEER_TO_PEER: + ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; + ENET_PTP_TSCTL |= (uint32_t)func; + break; + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do{ + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do{ + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do{ + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout){ + enet_state = ERROR; + }else{ + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))){ + ENET_PTP_TSCTL |= temp_config; + }else{ + ENET_PTP_TSCTL &= ~temp_config; + } + break; + } + + return enet_state; +} + +/*! + \brief configure system time subsecond increment value + \param[in] subsecond: the value will be added to the subsecond value of system time, + this value must be between 0 and 0xFF + \param[out] none + \retval none +*/ +void enet_ptp_subsecond_increment_config(uint32_t subsecond) +{ + ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); +} + +/*! + \brief adjusting the clock frequency only in fine update mode + \param[in] add: the value will be added to the accumulator register to achieve time synchronization + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_addend_config(uint32_t add) +{ + ENET_PTP_TSADDEND = add; +} + +/*! + \brief initialize or add/subtract to second of the system time + \param[in] sign: timestamp update positive or negative sign, + only one parameter can be selected which is shown as below + \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time + \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time + \param[in] second: initializing or adding/subtracting to second of the system time + \param[in] subsecond: the current subsecond of the system time + with 0.46 ns accuracy if required accuracy is 20 ns + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) +{ + ENET_PTP_TSUH = second; + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); +} + +/*! + \brief configure the expected target time + \param[in] second: the expected target second time + \param[in] nanosecond: the expected target nanosecond time (signed) + \param[out] none + \retval none +*/ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) +{ + ENET_PTP_ETH = second; + ENET_PTP_ETL = nanosecond; +} + +/*! + \brief get the current system time + \param[in] none + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \retval none +*/ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) +{ + uint32_t temp_sec = 0U, temp_subs = 0U; + + /* get the value of sysytem time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; + temp_subs = (uint32_t)ENET_PTP_TSL; + + /* get sysytem time and construct the enet_ptp_systime_struct structure */ + systime_struct->second = temp_sec; + systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); + systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); + systime_struct->sign = GET_PTP_TSL_STS(temp_subs); +} + +/*! + \brief configure the PPS output frequency + \param[in] freq: PPS output frequency, + only one parameter can be selected which is shown as below + \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency + \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency + \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency + \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency + \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency + \arg ENET_PPSOFC_8192HZ: PPS output 8192Hz frequency + \arg ENET_PPSOFC_16384HZ: PPS output 16384Hz frequency + \arg ENET_PPSOFC_32768HZ: PPS output 32768Hz frequency + \param[out] none + \retval none +*/ +void enet_ptp_pps_output_frequency_config(uint32_t freq) +{ + ENET_PTP_PPSCTL = freq; +} + +/*! + \brief configure and start PTP timestamp counter + \param[in] updatemethod: method for updating + \arg ENET_PTP_FINEMODE: fine correction method + \arg ENET_PTP_COARSEMODE: coarse correction method + \param[in] init_sec: second value for initializing system time + \param[in] init_subsec: subsecond value for initializing system time + \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) + \param[in] accuracy_cfg: the value to be added to the subsecond value of system time + \param[out] none + \retval none +*/ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) +{ + /* mask the timestamp trigger interrupt */ + enet_interrupt_disable(ENET_MAC_INT_TMSTIM); + + /* enable timestamp */ + enet_ptp_feature_enable(ENET_ALL_RX_TIMESTAMP | ENET_RXTX_TIMESTAMP); + + /* configure system time subsecond increment based on the PTP clock frequency */ + enet_ptp_subsecond_increment_config(accuracy_cfg); + + if(ENET_PTP_FINEMODE == updatemethod){ + /* fine correction method: configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); + /* wait until update is completed */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ + } + } + + /* choose the fine correction method */ + enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + enet_desc_select_enhanced_mode(); +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ +} + +/*! + \brief adjust frequency in fine method by configure addend register + \param[in] carry_cfg: the value to be added to the accumulator register + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) +{ + /* re-configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief update system time in coarse method + \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) +{ + uint32_t subsecond_val; + uint32_t carry_cfg; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* save the carry_cfg value */ + carry_cfg = ENET_PTP_TSADDEND_TMSA; + + /* update the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); + + /* wait until the update is completed */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ + } + + /* write back the carry_cfg value, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief set system time in fine method + \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) +{ + uint32_t subsecond_val; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + + /* wait until the system time initialzation finished */ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ + } +} + +/*! + \brief get the ptp flag status + \param[in] flag: ptp flag status to be checked + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_ptp_flag_get(uint32_t flag) +{ + FlagStatus bitstatus = RESET; + + if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ + bitstatus = SET; + } + + return bitstatus; +} + +/*! + \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \param[in] none + \param[out] none + \retval none +*/ +void enet_initpara_reset(void) +{ + enet_initpara.option_enable = 0U; + enet_initpara.forward_frame = 0U; + enet_initpara.dmabus_mode = 0U; + enet_initpara.dma_maxburst = 0U; + enet_initpara.dma_arbitration = 0U; + enet_initpara.store_forward_mode = 0U; + enet_initpara.dma_function = 0U; + enet_initpara.vlan_config = 0U; + enet_initpara.flow_control = 0U; + enet_initpara.hashtable_high = 0U; + enet_initpara.hashtable_low = 0U; + enet_initpara.framesfilter_mode = 0U; + enet_initpara.halfduplex_param = 0U; + enet_initpara.timer_config = 0U; + enet_initpara.interframegap = 0U; +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \param[in] none + \param[out] none + \retval none +*/ +static void enet_default_init(void) +{ + uint32_t reg_value = 0U; + + /* MAC */ + /* configure ENET_MAC_CFG register */ + reg_value = ENET_MAC_CFG; + reg_value &= MAC_CFG_MASK; + reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ + | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; + ENET_MAC_CFG = reg_value; + + /* configure ENET_MAC_FRMF register */ + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ + |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ + |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ + |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + + /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ + ENET_MAC_HLH = 0x0U; + + ENET_MAC_HLL = 0x0U; + + /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ + reg_value = ENET_MAC_FCTL; + reg_value &= MAC_FCTL_MASK; + reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ + |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ + |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + + ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; + + /* configure ENET_MAC_VLT register */ + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); + + /* DMA */ + /* configure ENET_DMA_CTL register */ + reg_value = ENET_DMA_CTL; + reg_value &= DMA_CTL_MASK; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ + |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ + |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ + |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ + |ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; + + /* configure ENET_DMA_BCTL register */ + reg_value = ENET_DMA_BCTL; + reg_value &= DMA_BCTL_MASK; + reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ + |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ + |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ + |ENET_NORMAL_DESCRIPTOR; + ENET_DMA_BCTL = reg_value; +} + +#ifndef USE_DELAY +/*! + \brief insert a delay time + \param[in] ncount: specifies the delay time length + \param[out] none + \param[out] none +*/ +static void enet_delay(uint32_t ncount) +{ + __IO uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--){ + } +} +#endif /* USE_DELAY */ + +#endif /* GD32F30X_CL */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c new file mode 100644 index 00000000000..96072e5df16 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c @@ -0,0 +1,629 @@ +/*! + \file gd32f30x_exmc.c + \brief EXMC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL_REGION0_RESET ((uint32_t)0x000030DBU) +#define BANK0_SNCTL_REGION1_2_3_RESET ((uint32_t)0x000030D2U) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC bank1/2 register reset mask*/ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC bank3 register reset mask*/ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) +#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) +#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) +#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) + +#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) +#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) + +#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) +#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) +#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) + +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) + +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) + +#define INTEN_INTS_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] exmc_norsram_region: select the region of bank0 + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t exmc_norsram_region) +{ + /* reset the registers */ + if(EXMC_BANK0_NORSRAM_REGION0 == exmc_norsram_region){ + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET; + }else{ + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET; + } + EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; + EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 + write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + write_timing: struct exmc_norsram_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | + EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | + EXMC_SNCTL_SYNCWR )); + + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| + (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | + (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | + (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* nor flash access enable */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* extended mode configure */ + if(ENABLE == exmc_norsram_init_struct->extended_mode){ + snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET ) | + (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD )| + (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & EXMC_SNWTCFG_WDSET )| + (((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_SNWTCFG_WBUSLAT ) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + }else{ + snwtcfg = BANK0_SNWTCFG_RESET; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; +} + +/*! + \brief initialize the struct exmc_norsram_parameter_struct + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + /* configure the structure with default value */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* read/write timing configure */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* write timing configure, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! + \brief CRAM page size configure + \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[in] page_size: CRAM page size + \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access + \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes + \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes + \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes + \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes + \param[out] none + \retval none +*/ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) +{ + /* reset the bits */ + EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; + + /* set the CPS bits */ + EXMC_SNCTL(exmc_norsram_region) |= page_size; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief deinitialize EXMC NAND bank + \param[in] exmc_nand_bank: select the bank of NAND + \arg EXMC_BANKx_NAND(x=1..2) + \param[out] none + \retval none +*/ +void exmc_nand_deinit(uint32_t exmc_nand_bank) +{ + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET; + EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET; + EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET; + EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; +} + +/*! + \brief initialize EXMC NAND bank + \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter + nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND + ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + ecc_logic: ENABLE or DISABLE + databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; + EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; + EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; +} + +/*! + \brief initialize the struct exmc_norsram_parameter_struct + \param[in] none + \param[out] the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + /* configure the structure with default value */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xfcU; + exmc_nand_init_struct->common_space_timing->waittime = 0xfcU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xfcU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xfcU; +} + +/*! + \brief enable NAND bank + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_enable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable NAND bank + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_disable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_NDBKEN); +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) +{ + if (ENABLE == newvalue){ + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; + }else{ + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_ECCEN); + } +} + +/*! + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) +{ + return (EXMC_NECC(exmc_nand_bank)); +} + +/*! + \brief deinitialize EXMC PC card bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_deinit(void) +{ + /* EXMC_BANK3_PCCARD */ + EXMC_NPCTL3 = BANK3_NPCTL_RESET; + EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; + EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; + EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; + EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; +} + +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| + (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); +} + +/*! + \brief initialize the struct exmc_pccard_parameter_struct + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the structure with default value */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief enable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_enable(void) +{ + EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_disable(void) +{ + EXMC_NPCTL3 &= (~EXMC_NPCTL_NDBKEN); +} + +/*! + \brief check EXMC flag is set or not + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC Card bank + \param[in] flag: specify get which flag + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) +{ + uint32_t status = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + + if ((status & flag) != (uint32_t)flag ){ + /* flag is reset */ + return RESET; + }else{ + /* flag is set */ + return SET; + } +} + +/*! + \brief clear EXMC flag + \param[in] exmc_bank: specifie the NAND bank , PCCARD bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] flag: specify get which flag + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval none +*/ +void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= (~flag); +} + +/*! + \brief check EXMC interrupt flag is set or not + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) +{ + uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); + + interrupt_enable = (status & interrupt_source); + + if ((interrupt_enable) && (interrupt_state)){ + /* interrupt flag is set */ + return SET; + }else{ + /* interrupt flag is reset */ + return RESET; + } +} + +/*! + \brief clear EXMC interrupt flag + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); +} + +/*! + \brief enable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank,PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) |= interrupt_source; +} + +/*! + \brief disable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= (~interrupt_source); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c new file mode 100644 index 00000000000..2eee70b00d4 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c @@ -0,0 +1,227 @@ +/*! + \file gd32f30x_exti.c + \brief EXTI driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_exti.h" + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x00000000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode){ + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type){ + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c new file mode 100644 index 00000000000..60470b6af8b --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c @@ -0,0 +1,927 @@ +/*! + \file gd32f30x_fmc.c + \brief FMC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_fmc.h" + +/*! + \brief set the wait state counter value + \param[in] wscnt:wait state counter value + \arg WS_WSCNT_0: FMC 0 wait + \arg WS_WSCNT_1: FMC 1 wait + \arg WS_WSCNT_2: FMC 2 wait + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* write the FMC unlock key */ + if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } + } +} + +/*! + \brief unlock the FMC bank0 operation + this function can be used for all GD32F30x devices. + for GD32F30x with flash more than 512KB, this function unlocks bank0. + for GD32F30x with flash no more than 512KB and it is equivalent to fmc_unlock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_unlock(void) +{ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } +} + +/*! + \brief unlock the FMC bank1 operation + this function can be used for GD32F30x with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_unlock(void) +{ + if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ + /* write the FMC unlock key */ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit */ + FMC_CTL0 |= FMC_CTL0_LK; + + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* set the LK bit */ + FMC_CTL1 |= FMC_CTL1_LK; + } +} + +/*! + \brief lock the FMC bank0 operation + this function can be used for all GD32F30X devices. + for GD32F30x with flash more than 512KB, this function locks bank0. + for GD32F30x with flash no more than 512KB and it is equivalent to fmc_lock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_lock(void) +{ + /* set the LK bit*/ + FMC_CTL0 |= FMC_CTL0_LK; +} + +/*! + \brief lock the FMC bank1 operation + this function can be used for GD32F30x with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_lock(void) +{ + /* set the LK bit*/ + FMC_CTL1 |= FMC_CTL1_LK; +} + +/*! + \brief erase page + \param[in] page_address: the page address to be erased. + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state; + + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > page_address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + }else{ + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL1 |= FMC_CTL1_PER; + FMC_ADDR1 = page_address; + if(FMC_OBSTAT & FMC_OBSTAT_SPC){ + FMC_ADDR0 = page_address; + } + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL1 &= ~FMC_CTL1_PER; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state; + if(FMC_BANK0_SIZE < FMC_SIZE){ + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase bank0 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start FMC bank0 erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief erase bank1 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* start FMC bank1 erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + }else{ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_END_ADDRESS > address){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + }else{ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + }else{ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWEN bit */ + FMC_CTL0 &= ~FMC_CTL0_OBWEN; +} + +/*! + \brief erase the FMC option byte + unlock the FMC_CTL0 and option byte before calling this function + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t temp_spc = FMC_NSPC; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* check the option byte security protection value */ + if(RESET != ob_spc_get()){ + temp_spc = FMC_USPC; + } + + if(FMC_READY == fmc_state){ + + /* start erase the option byte */ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + /* no security protection */ + OB_SPC = (uint16_t)temp_spc; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected + \arg OB_WPx(x=0..31): write protect specify sector + \arg OB_WP_ALL: write protect all sector + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) +{ + uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + ob_wp = (uint32_t)(~ob_wp); + temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); + temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); + temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); + temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); + + if(FMC_READY == fmc_state){ + + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + if(0xFFU != temp_wp0){ + OB_WP0 = temp_wp0; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ + OB_WP1 = temp_wp1; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ + OB_WP2 = temp_wp2; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ + OB_WP3 = temp_wp3; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection + \arg FMC_NSPC: no security protection + \arg FMC_USPC: under security protection + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + + /* start the option byte program */ + FMC_CTL0 |= FMC_CTL0_OBPG; + + OB_SPC = (uint16_t)ob_spc; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + }else{ + if(FMC_TOERR != fmc_state){ + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[in] ob_boot: specifies the option byte boot bank value + \arg OB_BOOT_B0: boot from bank0 + \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) +{ + fmc_state_enum fmc_state = FMC_READY; + uint8_t temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); + OB_USER = (uint16_t)temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program option bytes data + \param[in] address: the option bytes address to be programmed + \param[in] data: the byte to be programmed + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state){ + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state){ + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC user option byte + \param[in] none + \param[out] none + \retval the FMC user option byte values +*/ +uint8_t ob_user_get(void) +{ + /* return the FMC user option byte value */ + return (uint8_t)(FMC_OBSTAT >> 2U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> 10U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint32_t ob_write_protection_get(void) +{ + /* return the FMC write protection option byte value */ + return FMC_WP; +} + +/*! + \brief get the FMC option byte security protection + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ + spc_state = SET; + }else{ + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief check flag is set or not + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit + \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the FMC flag + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); +} + +/*! + \brief get FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); + }else{ + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); + } + + if(ret1 && ret2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) +{ + FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); +} + +/*! + \brief get the FMC bank0 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC bank1 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ + fmc_state = FMC_BUSY; + }else{ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ + fmc_state = FMC_WPERR; + }else{ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ + fmc_state = FMC_PGERR; + } + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank0 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_bank0_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank1 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do{ + /* get FMC state */ + fmc_state = fmc_bank1_state_get(); + timeout--; + }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state){ + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c new file mode 100644 index 00000000000..dcf1c5cf2d1 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c @@ -0,0 +1,120 @@ +/*! + \file gd32f30x_fwdgt.c + \brief FWDGT driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_fwdgt.h" + +/* write value to FWDGT_CTL_CMD bit field */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(FWDGT_STAT & flag){ + return SET; + } + + return RESET; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c new file mode 100644 index 00000000000..54695222635 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c @@ -0,0 +1,539 @@ +/*! + \file gd32f30x_gpio.c + \brief GPIO driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_gpio.h" + +#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ +#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ +#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ +#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ +#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ +#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ +#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph){ + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + case GPIOG: + /* reset GPIOG */ + rcu_periph_reset_enable(RCU_GPIOGRST); + rcu_periph_reset_disable(RCU_GPIOGRST); + break; + default: + break; + } +} + +/*! + \brief reset alternate function I/O(AFIO) + \param[in] none + \param[out] none + \retval none +*/ +void gpio_afio_deinit(void) +{ + rcu_periph_reset_enable(RCU_AFRST); + rcu_periph_reset_disable(RCU_AFRST); +} + +/*! + \brief GPIO parameter initialization + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] mode: gpio pin mode + \arg GPIO_MODE_AIN: analog input mode + \arg GPIO_MODE_IN_FLOATING: floating input mode + \arg GPIO_MODE_IPD: pull-down input mode + \arg GPIO_MODE_IPU: pull-up input mode + \arg GPIO_MODE_OUT_OD: GPIO output with open-drain + \arg GPIO_MODE_OUT_PP: GPIO output with push-pull + \arg GPIO_MODE_AF_OD: AFIO output with open-drain + \arg GPIO_MODE_AF_PP: AFIO output with push-pull + \param[in] speed: gpio output max speed value + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_MAX: output max speed more than 50MHz + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +#ifdef GD_MBED_USED +/* GPIO parameter initialization */ +void gpio_para_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) +#else +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) +#endif +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); + + /* GPIO speed configuration */ + if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ + /* output mode max speed */ + if(GPIO_OSPEED_MAX == (uint32_t)speed){ + temp_mode |= (uint32_t)0x03U; + /* set the corresponding SPD bit */ + GPIOx_SPD(gpio_periph) |= (uint32_t)pin ; + }else{ + /* output mode max speed:10MHz,2MHz,50MHz */ + temp_mode |= (uint32_t)speed; + } + } + + /* configure the eight low port pins with GPIO_CTL0 */ + for(i = 0U;i < 8U;i++){ + if((1U << i) & pin){ + reg = GPIO_CTL0(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if(GPIO_MODE_IPD == mode){ + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + }else{ + /* set the corresponding OCTL bit */ + if(GPIO_MODE_IPU == mode){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for(i = 8U;i < 16U;i++){ + if((1U << i) & pin){ + reg = GPIO_CTL1(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i - 8U); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if(GPIO_MODE_IPD == mode){ + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + }else{ + /* set the corresponding OCTL bit */ + if(GPIO_MODE_IPU == mode){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + +/*! + \brief set GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph,uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) +{ + if(RESET != bit_value){ + GPIO_BOP(gpio_periph) = (uint32_t)pin; + }else{ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] data: specify the value to be written to the port output data register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph,uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of gpio pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval input status of gpio all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)(GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of gpio pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) +{ + if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval output status of gpio all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief lock GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief configure GPIO pin event output + \param[in] output_port: gpio event output port + \arg GPIO_EVENT_PORT_GPIOA: event output port A + \arg GPIO_EVENT_PORT_GPIOB: event output port B + \arg GPIO_EVENT_PORT_GPIOC: event output port C + \arg GPIO_EVENT_PORT_GPIOD: event output port D + \arg GPIO_EVENT_PORT_GPIOE: event output port E + \param[in] output_pin: GPIO_EVENT_PIN_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) +{ + uint32_t reg = 0U; + reg = AFIO_EC; + + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ + reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); + + reg |= (uint32_t)((uint32_t)output_port << 0x04U); + reg |= (uint32_t)output_pin; + + AFIO_EC = reg; +} + +/*! + \brief enable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_enable(void) +{ + AFIO_EC |= AFIO_EC_EOE; +} + +/*! + \brief disable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_disable(void) +{ + AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); +} + +/*! + \brief select GPIO pin exti sources + \param[in] output_port: gpio event output port + \arg GPIO_PORT_SOURCE_GPIOA: output port source A + \arg GPIO_PORT_SOURCE_GPIOB: output port source B + \arg GPIO_PORT_SOURCE_GPIOC: output port source C + \arg GPIO_PORT_SOURCE_GPIOD: output port source D + \arg GPIO_PORT_SOURCE_GPIOE: output port source E + \arg GPIO_PORT_SOURCE_GPIOF: output port source F + \arg GPIO_PORT_SOURCE_GPIOG: output port source G + \param[in] output_pin: GPIO_PIN_SOURCE_0(x=0..15) + \param[out] none + \retval none +*/ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) +{ + uint32_t source = 0U; + source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)); + + /* select EXTI sources */ + if(GPIO_PIN_SOURCE_4 > output_pin){ + /* select EXTI0/EXTI1/EXTI2/EXTI3 */ + AFIO_EXTISS0 &= ~source; + AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + }else if(GPIO_PIN_SOURCE_8 > output_pin){ + /* select EXTI4/EXTI5/EXTI6/EXTI7 */ + AFIO_EXTISS1 &= ~source; + AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + }else if(GPIO_PIN_SOURCE_12 > output_pin){ + /* select EXTI8/EXTI9/EXTI10/EXTI11 */ + AFIO_EXTISS2 &= ~source; + AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + }else{ + /* select EXTI12/EXTI13/EXTI14/EXTI15 */ + AFIO_EXTISS3 &= ~source; + AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + } +} + +#ifdef GD32F30X_CL +/*! + \brief select ethernet MII or RMII PHY + \param[in] enet_sel: ethernet MII or RMII PHY selection + \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY + \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY + \param[out] none + \retval none +*/ +void gpio_ethernet_phy_select(uint32_t enet_sel) +{ + /* clear AFIO_PCF0_ENET_PHY_SEL bit */ + AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); + + /* select MII or RMII PHY */ + AFIO_PCF0 |= (uint32_t)enet_sel; +} +#endif /* GD32F30X_CL */ + +/*! + \brief configure GPIO pin remap + \param[in] gpio_remap: select the pin to remap + \arg GPIO_SPI0_REMAP: SPI0 remapping + \arg GPIO_I2C0_REMAP: I2C0 remapping + \arg GPIO_USART0_REMAP: USART0 remapping + \arg GPIO_USART1_REMAP: USART1 remapping + \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping + \arg GPIO_USART2_FULL_REMAP: USART2 full remapping + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping + \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping + \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping + \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping + \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping + \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping + \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping + \arg GPIO_TIMER3_REMAP: TIMER3 remapping + \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F30X_CL devices) + \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F30X_CL devices) + \arg GPIO_PD01_REMAP: PD01 remapping + \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F30X_CL devices and GD32F30X_HD devices) + \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F30X_CL devices) + \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F30X_CL devices) + \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST + \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled + \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled + \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F30X_CL devices) + \arg GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) + \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F30X_CL devices) + \arg GPIO_TIMER8_REMAP: TIMER8 remapping + \arg GPIO_TIMER9_REMAP: TIMER9 remapping + \arg GPIO_TIMER10_REMAP: TIMER10 remapping + \arg GPIO_TIMER12_REMAP: TIMER12 remapping + \arg GPIO_TIMER13_REMAP: TIMER13 remapping + \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect + \arg GPIO_CTC_REMAP0: CTC remapping(PD15) + \arg GPIO_CTC_REMAP1: CTC remapping(PF0) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue) +{ + uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; + + if(((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)){ + /* get AFIO_PCF1 regiter value */ + temp_reg = AFIO_PCF1; + }else{ + /* get AFIO_PCF0 regiter value */ + temp_reg = AFIO_PCF0; + } + + temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U; + remap1 = gpio_remap & LSB_16BIT_MASK; + + /* judge pin remap type */ + if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ + temp_reg &= PCF_SWJCFG_MASK; + AFIO_PCF0 &= PCF_SWJCFG_MASK; + }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){ + remap2 = ((uint32_t)0x03U) << temp_mask; + temp_reg &= ~remap2; + temp_reg |= ~PCF_SWJCFG_MASK; + }else{ + temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U)); + temp_reg |= ~PCF_SWJCFG_MASK; + } + + /* set pin remap value */ + if(DISABLE != newvalue){ + temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U)); + } + + if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){ + /* set AFIO_PCF1 regiter value */ + AFIO_PCF1 = temp_reg; + }else{ + /* set AFIO_PCF0 regiter value */ + AFIO_PCF0 = temp_reg; + } +} + +/*! + \brief configure the I/O compensation cell + \param[in] compensation: specifies the I/O compensation cell mode + \arg GPIO_COMPENSATION_ENABLE: I/O compensation cell is enabled + \arg GPIO_COMPENSATION_DISABLE: I/O compensation cell is disabled + \param[out] none + \retval none +*/ +void gpio_compensation_config(uint32_t compensation) +{ + uint32_t reg; + reg = AFIO_CPSCTL; + + /* reset the AFIO_CPSCTL_CPS_EN bit and set according to gpio_compensation */ + reg &= ~AFIO_CPSCTL_CPS_EN; + AFIO_CPSCTL = (reg | compensation); +} + +/*! + \brief check the I/O compensation cell is ready or not + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus gpio_compensation_flag_get(void) +{ + if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ + return SET; + }else{ + return RESET; + } +} + + + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c new file mode 100644 index 00000000000..215aea1ba79 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c @@ -0,0 +1,683 @@ +/*! + \file gd32f30x_i2c.c + \brief I2C driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_i2c.h" + +#define I2CCLK_MAX 0x7fU /*!< i2cclk max value */ +#define I2C_FLAG_MASK 0x0000FFFFU /*!< i2c flag mask */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph){ + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + and fast mode plus (up to 1MHz) + \param[in] dutycyc: duty cycle in fast mode or fast mode plus + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1,clkc,freq,risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1/1000000U); + if(freq >= I2CCLK_MAX){ + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed){ + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1/1000000U)+1U); + if(risetime >= I2CCLK_MAX){ + I2C_RT(i2c_periph) = I2CCLK_MAX; + }else{ + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1/(clkspeed*2U)); + if(clkc < 0x04U){ + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + }else if(400000U >= clkspeed){ + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); + if(I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)){ + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + }else{ + /* fast mode plus, the maximum SCL rise time is 120ns */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U); + if(I2C_DTCY_2 == dutycyc){ + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + /* enable fast mode */ + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + /* enable I2C fast mode plus */ + I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if(I2C_ACK_ENABLE == ack){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief I2C POAP position configure + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if(I2C_ACKPOS_NEXT == pos){ + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + }else{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master send slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + if(I2C_TRANSMITTER == trandirection){ + addr = addr & I2C_TRANSMITTER; + }else{ + addr = addr | I2C_RECEIVER; + } + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief dual-address mode switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dualaddr: + \arg I2C_DUADEN_DISABLE: disable dual-address mode + \arg I2C_DUADEN_ENABLE: enable dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) +{ + if(I2C_DUADEN_ENABLE == dualaddr){ + I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; + }else{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); + } +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief flag indicating DMA last transfer + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_DISSTRC); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag) +{ + uint32_t reg = 0U; + FlagStatus reval = RESET; + /* get the flag in which register */ + reg = (BIT(31) & flag); + if((BIT(31) == reg)){ + if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){ + reval = SET; + }else{ + reval = RESET; + } + }else{ + if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){ + reval = SET; + }else{ + reval = RESET; + } + } + /* return the flag status */ + return reval; +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: flag type + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag) +{ + if(I2C_FLAG_ADDSEND == flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_STAT0(i2c_periph) &= ~(flag); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] inttype: interrupt type + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype) +{ + I2C_CTL1(i2c_periph) |= (inttype); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] inttype: interrupt type + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype) +{ + I2C_CTL1(i2c_periph) &= ~(inttype); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: interrupt flag + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag) +{ + uint32_t evie, errie, bufie; + + evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE; + errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE; + /* check I2C event interrupt enable bit */ + if((intflag&0x00ffU) && evie){ + if(intflag&0x001fU){ + /* check I2C event flags except TBE and RBNE */ + if(intflag & I2C_STAT0(i2c_periph)){ + return SET; + }else{ + return RESET; + } + }else{ + /* check I2C event flags TBE and RBNE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + if(bufie){ + if(intflag & I2C_STAT0(i2c_periph)){ + return SET; + }else{ + return RESET; + } + }else{ + return RESET; + } + } + /* check I2C error interrupt enable bit */ + }else if((intflag&0xff00U) && errie){ + /* check I2C error flags */ + if(intflag & I2C_STAT0(i2c_periph)){ + return SET; + }else{ + return RESET; + } + }else{ + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] intflag: interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag) +{ + if(I2C_INT_FLAG_ADDSEND == intflag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_STAT0(i2c_periph) &= ~(intflag); + } +} + +/*! + \brief I2C PEC calculation on or off + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none +*/ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief enable or disable I2C ARP protocol in SMBus switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c new file mode 100644 index 00000000000..7d4e1d039b5 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c @@ -0,0 +1,146 @@ +/*! + \file gd32f30x_misc.c + \brief MISC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + /* use the priority group value to get the temp_pre and the temp_sub */ + if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ + temp_pre=0U; + temp_sub=0x4U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ + temp_pre=1U; + temp_sub=0x3U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ + temp_pre=2U; + temp_sub=0x2U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ + temp_pre=3U; + temp_sub=0x1U; + }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ + temp_pre=4U; + temp_sub=0x0U; + }else{ + } + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + }else{ + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c new file mode 100644 index 00000000000..bbfaeeaa5b4 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c @@ -0,0 +1,342 @@ +/*! + \file gd32f30x_pmu.c + \brief PMU driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_pmu.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL + \param[in] ldo_output: + \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode + \arg PMU_LDOVS_MID: low-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_HIGH: low-driver mode disable in deep-sleep mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief switch high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] highdr_switch: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag set */ + while(SET != pmu_flag_get(PMU_FLAG_HDRF)){ + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief enable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_LDEN; +} + +/*! + \brief disable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; +} + +/*! + \brief enable high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_HDEN; +} + +/*! + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief driver mode when use low power LDO + \param[in] mode: + \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO + \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_lowpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDLP; + PMU_CTL |= mode; +} + +/*! + \brief driver mode when use normal power LDO + \param[in] mode: + \arg PMU_NORMALDR_NORMALPWR: normal driver when use low power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_normalpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDNP; + PMU_CTL |= mode; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo + \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +{ + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd){ + __WFI(); + }else{ + __SEV(); + __WFE(); + __WFE(); + } + /* reset sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if(WFI_CMD == standbymodecmd){ + __WFI(); + }else{ + __WFE(); + } +} + +/*! + \brief clear flag bit + \param[in] flag_reset: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag_reset) +{ + switch(flag_reset){ + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} + +/*! + \brief get flag state + \param[in] flag: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag + \arg PMU_FLAG_HDRF: high-driver ready flag + \arg PMU_FLAG_HDSRF: high-driver switch ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief enable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief enable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c new file mode 100644 index 00000000000..b779253718d --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c @@ -0,0 +1,1276 @@ +/*! + \file gd32f30x_rcu.c + \brief RCU driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint16_t)0U) +#define SEL_HXTAL ((uint16_t)1U) +#define SEL_PLL ((uint16_t)2U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + rcu_osci_stab_wait(RCU_IRC8M); + + /* reset CFG0 register */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | + RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBDPSC_2); +#elif defined(GD32F30X_CL) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBFSPSC_2); +#endif /* GD32F30X_HD and GD32F30X_XD */ + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + RCU_CTL &= ~RCU_CTL_HXTALBPS; +#ifdef GD32F30X_CL + RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); +#endif /* GD32F30X_CL */ + + /* reset INT and CFG1 register */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_INT = 0x009f0000U; + RCU_CFG1 &= ~(RCU_CFG1_ADCPSC_3 | RCU_CFG1_PLLPRESEL); +#elif defined(GD32F30X_CL) + RCU_INT = 0x00ff0000U; + RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | + RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL | RCU_CFG1_ADCPSC_3 | + RCU_CFG1_PLLPRESEL | RCU_CFG1_PLL2MF_4); +#endif /* GD32F30X_HD and GD32F30X_XD */ +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF : alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_CTC: CTC clock + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF: alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_CTC: CTC clock + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC + \arg RCU_CTCRST: reset CTC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC + \arg RCU_CTCRST: reset CTC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP domain + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP domain reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_NONE: no clock selected + \arg RCU_CKOUT0SRC_CKSYS: system clock selected + \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected + \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected + \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected + \arg RCU_CKOUT0SRC_EXT1: EXT1 selected + \arg RCU_CKOUT0SRC_CKPLL2: PLL selected + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the CKOUT0SRC, set according to ckout0_src */ + reg &= ~RCU_CFG0_CKOUT0SEL; + RCU_CFG0 = (reg | ckout0_src); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL + \arg RCU_PLLSRC_HXTAL_IRC48M: HXTAL or IRC48M selected as source clock of PLL + \param[in] pll_mul: PLL clock multiplication factor + \arg RCU_PLL_MULx (XD series x = 2..63, CL series x = 2..14, 16..63, 6.5) + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + + /* PLL clock source and multiplication factor configuration */ + reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + reg |= (pll_src | pll_mul); + + RCU_CFG0 = reg; +} + +/*! + \brief configure the PLL clock source preselection + \param[in] pll_presel: PLL clock source preselection + \arg RCU_PLLPRESRC_HXTAL: HXTAL selected as PLL source clock + \arg RCU_PLLPRESRC_IRC48M: CK_PLL selected as PREDV0 input source clock + \param[out] none + \retval none +*/ +void rcu_pllpresel_config(uint32_t pll_presel) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + + /* PLL clock source preselection */ + reg &= ~RCU_CFG1_PLLPRESEL; + reg |= pll_presel; + + RCU_CFG1 = reg; +} + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +/*! + \brief configure the PREDV0 division factor + \param[in] predv0_div: PREDV0 division factor + \arg RCU_PREDV0_DIVx, x = 1,2 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + /* reset PREDV0 bit */ + reg &= ~RCU_CFG0_PREDV0; + if(RCU_PREDV0_DIV2 == predv0_div){ + /* set the PREDV0 bit */ + reg |= RCU_CFG0_PREDV0; + } + + RCU_CFG0 = reg; +} +#elif defined(GD32F30X_CL) +/*! + \brief configure the PREDV0 division factor and clock source + \param[in] predv0_source: PREDV0 input clock source selection + \arg RCU_PREDV0SRC_HXTAL_IRC48M: HXTAL or IRC48M selected as PREDV0 input source clock + \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock + \param[in] predv0_div: PREDV0 division factor + \arg RCU_PREDV0_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset PREDV0SEL and PREDV0 bits */ + reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); + /* set the PREDV0SEL and PREDV0 division factor */ + reg |= (predv0_source | predv0_div); + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PREDV1 division factor + \param[in] predv1_div: PREDV1 division factor + \arg RCU_PREDV1_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv1_config(uint32_t predv1_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset the PREDV1 bits */ + reg &= ~RCU_CFG1_PREDV1; + /* set the PREDV1 division factor */ + reg |= predv1_div; + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PLL1 clock + \param[in] pll_mul: PLL clock multiplication factor + \arg RCU_PLL1_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll1_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL1MF; + RCU_CFG1 |= pll_mul; +} + +/*! + \brief configure the PLL2 clock + \param[in] pll_mul: PLL clock multiplication factor + \arg RCU_PLL2_MULx (x = 8..16, 18..32, 40) + \param[out] none + \retval none +*/ +void rcu_pll2_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL2MF; + RCU_CFG1 |= pll_mul; +} +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/*! + \brief configure the ADC prescaler factor + \param[in] adc_psc: ADC prescaler factor + \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 + \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 + \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 + \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 + \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 + \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 + \arg RCU_CKADC_CKAHB_DIV5: ADC prescaler select CK_AHB/5 + \arg RCU_CKADC_CKAHB_DIV6: ADC prescaler select CK_AHB/6 + \arg RCU_CKADC_CKAHB_DIV10: ADC prescaler select CK_AHB/10 + \arg RCU_CKADC_CKAHB_DIV20: ADC prescaler select CK_AHB/20 + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(uint32_t adc_psc) +{ + uint32_t reg0,reg1; + + /* reset the ADCPSC bits */ + reg0 = RCU_CFG0; + reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); + reg1 = RCU_CFG1; + reg1 &= ~RCU_CFG1_ADCPSC_3; + + /* set the ADC prescaler factor */ + switch(adc_psc){ + case RCU_CKADC_CKAPB2_DIV2: + case RCU_CKADC_CKAPB2_DIV4: + case RCU_CKADC_CKAPB2_DIV6: + case RCU_CKADC_CKAPB2_DIV8: + reg0 |= (adc_psc << 14); + break; + + case RCU_CKADC_CKAPB2_DIV12: + case RCU_CKADC_CKAPB2_DIV16: + adc_psc &= ~BIT(2); + reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); + break; + + case RCU_CKADC_CKAHB_DIV5: + case RCU_CKADC_CKAHB_DIV6: + case RCU_CKADC_CKAHB_DIV10: + case RCU_CKADC_CKAHB_DIV20: + adc_psc &= ~BITS(2,3); + reg0 |= (adc_psc << 14); + reg1 |= RCU_CFG1_ADCPSC_3; + break; + + default: + break; + } + + /* set the register */ + RCU_CFG0 = reg0; + RCU_CFG1 = reg1; +} + +/*! + \brief configure the USBD/USBFS prescaler factor + \param[in] adc_div: USB prescaler factor + \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 + \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 + \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 + \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 + \arg RCU_CKUSB_CKPLL_DIV3: USBD/USBFS prescaler select CK_PLL/3 + \arg RCU_CKUSB_CKPLL_DIV3_5: USBD/USBFS prescaler select CK_PLL/3.5 + \arg RCU_CKUSB_CKPLL_DIV4: USBD/USBFS prescaler select CK_PLL/4 + \param[out] none + \retval none +*/ +void rcu_usb_clock_config(uint32_t usb_psc) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* configure the USBD/USBFS prescaler factor */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + reg &= ~RCU_CFG0_USBDPSC; +#elif defined(GD32F30X_CL) + reg &= ~RCU_CFG0_USBFSPSC; +#endif /* GD32F30X_HD and GD32F30X_XD */ + + RCU_CFG0 = (reg | usb_psc); +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +#ifdef GD32F30X_CL +/*! + \brief configure the I2S1 clock source selection + \param[in] i2s_clock_source: I2S1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock + \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock + \param[out] none + \retval none +*/ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S1SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S1SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} + +/*! + \brief configure the I2S2 clock source selection + \param[in] i2s_clock_source: I2S2 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock + \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock + \param[out] none + \retval none +*/ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S2SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S2SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} +#endif /* GD32F30X_CL */ + +/*! + \brief configure the CK48M clock source selection + \param[in] ck48m_clock_source: CK48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CK48MSRC_CKPLL: CK_PLL selected as CK48M source clock + \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock + \param[out] none + \retval none +*/ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the CK48MSEL bit and set according to ck48m_clock_source */ + reg &= ~RCU_ADDCTL_CK48MSEL; + RCU_ADDCTL = (reg | ck48m_clock_source); +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) + \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTAL_LOWDRI: lower driving capability + \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability + \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability + \arg RCU_LXTAL_HIGHDRI: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + uint32_t reg; + + reg = RCU_BDCTL; + + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + reg &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL = (reg | lxtal_dricap); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch(osci){ + /* wait HXTAL stable */ + case RCU_HXTAL: + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC48M stable */ + case RCU_IRC48M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + reval = SUCCESS; + } + break; + +#ifdef GD32F30X_CL + /* wait PLL1 stable */ + case RCU_PLL1_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ + reval = SUCCESS; + } + break; + /* wait PLL2 stable */ + case RCU_PLL2_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ + reval = SUCCESS; + } + break; +#endif /* GD32F30X_CL */ + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F30X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F30X_CL */ + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch(osci){ + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F30X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F30X_CL */ + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + reg &= ~RCU_CTL_IRC8MADJ; + RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V + \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src, idx, clk_exp; +#ifdef GD32F30X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F30X_CL */ + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if(RCU_PLLSRC_HXTAL_IRC48M == pllsel) { + /* PLL clock source is HXTAL or IRC48M */ + pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); + + if(RCU_PLLPRESRC_HXTAL == pllpresel){ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + }else{ + /* PLL clock source is IRC48 */ + ck_src = IRC48M_VALUE; + } + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE/2U; + } +#elif defined(GD32F30X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src/predv1)*pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F30X_HD and GD32F30X_XD */ + }else{ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE/2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){ + pllmf |= 0x20U; + } + if(pllmf < 15U){ + pllmf += 2U; + }else if((pllmf >= 15U) && (pllmf <= 62U)){ + pllmf += 1U; + }else{ + pllmf = 63U; + } + cksys_freq = ck_src*pllmf; + #ifdef GD32F30X_CL + if(15U == pllmf){ + cksys_freq = ck_src*6U + ck_src/2U; + } + #endif /* GD32F30X_CL */ + + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock){ + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c new file mode 100644 index 00000000000..c4e1d9e4fcc --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c @@ -0,0 +1,203 @@ +/*! + \file gd32f30x_rtc.c + \brief RTC driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_rtc.h" + +/*! + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + RTC_INTEN |= interrupt; +} + +/*! + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disbale + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + RTC_INTEN &= ~interrupt; +} + +/*! + \brief enter RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_enter(void) +{ + RTC_CTL |= RTC_CTL_CMF; +} + +/*! + \brief exit RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_exit(void) +{ + RTC_CTL &= ~RTC_CTL_CMF; +} + +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while (RESET == (RTC_CTL & RTC_CTL_LWOFF)){ + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while (RESET == (RTC_CTL & RTC_CTL_RSYNF)){ + } +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + temp = RTC_CNTL; + temp |= (RTC_CNTH << 16); + return temp; +} + +/*! + \brief set RTC counter value + \param[in] cnt: RTC counter value + \param[out] none + \retval none +*/ +void rtc_counter_set(uint32_t cnt) +{ + rtc_configuration_mode_enter(); + /* set the RTC counter high bits */ + RTC_CNTH = cnt >> 16; + /* set the RTC counter low bits */ + RTC_CNTL = (cnt & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC prescaler value + \param[in] psc: RTC prescaler value + \param[out] none + \retval none +*/ +void rtc_prescaler_set(uint32_t psc) +{ + rtc_configuration_mode_enter(); + /* set the RTC prescaler high bits */ + RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16; + /* set the RTC prescaler low bits */ + RTC_PSCL = (psc & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC alarm value + \param[in] alarm: RTC alarm value + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint32_t alarm) +{ + rtc_configuration_mode_enter(); + /* set the alarm high bits */ + RTC_ALRMH = alarm >> 16; + /* set the alarm low bits */ + RTC_ALRML = (alarm & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief get RTC divider value + \param[in] none + \param[out] none + \retval RTC divider value +*/ +uint32_t rtc_divider_get(void) +{ + uint32_t temp = 0x00U; + temp = (RTC_DIVH & RTC_DIVH_DIV) << 16; + temp |= RTC_DIVL; + return temp; +} + +/*! + \brief get RTC flag status + \param[in] flag: specify which flag status to get + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + if(RESET != (RTC_CTL & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear RTC flag status + \param[in] flag: specify which flag status to clear + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + /* clear RTC flag */ + RTC_CTL &= ~flag; +} + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c new file mode 100644 index 00000000000..67ab84009d8 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c @@ -0,0 +1,772 @@ +/*! + \file gd32f30x_sdio.c + \brief SDIO driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_sdio.h" + +#define DEFAULT_RESET_VALUE 0x00000000U + +/*! + \brief deinitialize the SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_deinit(void) +{ + SDIO_PWRCTL = DEFAULT_RESET_VALUE; + SDIO_CLKCTL = DEFAULT_RESET_VALUE; + SDIO_CMDAGMT = DEFAULT_RESET_VALUE; + SDIO_CMDCTL = DEFAULT_RESET_VALUE; + SDIO_DATATO = DEFAULT_RESET_VALUE; + SDIO_DATALEN = DEFAULT_RESET_VALUE; + SDIO_DATACTL = DEFAULT_RESET_VALUE; + SDIO_INTC = DEFAULT_RESET_VALUE; + SDIO_INTEN = DEFAULT_RESET_VALUE; +} + +/*! + \brief configure the SDIO clock + \param[in] clock_edge: SDIO_CLK clock edge + \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK + \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK + \param[in] clock_bypass: clock bypass + \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass + \arg SDIO_CLOCKBYPASS_DISABLE: no bypass + \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle + \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on + \param[in] clock_division: clock division, less than 512 + \param[out] none + \retval none +*/ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) +{ + uint32_t clock_config = 0U; + clock_config = SDIO_CLKCTL; + /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ + clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); + /* if the clock division is greater or equal to 256, set the DIV[8] */ + if(clock_division >= 256U){ + clock_config |= SDIO_CLKCTL_DIV8; + clock_division -= 256U; + } + /* configure the SDIO_CLKCTL according to the parameters */ + clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); + SDIO_CLKCTL = clock_config; +} + +/*! + \brief enable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief disable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief set different SDIO card bus mode + \param[in] bus_mode: SDIO card bus mode + \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode + \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode + \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode + \param[out] none + \retval none +*/ +void sdio_bus_mode_set(uint32_t bus_mode) +{ + /* reset the SDIO card bus mode bits and set according to bus_mode */ + SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; + SDIO_CLKCTL |= bus_mode; +} + +/*! + \brief set the SDIO power state + \param[in] power_state: SDIO power state + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off + \param[out] none + \retval none +*/ +void sdio_power_state_set(uint32_t power_state) +{ + SDIO_PWRCTL = power_state; +} + +/*! + \brief get the SDIO power state + \param[in] none + \param[out] none + \retval SDIO power state + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off +*/ +uint32_t sdio_power_state_get(void) +{ + return SDIO_PWRCTL; +} + +/*! + \brief enable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; +} + +/*! + \brief disable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; +} + +/*! + \brief configure the command and response + \param[in] cmd_index: command index, refer to the related specifications + \param[in] cmd_argument: command argument, refer to the related specifications + \param[in] response_type: response type + \arg SDIO_RESPONSETYPE_NO: no response + \arg SDIO_RESPONSETYPE_SHORT: short response + \arg SDIO_RESPONSETYPE_LONG: long response + \param[out] none + \retval none +*/ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) +{ + uint32_t cmd_config = 0U; + /* reset the command index, command argument and response type */ + SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; + SDIO_CMDAGMT = cmd_argument; + cmd_config = SDIO_CMDCTL; + cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); + /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ + cmd_config |= (cmd_index | response_type); + SDIO_CMDCTL = cmd_config; +} + +/*! + \brief set the command state machine wait type + \param[in] wait_type: wait type + \arg SDIO_WAITTYPE_NO: not wait interrupt + \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt + \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer + \param[out] none + \retval none +*/ +void sdio_wait_type_set(uint32_t wait_type) +{ + /* reset INTWAIT and WAITDEND */ + SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); + /* set the wait type according to wait_type */ + SDIO_CMDCTL |= wait_type; +} + +/*! + \brief enable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; +} + +/*! + \brief disable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; +} + +/*! + \brief get the last response command index + \param[in] none + \param[out] none + \retval last response command index +*/ +uint8_t sdio_command_index_get(void) +{ + return (uint8_t)SDIO_RSPCMDIDX; +} + +/*! + \brief get the response for the last received command + \param[in] responsex: SDIO response + \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] + \arg SDIO_RESPONSE1: card response[95:64] + \arg SDIO_RESPONSE2: card response[63:32] + \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 + \param[out] none + \retval response for the last received command +*/ +uint32_t sdio_response_get(uint32_t responsex) +{ + uint32_t resp_content = 0U; + switch(responsex){ + case SDIO_RESPONSE0: + resp_content = SDIO_RESP0; + break; + case SDIO_RESPONSE1: + resp_content = SDIO_RESP1; + break; + case SDIO_RESPONSE2: + resp_content = SDIO_RESP2; + break; + case SDIO_RESPONSE3: + resp_content = SDIO_RESP3; + break; + default: + break; + } + return resp_content; +} + +/*! + \brief configure the data timeout, data length and data block size + \param[in] data_timeout: data timeout period in card bus clock periods + \param[in] data_length: number of data bytes to be transferred + \param[in] data_blocksize: size of data block for block transfer + \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte + \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes + \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes + \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes + \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes + \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes + \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes + \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes + \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes + \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes + \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes + \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes + \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes + \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes + \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes + \param[out] none + \retval none +*/ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) +{ + /* reset data timeout, data length and data block size */ + SDIO_DATATO &= ~SDIO_DATATO_DATATO; + SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; + SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; + /* configure the related parameters of data */ + SDIO_DATATO = data_timeout; + SDIO_DATALEN = data_length; + SDIO_DATACTL |= data_blocksize; +} + +/*! + \brief configure the data transfer mode and direction + \param[in] transfer_mode: mode of data transfer + \arg SDIO_TRANSMODE_BLOCK: block transfer + \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer + \param[in] transfer_direction: data transfer direction, read or write + \arg SDIO_TRANSDIRECTION_TOCARD: write data to card + \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card + \param[out] none + \retval none +*/ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) +{ + uint32_t data_trans = 0U; + /* reset the data transfer mode, transfer direction and set according to the parameters */ + data_trans = SDIO_DATACTL; + data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); + data_trans |= (transfer_mode | transfer_direction); + SDIO_DATACTL = data_trans; +} + +/*! + \brief enable the DSM(data state machine) for data transfer + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DATAEN; +} + +/*! + \brief disable the DSM(data state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; +} + +/*! + \brief write data(one word) to the transmit FIFO + \param[in] data: 32-bit data write to card + \param[out] none + \retval none +*/ +void sdio_data_write(uint32_t data) +{ + SDIO_FIFO = data; +} + +/*! + \brief read data(one word) from the receive FIFO + \param[in] none + \param[out] none + \retval received data +*/ +uint32_t sdio_data_read(void) +{ + return SDIO_FIFO; +} + +/*! + \brief get the number of remaining data bytes to be transferred to card + \param[in] none + \param[out] none + \retval number of remaining data bytes to be transferred +*/ +uint32_t sdio_data_counter_get(void) +{ + return SDIO_DATACNT; +} + +/*! + \brief get the number of words remaining to be written or read from FIFO + \param[in] none + \param[out] none + \retval remaining number of words +*/ +uint32_t sdio_fifo_counter_get(void) +{ + return SDIO_FIFOCNT; +} + +/*! + \brief enable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DMAEN; +} + +/*! + \brief disable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; +} + +/*! + \brief get the flags state of SDIO + \param[in] flag: flags state of SDIO + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_CMDRUN: command transmission in progress flag + \arg SDIO_FLAG_TXRUN: data transmission in progress flag + \arg SDIO_FLAG_RXRUN: data reception in progress flag + \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO + \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO + \arg SDIO_FLAG_TFF: transmit FIFO is full flag + \arg SDIO_FLAG_RFF: receive FIFO is full flag + \arg SDIO_FLAG_TFE: transmit FIFO is empty flag + \arg SDIO_FLAG_RFE: receive FIFO is empty flag + \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag + \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_flag_get(uint32_t flag) +{ + FlagStatus temp_flag = RESET; + if(RESET != (SDIO_STAT & flag)){ + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the pending flags of SDIO + \param[in] flag: flags state of SDIO + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_flag_clear(uint32_t flag) +{ + SDIO_INTC = flag; +} + +/*! + \brief enable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_enable(uint32_t int_flag) +{ + SDIO_INTEN |= int_flag; +} + +/*! + \brief disable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_disable(uint32_t int_flag) +{ + SDIO_INTEN &= ~int_flag; +} + +/*! + \brief get the interrupt flags state of SDIO + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state = 0U; + state = SDIO_STAT; + if(state & int_flag){ + state = SDIO_INTEN; + /* check whether the corresponding bit in SDIO_INTEN is set or not */ + if(state & int_flag){ + return SET; + } + } + return RESET; +} + +/*! + \brief clear the interrupt pending flags of SDIO + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_interrupt_flag_clear(uint32_t int_flag) +{ + SDIO_INTC = int_flag; +} + +/*! + \brief enable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWEN; +} + +/*! + \brief disable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; +} + +/*! + \brief enable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; +} + +/*! + \brief disable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; +} + +/*! + \brief set the read wait type(SD I/O only) + \param[in] readwait_type: SD I/O read wait type + \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK + \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] + \param[out] none + \retval none +*/ +void sdio_readwait_type_set(uint32_t readwait_type) +{ + if(SDIO_READWAITTYPE_CLK == readwait_type){ + SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; + }else{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; + } +} + +/*! + \brief enable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_IOEN; +} + +/*! + \brief disable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; +} + +/*! + \brief enable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief disable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief enable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; +} + +/*! + \brief disable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; +} + +/*! + \brief enable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_enable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; +} + +/*! + \brief disable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_disable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; +} + +/*! + \brief enable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; +} + +/*! + \brief disable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c new file mode 100644 index 00000000000..709b07a83fe --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c @@ -0,0 +1,797 @@ +/*! + \file gd32f30x_spi.c + \brief SPI driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#include "gd32f30x_spi.h" + +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ +#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ +#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ +#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph){ + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 and I2S1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2 and I2S2 */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + default : + break; + } +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ + #ifdef GD_MBED_USED +/* initialize SPI parameter */ +void spi_para_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +#else +void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +#endif +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPIx(x=1,2) + \param[in] audiosample: I2S audio sample rate + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + +#ifdef GD32F30X_CL + uint32_t pll2mf_4 = 0U; +#endif /* GD32F30X_CL */ + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = 0x0002U; + +#ifdef GD32F30X_CL + /* get the I2S clock source */ + if(((uint32_t)spi_periph) == SPI1){ + /* I2S1 clock source selection */ + clks = I2S1_CLOCK_SEL; + }else{ + /* I2S2 clock source selection */ + clks = I2S2_CLOCK_SEL; + } + + if(0U != (RCU_CFG1 & clks)){ + /* get RCU PLL2 clock multiplication factor */ + clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U); + + pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4; + + if( 0U == pll2mf_4){ + if((clks > 5U) && (clks < 15U)){ + /* multiplier is between 8 and 16 */ + clks += 2U; + }else{ + if(15U == clks){ + /* multiplier is 20 */ + clks = 20U; + } + } + }else{ + if(clks < 15U){ + /* multiplier is between 18 and 32 */ + clks += 18U; + }else{ + if(15U == clks){ + /* multiplier is 40 */ + clks = 40U; + } + } + } + + /* get the PREDV1 value */ + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U); + /* calculate i2sclock based on PLL2 and PREDV1 */ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + }else{ + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + } +#else + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); +#endif /* GD32F30X_CL */ + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout){ + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + }else{ + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ + clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); + }else{ + clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] mode: I2S operation mode + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg= 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + }else{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma){ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + }else{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] frame_format: SPI frame size + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* confige SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] transfer_direction: SPI transfer direction + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + }else{ + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt flag status + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if(reg1 && reg2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] flag: SPI/I2S flag status + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error interrupt flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(SPI_STAT(spi_periph) & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief set CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc: SPI crc value + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) +{ + if(SPI_CRC_TX == crc){ + return ((uint16_t)(SPI_TCRC(spi_periph))); + }else{ + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + + /*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ + void qspi_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c new file mode 100644 index 00000000000..0666be7311c --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c @@ -0,0 +1,1872 @@ +/*! + \file gd32f30x_timer.c + \brief TIMER driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#include "gd32f30x_timer.h" + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph){ + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; +#ifndef GD32F30X_HD + case TIMER8: + /* reset TIMER8 */ + rcu_periph_reset_enable(RCU_TIMER8RST); + rcu_periph_reset_disable(RCU_TIMER8RST); + break; + case TIMER9: + /* reset TIMER9 */ + rcu_periph_reset_enable(RCU_TIMER9RST); + rcu_periph_reset_disable(RCU_TIMER9RST); + break; + case TIMER10: + /* reset TIMER10 */ + rcu_periph_reset_enable(RCU_TIMER10RST); + rcu_periph_reset_disable(RCU_TIMER10RST); + break; + case TIMER11: + /* reset TIMER11 */ + rcu_periph_reset_enable(RCU_TIMER11RST); + rcu_periph_reset_disable(RCU_TIMER11RST); + break; + case TIMER12: + /* reset TIMER12 */ + rcu_periph_reset_enable(RCU_TIMER12RST); + rcu_periph_reset_disable(RCU_TIMER12RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; +#endif /* GD32F30X_HD */ + default: + break; + } +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] aligned: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph,uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..8,11) + \param[in] spmode: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph,uint8_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + }else{ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] update: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph,uint8_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update){ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + }else if(update == TIMER_UPDATE_SRC_GLOBAL){ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + }else{ + } +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source enable + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t interrupt) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph , uint32_t flag) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16) + \param[in] dma: timer DMA source enable + \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph,uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: timer DMA source enable + \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph,uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] dma_request: channel DMA request source selection + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + }else{ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: please refer to the following parameters + \param[in] dma_baseaddr: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) + \param[in] dma_lenth: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph,uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph,timer_break_parameter_struct* breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| + ((uint32_t)(breakpara->ideloffstate))| + ((uint32_t)(breakpara->deadtime))| + ((uint32_t)(breakpara->breakpolarity))| + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode))| + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + }else{ + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief channel capture/compare control shadow register enable + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue) +{ + if(ENABLE == newvalue){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + }else{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] ccuctl: channel control shadow register update control + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl){ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + }else{ + } +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct* ocpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); + + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocmode: channel output compare mode + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] pulse: channel output pulse value + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse) +{ + switch(channel){ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocshadow: channel output shadow state + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocfast: channel output fast function + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \arg TIMER_CH_3: TIMER channel3 + \param[in] occlear: channel output clear function + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocpolarity: channel output polarity + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7)) + \param[in] ocnpolarity: channel complementary output polarity + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] state: TIMER channel enable state + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7)) + \param[in] ocnstate: TIMER channel complementary output enable state + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct* icpara) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] prescaler: channel input capture prescaler value + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler) +{ + switch(channel){ + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel){ + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct* icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + icpolarity = TIMER_IC_POLARITY_FALLING; + }else{ + icpolarity = TIMER_IC_POLARITY_RISING; + } + + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + icselection = TIMER_IC_SELECTION_INDIRECTTI; + }else{ + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel){ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + }else{ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] hallmode: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph,uint8_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + }else{ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output + \arg TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] slavemode: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable + \arg TIMER_ENCODER_MODE0: encoder mode 0 + \arg TIMER_ENCODER_MODE1: encoder mode 1 + \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_SLAVE_MODE_RESTART: restart mode + \arg TIMER_SLAVE_MODE_PAUSE: pause mode + \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] masterslave: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph,uint8_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + }else{ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler, + uint32_t expolarity,uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter<< 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] decomode: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode, + uint16_t ic0polarity,uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity<< 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph,intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extrigger: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] expolarity: + \arg TIMER_IC_POLARITY_RISING: active low or falling edge active + \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger, + uint16_t expolarity,uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter<< 8U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + }else{ + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph,extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extprescaler: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler, + uint32_t expolarity,uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler, + uint32_t expolarity,uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) + \param[in] ccsel: + \arg TIMER_CCSEL_DISABLE: no effect + \arg TIMER_CCSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CCSEL_ENABLE == ccsel){ + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + }else if(TIMER_CCSEL_DISABLE == ccsel){ + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + }else{ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] outsel: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel){ + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + }else if(TIMER_OUTSEL_DISABLE == outsel){ + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + }else{ + } +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c new file mode 100644 index 00000000000..b96fa05aed7 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c @@ -0,0 +1,874 @@ +/*! + \file gd32f30x_usart.c + \brief USART driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.2, firmware for GD32F30x +*/ + +#include "gd32f30x_usart.h" + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph){ + case USART0: + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case UART3: + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; + switch(usart_periph){ + /* get clock frequency */ + case USART0: + uclk=rcu_clock_freq_get(CK_APB2); + break; + case USART1: + uclk=rcu_clock_freq_get(CK_APB1); + break; + case USART2: + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART3: + uclk=rcu_clock_freq_get(CK_APB1); + break; + case UART4: + uclk=rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk+baudval/2U)/baudval; + intdiv = udiv & 0xfff0U; + fradiv = udiv & 0xfU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] paritycfg: configure USART parity + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wlen: USART word length configure + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] stblen: USART stop bit configure + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] txconfig: enable or disable USART transmitter + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] rxconfig: enable or disable USART receiver + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] msbf: LSB/MSB + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); + USART_CTL3(usart_periph) |= msbf; +} + +/*! + \brief configure USART inversion + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] invertpara: refer to enum USART_INVERT_CONFIG + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + /* inverted or not the specified siginal */ + switch(invertpara){ + case USART_DINV_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_DINV; + break; + case USART_TXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_TINV; + break; + case USART_RXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_RINV; + break; + case USART_DINV_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); + break; + case USART_TXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); + break; + case USART_RXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); + break; + default: + break; + } +} + +/*! + \brief enable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) |= USART_CTL3_RTEN; +} + +/*! + \brief disable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); +} + +/*! + \brief set the receiver timeout threshold of USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] rtimeout: 0-0xFFFFFF + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief receiver in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief receiver in active mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wmethod: two methods be used to enter or exit the mute mode + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] lblen: lin break frame length + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] clen: CK length + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] guat: guard time value + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<<8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] scrtnum: smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<1)); +} + +/*! + \brief configure block length in Smartcard T=1 reception + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] bl: block length + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<24)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] psc: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] irlp: IrDA low-power or normal + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable RTS + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable CTS + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for reception + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for transmission + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one among these parameters can be selected + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +#ifndef GD_MBED_USED +/*! + \brief clear flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one among these parameters can be selected + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} +#else +/*! + \brief clear flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one among these parameters can be selected + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + if((BIT(USART_BIT_POS(flag)) & 0x1f) != 0U){ + /* read USART_STAT0 and then read USART_DATA to clear error flag */ + USART_STAT0(usart_periph); + USART_DATA(usart_periph); + }else if((BIT(USART_BIT_POS(flag)) & 0x1b60) != 0U){ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); + } +} +#endif + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one among these parameters can be selected + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one among these parameters can be selected + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag + \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag + \param[out] none + \retval FlagStatus +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART interrupt flag + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) +{ + USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c new file mode 100644 index 00000000000..cdfc4df6863 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c @@ -0,0 +1,122 @@ +/*! + \file gd32f30x_wwdgt.c + \brief WWDGT driver +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#include "gd32f30x_wwdgt.h" + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + uint32_t reg = 0U; + + reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + reg |= CTL_CNT(counter_value); + + WWDGT_CTL = reg; +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + uint32_t reg_cfg = 0U, reg_ctl = 0U; + + /* clear WIN and PSC bits, clear CNT bit */ + reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); + reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); + + /* configure WIN and PSC bits, configure CNT bit */ + reg_cfg |= CFG_WIN(window); + reg_cfg |= prescaler; + reg_ctl |= CTL_CNT(counter); + + WWDGT_CTL = reg_ctl; + WWDGT_CFG = reg_cfg; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(WWDGT_STAT & WWDGT_STAT_EWIF){ + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (~WWDGT_STAT_EWIF); +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/PeripheralPins.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/PeripheralPins.h new file mode 100644 index 00000000000..80feb50f7bd --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/PeripheralPins.h @@ -0,0 +1,72 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +extern const int GD_GPIO_REMAP[]; +extern const int GD_GPIO_MODE[]; +extern const int GD_GPIO_SPEED[]; + +/* ADC */ +#ifdef DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +/* DAC */ +#ifdef DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +/* I2C */ +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +/* PWM */ +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM[]; +#endif + +/* SERIAL */ +#ifdef DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +#ifdef DEVICE_SERIAL_FC +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif +#endif + +/* SPI */ +#ifdef DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +/* CAN */ +#ifdef DEVICE_CAN +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; +#endif + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/PortNames.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/PortNames.h new file mode 100644 index 00000000000..7b4bc80b35b --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/PortNames.h @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PORTA = 0, + PORTB = 1, + PORTC = 2, + PORTD = 3, + PORTE = 4, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralNames.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralNames.h new file mode 100644 index 00000000000..eb28838a95a --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralNames.h @@ -0,0 +1,83 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = (int)ADC0, + ADC_1 = (int)ADC1 +} ADCName; + +typedef enum { + DAC_0 = (int)DAC0, + DAC_1 = (int)DAC1, +} DACName; + +typedef enum { + UART_0 = (int)USART0, + UART_1 = (int)USART1, + UART_2 = (int)USART2, + UART_3 = (int)UART3, + UART_4 = (int)UART4 +} UARTName; + +#define STDIO_UART_TX PORTA_9 +#define STDIO_UART_RX PORTA_10 +#define STDIO_UART UART_0 + +typedef enum { + SPI_0 = (int)SPI0, + SPI_1 = (int)SPI1, + SPI_2 = (int)SPI2 +} SPIName; + +typedef enum { + I2C_0 = (int)I2C0, + I2C_1 = (int)I2C1 +} I2CName; + +typedef enum { + PWM_0 = (int)TIMER0, + PWM_1 = (int)TIMER1, + PWM_2 = (int)TIMER2, + PWM_3 = (int)TIMER3, + PWM_4 = (int)TIMER4, + PWM_5 = (int)TIMER7, + PWM_6 = (int)TIMER8, + PWM_7 = (int)TIMER9, + PWM_8 = (int)TIMER10, + PWM_9 = (int)TIMER11, + PWM_10 = (int)TIMER12, + PWM_11 = (int)TIMER13 +} PWMName; + +typedef enum { + CAN_0 = (int)CAN0, + CAN_1 = (int)CAN1 +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralPins.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralPins.c new file mode 100644 index 00000000000..81ea0e488ec --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralPins.c @@ -0,0 +1,356 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + + +/* void pin_function(PinName pin, int function); + configure the speed, mode,and remap function of pins + the parameter function contains the configuration information,show as below + bit 0:2 gpio mode + bit 3:8 remap + bit 9:10 gpio speed + bit 11:15 adc /timer channel +*/ +const int GD_GPIO_REMAP[] = { + 0x00000000, + GPIO_SPI0_REMAP, /* 1 */ + GPIO_I2C0_REMAP, /* 2 */ + GPIO_USART0_REMAP, /* 3 */ + GPIO_USART1_REMAP, /* 4 */ + GPIO_USART2_PARTIAL_REMAP, /* 5 */ + GPIO_USART2_FULL_REMAP, /* 6 */ + GPIO_TIMER0_PARTIAL_REMAP, /* 7 */ + GPIO_TIMER0_FULL_REMAP, /* 8 */ + GPIO_TIMER1_PARTIAL_REMAP0, /* 9 */ + GPIO_TIMER1_PARTIAL_REMAP1, /* 10 */ + GPIO_TIMER1_FULL_REMAP, /* 11 */ + GPIO_TIMER2_PARTIAL_REMAP, /* 12 */ + GPIO_TIMER2_FULL_REMAP, /* 13 */ + GPIO_TIMER3_REMAP, /* 14 */ + GPIO_PD01_REMAP, /* 15 */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + GPIO_CAN_PARTIAL_REMAP, /* 16 */ + GPIO_CAN_FULL_REMAP, /* 17 */ +#else + 0, + 0, +#endif +#if (defined(GD32F30X_CL) || defined(GD32F30X_HD)) + GPIO_TIMER4CH3_IREMAP, /* 18 */ +#else + 0, +#endif + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + GPIO_ADC0_ETRGINS_REMAP, /* 19 */ + GPIO_ADC0_ETRGREG_REMAP, /* 20 */ + GPIO_ADC1_ETRGINS_REMAP, /* 21 */ + GPIO_ADC1_ETRGREG_REMAP, /* 22 */ +#else + 0, + 0, + 0, + 0, +#endif + + GPIO_SWJ_NONJTRST_REMAP, /* 23 */ + GPIO_SWJ_SWDPENABLE_REMAP, /* 24 */ + GPIO_SWJ_DISABLE_REMAP, /* 25 */ + +#if (defined(GD32F30X_CL)) + GPIO_CAN0_PARTIAL_REMAP, /* 26 */ + GPIO_CAN0_FULL_REMAP, /* 27 */ + GPIO_ENET_REMAP, /* 28 */ + GPIO_CAN1_REMAP, /* 29 */ + GPIO_SPI2_REMAP, /* 30 */ + GPIO_TIMER1ITR0_REMAP, /* 31 */ + GPIO_PTP_PPS_REMAP, /* 32 */ +#else + 0, + 0, + 0, + 0, + 0, + 0, + 0, +#endif + + GPIO_TIMER8_REMAP, /* 33 */ + GPIO_TIMER9_REMAP, /* 34 */ + GPIO_TIMER10_REMAP, /* 35 */ + GPIO_TIMER12_REMAP, /* 36 */ + GPIO_TIMER13_REMAP, /* 37 */ + GPIO_EXMC_NADV_REMAP, /* 38 */ + GPIO_CTC_REMAP0, /* 39 */ + GPIO_CTC_REMAP1, /* 40 */ +#if (defined(GD32F30X_CL)) + GPIO_ENET_PHY_MII, /* 41 */ + GPIO_ENET_PHY_RMII, /* 42 */ +#else + 0, + 0, +#endif +}; + +/* GPIO MODE */ +const int GD_GPIO_MODE[] = { + GPIO_MODE_AIN, /* 0 */ + GPIO_MODE_IN_FLOATING, /* 1 */ + GPIO_MODE_IPD, /* 2 */ + GPIO_MODE_IPU, /* 3 */ + GPIO_MODE_OUT_OD, /* 4 */ + GPIO_MODE_OUT_PP, /* 5 */ + GPIO_MODE_AF_OD, /* 6 */ + GPIO_MODE_AF_PP, /* 7 */ +}; + +/* GPIO SPEED */ +const int GD_GPIO_SPEED[] = { + GPIO_OSPEED_50MHZ, /* 0 */ + GPIO_OSPEED_10MHZ, /* 1 */ + GPIO_OSPEED_2MHZ, /* 2 */ +}; + +/* ADC PinMap */ +const PinMap PinMap_ADC[] = { + {PORTA_0, ADC_0, 0 | (0 << 11)}, /* ADC0_IN0 */ + {PORTA_1, ADC_0, 0 | (1 << 11)}, /* ADC0_IN1 */ + {PORTA_2, ADC_0, 0 | (2 << 11)}, /* ADC0_IN2 */ + {PORTA_3, ADC_0, 0 | (3 << 11)}, /* ADC0_IN3 */ + {PORTA_4, ADC_0, 0 | (4 << 11)}, /* ADC0_IN4 */ + {PORTA_5, ADC_0, 0 | (5 << 11)}, /* ADC0_IN5 */ + {PORTA_6, ADC_0, 0 | (6 << 11)}, /* ADC0_IN6 */ + {PORTA_7, ADC_0, 0 | (7 << 11)}, /* ADC0_IN7 */ + {PORTB_0, ADC_0, 0 | (8 << 11)}, /* ADC0_IN8 */ + {PORTB_1, ADC_0, 0 | (9 << 11)}, /* ADC0_IN9 */ + {PORTC_0, ADC_0, 0 | (10 << 11)}, /* ADC0_IN10 */ + {PORTC_1, ADC_0, 0 | (11 << 11)}, /* ADC0_IN11 */ + {PORTC_2, ADC_0, 0 | (12 << 11)}, /* ADC0_IN12 */ + {PORTC_3, ADC_0, 0 | (13 << 11)}, /* ADC0_IN13 */ + {PORTC_4, ADC_0, 0 | (14 << 11)}, /* ADC0_IN14 */ + {PORTC_5, ADC_0, 0 | (15 << 11)}, /* ADC0_IN15 */ + {ADC_TEMP, ADC_0, 0 | (16 << 11)}, /* ADC0_IN16 */ + {ADC_VREF, ADC_0, 0 | (17 << 11)}, /* ADC0_IN17 */ + + {PORTA_0_MUL0, ADC_1, 0 | (0 << 11)}, /* ADC1_IN0 */ + {PORTA_1_MUL0, ADC_1, 0 | (1 << 11)}, /* ADC1_IN1 */ + {PORTA_2_MUL0, ADC_1, 0 | (2 << 11)}, /* ADC1_IN2 */ + {PORTA_3_MUL0, ADC_1, 0 | (3 << 11)}, /* ADC1_IN3 */ + {PORTA_4_MUL0, ADC_1, 0 | (4 << 11)}, /* ADC1_IN4 */ + {PORTA_5_MUL0, ADC_1, 0 | (5 << 11)}, /* ADC1_IN5 */ + {PORTA_6_MUL0, ADC_1, 0 | (6 << 11)}, /* ADC1_IN6 */ + {PORTA_7_MUL0, ADC_1, 0 | (7 << 11)}, /* ADC1_IN7 */ + {PORTB_0_MUL0, ADC_1, 0 | (8 << 11)}, /* ADC1_IN8 */ + {PORTB_1_MUL0, ADC_1, 0 | (9 << 11)}, /* ADC1_IN9 */ + {PORTC_0_MUL0, ADC_1, 0 | (10 << 11)}, /* ADC1_IN10 */ + {PORTC_1_MUL0, ADC_1, 0 | (11 << 11)}, /* ADC1_IN11 */ + {PORTC_2_MUL0, ADC_1, 0 | (12 << 11)}, /* ADC1_IN12 */ + {PORTC_3_MUL0, ADC_1, 0 | (13 << 11)}, /* ADC1_IN13 */ + {PORTC_4_MUL0, ADC_1, 0 | (14 << 11)}, /* ADC1_IN14 */ + {PORTC_5_MUL0, ADC_1, 0 | (15 << 11)}, /* ADC1_IN15 */ + {NC, NC, 0} +}; + +/* DAC PinMap */ +const PinMap PinMap_DAC[] = { + {PORTA_4, DAC_0, 0 | (0 << 11)}, /* DAC_OUT0 */ + {PORTA_5, DAC_0, 0 | (1 << 11)}, /* DAC_OUT1 */ + {NC, NC, 0} +}; + + +/* I2C PinMap */ +const PinMap PinMap_I2C_SDA[] = { + {PORTB_7, I2C_0, 6}, + {PORTB_9, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */ + {PORTB_11, I2C_1, 6}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PORTB_6, I2C_0, 6}, + {PORTB_8, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */ + {PORTB_10, I2C_1, 6}, + {NC, NC, 0} +}; + +/* PWM PinMap */ +const PinMap PinMap_PWM[] = { + {PORTA_8, PWM_0, 7 | (0 << 11)}, /* TIMER0_CH0 - Default */ + {PORTA_9, PWM_0, 7 | (1 << 11)}, /* TIMER0_CH1 - Default */ + {PORTA_10, PWM_0, 7 | (2 << 11)}, /* TIMER0_CH2 - Default */ + {PORTA_11, PWM_0, 7 | (3 << 11)}, /* TIMER0_CH3 - Default */ + {PORTE_9, PWM_0, 7 | (8 << 3) | (0 << 11)}, /* TIMER0_CH0 - GPIO_TIMER0_FULL_REMAP */ + {PORTE_11, PWM_0, 7 | (8 << 3) | (1 << 11)}, /* TIMER0_CH1 - GPIO_TIMER0_FULL_REMAP */ + {PORTE_13, PWM_0, 7 | (8 << 3) | (2 << 11)}, /* TIMER0_CH2 - GPIO_TIMER0_FULL_REMAP */ + {PORTE_14, PWM_0, 7 | (8 << 3) | (3 << 11)}, /* TIMER0_CH3 - GPIO_TIMER0_FULL_REMAP */ + + {PORTA_0, PWM_1, 7 | (0 << 11)}, /* TIMER1_CH0_ETI - Default */ + {PORTA_1, PWM_1, 7 | (1 << 11)}, /* TIMER1_CH1_ETI - Default */ + {PORTA_2, PWM_1, 7 | (2 << 11)}, /* TIMER1_CH2_ETI - Default */ + {PORTA_3, PWM_1, 7 | (3 << 11)}, /* TIMER1_CH3_ETI - Default */ + {PORTA_15, PWM_1, 7 | (9 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI- GPIO_TIMER1_PARTIAL_REMAP0 */ + {PORTB_3, PWM_1, 7 | (9 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_PARTIAL_REMAP0 */ + {PORTB_10, PWM_1, 7 | (10 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_PARTIAL_REMAP1 */ + {PORTB_11, PWM_1, 7 | (10 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_PARTIAL_REMAP1 */ + {PORTA_15, PWM_1, 7 | (11 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI - GPIO_TIMER1_FULL_REMAP */ + {PORTB_3, PWM_1, 7 | (11 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_FULL_REMAP */ + {PORTB_10, PWM_1, 7 | (11 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_FULL_REMAP */ + {PORTB_11, PWM_1, 7 | (11 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_FULL_REMAP */ + + {PORTA_6, PWM_2, 7 | (0 << 11)}, /* TIMER2_CH0 - Default */ + {PORTA_7, PWM_2, 7 | (1 << 11)}, /* TIMER2_CH1 - Default */ + {PORTB_0, PWM_2, 7 | (2 << 11)}, /* TIMER2_CH2 - Default */ + {PORTB_1, PWM_2, 7 | (3 << 11)}, /* TIMER2_CH3 - Default */ + {PORTB_4, PWM_2, 7 | (12 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_PARTIAL_REMAP */ + {PORTB_5, PWM_2, 7 | (12 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_PARTIAL_REMAP */ + {PORTC_6, PWM_2, 7 | (13 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_FULL_REMAP */ + {PORTC_7, PWM_2, 7 | (13 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_FULL_REMAP */ + {PORTC_8, PWM_2, 7 | (13 << 3) | (2 << 11)}, /* TIMER2_CH2 - GPIO_TIMER2_FULL_REMAP */ + {PORTC_9, PWM_2, 7 | (13 << 3) | (3 << 11)}, /* TIMER2_CH3 - GPIO_TIMER2_FULL_REMAP */ + + {PORTB_6, PWM_3, 7 | (0 << 11)}, /* TIMER3_CH0 - Default */ + {PORTB_7, PWM_3, 7 | (1 << 11)}, /* TIMER3_CH1 - Default */ + {PORTB_8, PWM_3, 7 | (2 << 11)}, /* TIMER3_CH2 - Default */ + {PORTB_9, PWM_3, 7 | (3 << 11)}, /* TIMER3_CH3 - Default */ + {PORTD_12, PWM_3, 7 | (14 << 3) | (0 << 11)}, /* TIMER3_CH0 - GPIO_TIMER3_REMAP */ + {PORTD_13, PWM_3, 7 | (14 << 3) | (1 << 11)}, /* TIMER3_CH1 - GPIO_TIMER3_REMAP */ + {PORTD_14, PWM_3, 7 | (14 << 3) | (2 << 11)}, /* TIMER3_CH2 - GPIO_TIMER3_REMAP */ + {PORTD_15, PWM_3, 7 | (14 << 3) | (3 << 11)}, /* TIMER3_CH3 - GPIO_TIMER3_REMAP */ + + {PORTA_0_MUL0, PWM_4, 7 | (0 << 11)}, /* TIMER4_CH0 - Default */ + {PORTA_1_MUL0, PWM_4, 7 | (1 << 11)}, /* TIMER4_CH1 - Default */ + {PORTA_2_MUL0, PWM_4, 7 | (2 << 11)}, /* TIMER4_CH2 - Default */ + {PORTA_3_MUL0, PWM_4, 7 | (3 << 11)}, /* TIMER4_CH3 - Default */ + + {PORTC_6_MUL0, PWM_5, 7 | (0 << 11)}, /* TIMER7_CH0 - Default */ + {PORTC_7_MUL0, PWM_5, 7 | (1 << 11)}, /* TIMER7_CH1 - Default */ + {PORTC_8_MUL0, PWM_5, 7 | (2 << 11)}, /* TIMER7_CH2 - Default */ + {PORTC_9_MUL0, PWM_5, 7 | (3 << 11)}, /* TIMER7_CH3 - Default */ + + {PORTA_2_MUL1, PWM_6, 7 | (0 << 11)}, /* TIMER8_CH0 - Default */ + {PORTA_3_MUL1, PWM_6, 7 | (1 << 11)}, /* TIMER8_CH1 - Default */ + {PORTE_5, PWM_6, 7 | (33 << 3) | (0 << 11)}, /* TIMER8_CH0 - GPIO_TIMER8_REMAP */ + {PORTE_6, PWM_6, 7 | (33 << 3) | (1 << 11)}, /* TIMER8_CH1 - GPIO_TIMER8_REMAP */ + + {PORTB_8_MUL0, PWM_7, 7 | (0 << 11)}, /* TIMER9_CH0 - Default */ + + {PORTB_9_MUL0, PWM_8, 7 | (0 << 11)}, /* TIMER10_CH0 - Default */ + + {PORTB_14, PWM_9, 7 | (0 << 11)}, /* TIMER11_CH0 - Default */ + {PORTB_15, PWM_9, 7 | (1 << 11)}, /* TIMER11_CH1 - Default */ + + {PORTA_6_MUL0, PWM_10, 7 | (0 << 11)}, /* TIMER12_CH0 - Default */ + + {PORTA_7_MUL0, PWM_11, 7 | (0 << 11)}, /* TIMER13_CH0 - Default */ + + {NC, NC, 0} +}; + +/* USART PinMap */ +const PinMap PinMap_UART_TX[] = { + {PORTA_9, UART_0, 7}, + {PORTB_6, UART_0, 7 | (3 << 3)}, /* GPIO_USART0_TX_REMAP */ + {PORTA_2, UART_1, 7}, + {PORTD_5, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_TX_REMAP */ + {PORTB_10, UART_2, 7}, + {PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */ + {PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */ + {PORTC_10, UART_3, 7}, + {PORTC_12, UART_4, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PORTA_10, UART_0, 1}, + {PORTB_7, UART_0, 1 | (3 << 3)}, /* GPIO_USART0_RX_REMAP */ + {PORTA_3, UART_1, 1}, + {PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */ + {PORTB_11, UART_2, 1}, + {PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */ + {PORTD_9, UART_2, 1 | (6 << 3)}, /* PGPIO_USART2_RX_PARTIAL_REMAP */ + {PORTC_11, UART_3, 1}, + {PORTD_2, UART_4, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PORTA_12, UART_0, 7}, + {PORTA_1, UART_1, 7}, + {PORTD_4, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_RTS_REMAP */ + {PORTB_14, UART_2, 7}, + {PORTD_12, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_RTS_FULL_REMAP */ + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PORTA_11, UART_0, 7}, + {PORTA_0, UART_1, 7}, + {PORTD_3, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_CTS_REMAP */ + {PORTB_13, UART_2, 7}, + {PORTD_11, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_CTS_FULL_REMAP */ + {NC, NC, 0} +}; + +/* SPI PinMap */ +const PinMap PinMap_SPI_MOSI[] = { + {PORTA_7, SPI_0, 7}, + {PORTB_5, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_15, SPI_1, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PORTA_6, SPI_0, 1}, + {PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_14, SPI_1, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PORTA_5, SPI_0, 7}, + {PORTB_3, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_13, SPI_1, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PORTA_4, SPI_0, 7}, + {PORTA_15, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_12, SPI_1, 7}, + {NC, NC, 0} +}; + +/* CAN PinMap */ +const PinMap PinMap_CAN_RD[] = { + {PORTA_11, CAN_0, 3}, + {PORTB_8, CAN_0, 3 | (26 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */ + {PORTD_0, CAN_0, 3 | (27 << 3)}, /* GPIO_CAN0_FULL_REMAP */ + {PORTB_12, CAN_1, 3}, + {PORTB_5, CAN_1, 3 | (29 << 3)}, /* GPIO_CAN1_REMAP */ + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PORTA_12, CAN_0, 7}, + {PORTB_9, CAN_0, 7 | (26 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */ + {PORTD_1, CAN_0, 7 | (27 << 3)}, /* GPIO_CAN0_FULL_REMAP */ + {PORTB_13, CAN_1, 7}, + {PORTB_6, CAN_1, 7 | (29 << 3)}, /* GPIO_CAN1_REMAP */ + {NC, NC, 0} +}; + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h new file mode 100644 index 00000000000..dbcbac16d17 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h @@ -0,0 +1,239 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Multiplex GPIO flag*/ +typedef enum { + MUL0 = 0x100, + MUL1 = 0x200, + MUL2 = 0x300, + MUL3 = 0x400 +} MULx; + +typedef enum { + PORTA_0 = 0x00, + PORTA_0_MUL0 = PORTA_0 | MUL0, + PORTA_1 = 0x01, + PORTA_1_MUL0 = PORTA_1 | MUL0, + PORTA_2 = 0x02, + PORTA_2_MUL0 = PORTA_2 | MUL0, + PORTA_2_MUL1 = PORTA_2 | MUL1, + PORTA_3 = 0x03, + PORTA_3_MUL0 = PORTA_3 | MUL0, + PORTA_3_MUL1 = PORTA_3 | MUL1, + PORTA_4 = 0x04, + PORTA_4_MUL0 = PORTA_4 | MUL0, + PORTA_5 = 0x05, + PORTA_5_MUL0 = PORTA_5 | MUL0, + PORTA_6 = 0x06, + PORTA_6_MUL0 = PORTA_6 | MUL0, + PORTA_7 = 0x07, + PORTA_7_MUL0 = PORTA_7 | MUL0, + PORTA_8 = 0x08, + PORTA_9 = 0x09, + PORTA_10 = 0x0A, + PORTA_11 = 0x0B, + PORTA_12 = 0x0C, + PORTA_13 = 0x0D, + PORTA_14 = 0x0E, + PORTA_15 = 0x0F, + + PORTB_0 = 0x10, + PORTB_0_MUL0 = PORTB_0 | MUL0, + PORTB_1 = 0x11, + PORTB_1_MUL0 = PORTB_1 | MUL0, + PORTB_2 = 0x12, + PORTB_3 = 0x13, + PORTB_4 = 0x14, + PORTB_5 = 0x15, + PORTB_6 = 0x16, + PORTB_7 = 0x17, + PORTB_8 = 0x18, + PORTB_8_MUL0 = PORTB_8 | MUL0, + PORTB_9 = 0x19, + PORTB_9_MUL0 = PORTB_9 | MUL0, + PORTB_10 = 0x1A, + PORTB_11 = 0x1B, + PORTB_12 = 0x1C, + PORTB_13 = 0x1D, + PORTB_14 = 0x1E, + PORTB_15 = 0x1F, + + PORTC_0 = 0x20, + PORTC_0_MUL0 = PORTC_0 | MUL0, + PORTC_1 = 0x21, + PORTC_1_MUL0 = PORTC_1 | MUL0, + PORTC_2 = 0x22, + PORTC_2_MUL0 = PORTC_2 | MUL0, + PORTC_3 = 0x23, + PORTC_3_MUL0 = PORTC_3 | MUL0, + PORTC_4 = 0x24, + PORTC_4_MUL0 = PORTC_4 | MUL0, + PORTC_5 = 0x25, + PORTC_5_MUL0 = PORTC_5 | MUL0, + PORTC_6 = 0x26, + PORTC_6_MUL0 = PORTC_6 | MUL0, + PORTC_7 = 0x27, + PORTC_7_MUL0 = PORTC_7 | MUL0, + PORTC_8 = 0x28, + PORTC_8_MUL0 = PORTC_8 | MUL0, + PORTC_9 = 0x29, + PORTC_9_MUL0 = PORTC_9 | MUL0, + PORTC_10 = 0x2A, + PORTC_11 = 0x2B, + PORTC_12 = 0x2C, + PORTC_13 = 0x2D, + PORTC_14 = 0x2E, + PORTC_15 = 0x2F, + + PORTD_0 = 0x30, + PORTD_1 = 0x31, + PORTD_2 = 0x32, + PORTD_3 = 0x33, + PORTD_4 = 0x34, + PORTD_5 = 0x35, + PORTD_6 = 0x36, + PORTD_7 = 0x37, + PORTD_8 = 0x38, + PORTD_9 = 0x39, + PORTD_10 = 0x3A, + PORTD_11 = 0x3B, + PORTD_12 = 0x3C, + PORTD_13 = 0x3D, + PORTD_14 = 0x3E, + PORTD_15 = 0x3F, + + PORTE_0 = 0x40, + PORTE_1 = 0x41, + PORTE_2 = 0x42, + PORTE_3 = 0x43, + PORTE_4 = 0x44, + PORTE_5 = 0x45, + PORTE_6 = 0x46, + PORTE_7 = 0x47, + PORTE_8 = 0x48, + PORTE_9 = 0x49, + PORTE_10 = 0x4A, + PORTE_11 = 0x4B, + PORTE_12 = 0x4C, + PORTE_13 = 0x4D, + PORTE_14 = 0x4E, + PORTE_15 = 0x4F, + + /* ADC internal channels */ + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + + + /* Arduino connector namings */ + A0 = PORTC_0, + A1 = PORTC_1, + A2 = PORTC_2, + A3 = PORTC_3, + A4 = PORTC_4, + A4_I2C_SDA = PORTC_11, + A4_I2C_SCL = PORTC_10, + A5 = PORTC_5, + D0 = PORTA_3, + D1 = PORTA_2, + D2 = PORTA_4, + D3 = PORTC_6, + D4 = PORTB_3, + D5 = PORTC_7, + D6 = PORTC_8, + D7 = PORTB_4, + D8 = PORTB_5, + D9 = PORTC_9, + D10 = PORTA_1, + D11 = PORTB_15, + D12 = PORTB_14, + D13 = PORTB_13, + D14 = PORTB_9, + D15 = PORTB_8, + + LED1 = PORTE_0, + LED2 = PORTE_1, + LED3 = PORTE_6, + + KEY2 = PORTA_0, + KEY3 = PORTB_1, + KEY4 = PORTD_2, + + BUTTON1 = KEY2, + BUTTON2 = KEY3, + BUTTON3 = KEY4, + + SERIAL_TX = PORTA_9, + SERIAL_RX = PORTA_10, + USBTX = PORTA_9, + USBRX = PORTA_10, + + I2C_SCL = PORTB_6, + I2C_SDA = PORTB_7, + SPI_MOSI = PORTA_7, + SPI_MISO = PORTA_6, + SPI_SCK = PORTA_5, + SPI_CS = PORTE_3, + PWM_OUT = PORTA_7, + + NC = (int)0xFFFFFFFF +} PinName; + +/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE, 5=PORTF) + BIT[3:0] pin number */ +#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF) +#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF)) + +/* Get mode,speed,remap function,channel of GPIO pin */ +#define GD_PIN_MODE_GET(X) (X & 0x07) +#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03) +#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F) +#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x0F) + +/* Defines GPIO pin direction */ +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT +} PinDirection; + +/* Defines mode types of GPIO pin */ +typedef enum { + MODE_AIN = 0, + MODE_IN_FLOATING, + MODE_IPD, + MODE_IPU, + MODE_OUT_OD, + MODE_OUT_PP, + MODE_AF_OD, + MODE_AF_PP, + PullDefault = MODE_IN_FLOATING, + PullUp = MODE_IPU, + PullDown = MODE_IPD, + PullNone = 11 +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct new file mode 100644 index 00000000000..ac88b41d1a0 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct @@ -0,0 +1,27 @@ +#! armcc -E +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ***** + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K) + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150) + RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s new file mode 100644 index 00000000000..a76c22c92ae --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s @@ -0,0 +1,337 @@ +;/*! +; \file startup_gd32f30x_cl.s +; \brief start up file +;*/ + +;/* +; Copyright (C) 2017 GigaDevice + +; 2017-02-10, V1.0.1, firmware for GD32F30x +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20010000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +EXMC_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler + + B . + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct new file mode 100644 index 00000000000..ac88b41d1a0 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct @@ -0,0 +1,27 @@ +#! armcc -E +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ***** + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K) + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150) + RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s new file mode 100644 index 00000000000..30044cb47c0 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s @@ -0,0 +1,334 @@ +;/*! +; \file startup_gd32f30x_cl.s +; \brief start up file +;*/ + +;/* +; Copyright (C) 2017 GigaDevice + +; 2017-02-10, V1.0.1, firmware for GD32F30x +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20018000 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +EXMC_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler + + B . + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld new file mode 100644 index 00000000000..2acfd1d1f6f --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* specify memory regions */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150 +} + +/* define output sections */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* initializes stack on the end of block */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s new file mode 100644 index 00000000000..813b02859ef --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s @@ -0,0 +1,393 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global VecTab +.global Default_Handler + +/* start address of the initialization .data */ +.word _sidata +/* start address of the .data section */ +.word _sdata +/* end address of the .data section */ +.word _edata + +/* reset Handler */ + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* copy the data segment into RAM */ + movs r1, #0 + b DataInit + +CopyData: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +DataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyData + +/* system clock intitialization*/ + bl SystemInit +/* static constructors */ +// bl __libc_init_array +/* jump to application's entry point */ +// bl main + bl _start +/* infinite loop */ + b . + + +.size Reset_Handler, .-Reset_Handler + + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +/* infinite loop */ + b . + .size Default_Handler, .-Default_Handler + + .section .isr_vector,"a",%progbits + .type VecTab, %object + .size VecTab, .-VecTab + + +VecTab: + + .word _estack /* Top of Stack */ + .word Reset_Handler /* 1,Reset Handler */ + .word NMI_Handler /* 2,NMI Handler */ + .word HardFault_Handler /* 3,Hard Fault Handler */ + .word MemManage_Handler /* 4,MPU Fault Handler */ + .word BusFault_Handler /* 5,Bus Fault Handler */ + .word UsageFault_Handler /* 6,Usage Fault Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler /* 11,SVCall Handler */ + .word DebugMon_Handler /* 12,Debug Monitor Handler */ + .word 0 /* Reserved */ + .word PendSV_Handler /* 14,PendSV Handler */ + .word SysTick_Handler /* 15,SysTick Handler */ + /* External Interrupts */ + .word WWDGT_IRQHandler /* 16,Window Watchdog Timer */ + .word LVD_IRQHandler /* 17,LVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* 18,Tamper through EXTI Line detect */ + .word RTC_IRQHandler /* 19,RTC through EXTI Line */ + .word FMC_IRQHandler /* 20,FMC */ + .word RCU_CTC_IRQHandler /* 21,RCU and CTC */ + .word EXTI0_IRQHandler /* 22,EXTI Line 0 */ + .word EXTI1_IRQHandler /* 23,EXTI Line 1 */ + .word EXTI2_IRQHandler /* 24,EXTI Line 2 */ + .word EXTI3_IRQHandler /* 25,EXTI Line 3 */ + .word EXTI4_IRQHandler /* 26,EXTI Line 4 */ + .word DMA0_Channel0_IRQHandler /* 27,DMA0 Channel 0 */ + .word DMA0_Channel1_IRQHandler /* 28,DMA0 Channel 1 */ + .word DMA0_Channel2_IRQHandler /* 29,DMA0 Channel 2 */ + .word DMA0_Channel3_IRQHandler /* 30,DMA0 Channel 3 */ + .word DMA0_Channel4_IRQHandler /* 31,DMA0 Channel 4 */ + .word DMA0_Channel5_IRQHandler /* 32,DMA0 Channel 5 */ + .word DMA0_Channel6_IRQHandler /* 33,DMA0 Channel 6 */ + .word ADC0_1_IRQHandler /* 34,ADC0 and ADC1 */ + .word CAN0_TX_IRQHandler /* 35,CAN0 TX */ + .word CAN0_RX0_IRQHandler /* 36,CAN0 RX0 */ + .word CAN0_RX1_IRQHandler /* 37,CAN0 RX1 */ + .word CAN0_EWMC_IRQHandler /* 38,CAN0 EWMC */ + .word EXTI5_9_IRQHandler /* 39,EXTI5 to EXTI9 */ + .word TIMER0_BRK_TIMER8_IRQHandler /* 40,TIMER0 Break and TIMER8 */ + .word TIMER0_UP_TIMER9_IRQHandler /* 41,TIMER0 Update and TIMER9 */ + .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42,TIMER0 Trigger and Commutation and TIMER10 */ + .word TIMER0_Channel_IRQHandler /* 43,TIMER0 Channel Capture Compare */ + .word TIMER1_IRQHandler /* 44,TIMER4 */ + .word TIMER2_IRQHandler /* 45,TIMER2 */ + .word TIMER3_IRQHandler /* 46,TIMER3 */ + .word I2C0_EV_IRQHandler /* 47,I2C0 Event */ + .word I2C0_ER_IRQHandler /* 48,I2C0 Error */ + .word I2C1_EV_IRQHandler /* 49,I2C1 Event */ + .word I2C1_ER_IRQHandler /* 50,I2C1 Error */ + .word SPI0_IRQHandler /* 51,SPI0 */ + .word SPI1_IRQHandler /* 52,SPI1 */ + .word USART0_IRQHandler /* 53,USART0 */ + .word USART1_IRQHandler /* 54,USART1 */ + .word USART2_IRQHandler /* 55,USART2 */ + .word EXTI10_15_IRQHandler /* 56,EXTI10 to EXTI15 */ + .word RTC_Alarm_IRQHandler /* 57,RTC Alarm */ + .word USBFS_WKUP_IRQHandler /* 58,USBFS Wakeup */ + .word TIMER7_BRK_TIMER11_IRQHandler /* 59,TIMER7 Break and TIMER11 */ + .word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */ + .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */ + .word TIMER7_Channel_IRQHandler /* 62,TIMER7 Capture Compare */ + .word 0 /* Reserved */ + .word EXMC_IRQHandler /* 64,EXMC */ + .word 0 /* Reserved */ + .word TIMER4_IRQHandler /* 66,TIMER4 */ + .word SPI2_IRQHandler /* 67,SPI2 */ + .word UART3_IRQHandler /* 68,UART3 */ + .word UART4_IRQHandler /* 69,UART4 */ + .word TIMER5_IRQHandler /* 70,TIMER5 */ + .word TIMER6_IRQHandler /* 71,TIMER6 */ + .word DMA1_Channel0_IRQHandler /* 72,DMA1 Channel0 */ + .word DMA1_Channel1_IRQHandler /* 73,DMA1 Channel1 */ + .word DMA1_Channel2_IRQHandler /* 74,DMA1 Channel2 */ + .word DMA1_Channel3_IRQHandler /* 75,DMA1 Channel3 */ + .word DMA1_Channel4_IRQHandler /* 76,DMA1 Channel4 */ + .word ENET_IRQHandler /* 77,Ethernet */ + .word ENET_WKUP_IRQHandler /* 78,Ethernet Wakeup through EXTI line */ + .word CAN1_TX_IRQHandler /* 79,CAN1 TX */ + .word CAN1_RX0_IRQHandler /* 80,CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* 81,CAN1 RX1 */ + .word CAN1_EWMC_IRQHandler /* 82,CAN1 EWMC */ + .word USBFS_IRQHandler /* 83,USBFS */ + +/* dummy Exception Handlers */ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDGT_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak LVD_IRQHandler + .thumb_set LVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak RCU_CTC_IRQHandler + .thumb_set RCU_CTC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA0_Channel0_IRQHandler + .thumb_set DMA0_Channel0_IRQHandler,Default_Handler + + .weak DMA0_Channel1_IRQHandler + .thumb_set DMA0_Channel1_IRQHandler,Default_Handler + + .weak DMA0_Channel2_IRQHandler + .thumb_set DMA0_Channel2_IRQHandler,Default_Handler + + .weak DMA0_Channel3_IRQHandler + .thumb_set DMA0_Channel3_IRQHandler,Default_Handler + + .weak DMA0_Channel4_IRQHandler + .thumb_set DMA0_Channel4_IRQHandler,Default_Handler + + .weak DMA0_Channel5_IRQHandler + .thumb_set DMA0_Channel5_IRQHandler,Default_Handler + + .weak DMA0_Channel6_IRQHandler + .thumb_set DMA0_Channel6_IRQHandler,Default_Handler + + .weak ADC0_1_IRQHandler + .thumb_set ADC0_1_IRQHandler,Default_Handler + + .weak CAN0_TX_IRQHandler + .thumb_set CAN0_TX_IRQHandler,Default_Handler + + .weak CAN0_RX0_IRQHandler + .thumb_set CAN0_RX0_IRQHandler,Default_Handler + + .weak CAN0_RX1_IRQHandler + .thumb_set CAN0_RX1_IRQHandler,Default_Handler + + .weak CAN0_EWMC_IRQHandler + .thumb_set CAN0_EWMC_IRQHandler,Default_Handler + + .weak EXTI5_9_IRQHandler + .thumb_set EXTI5_9_IRQHandler,Default_Handler + + .weak TIMER0_BRK_TIMER8_IRQHandler + .thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler + + .weak TIMER0_UP_TIMER9_IRQHandler + .thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler + + .weak TIMER0_TRG_CMT_TIMER10_IRQHandler + .thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler + + .weak TIMER0_Channel_IRQHandler + .thumb_set TIMER0_Channel_IRQHandler,Default_Handler + + .weak TIMER1_IRQHandler + .thumb_set TIMER1_IRQHandler,Default_Handler + + .weak TIMER2_IRQHandler + .thumb_set TIMER2_IRQHandler,Default_Handler + + .weak TIMER3_IRQHandler + .thumb_set TIMER3_IRQHandler,Default_Handler + + .weak I2C0_EV_IRQHandler + .thumb_set I2C0_EV_IRQHandler,Default_Handler + + .weak I2C0_ER_IRQHandler + .thumb_set I2C0_ER_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI0_IRQHandler + .thumb_set SPI0_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART0_IRQHandler + .thumb_set USART0_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI10_15_IRQHandler + .thumb_set EXTI10_15_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBFS_WKUP_IRQHandler + .thumb_set USBFS_WKUP_IRQHandler,Default_Handler + + .weak TIMER7_BRK_TIMER11_IRQHandler + .thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler + + .weak TIMER7_UP_TIMER12_IRQHandler + .thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler + + .weak TIMER7_TRG_CMT_TIMER13_IRQHandler + .thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler + + .weak TIMER7_Channel_IRQHandler + .thumb_set TIMER7_Channel_IRQHandler,Default_Handler + + .weak EXMC_IRQHandler + .thumb_set EXMC_IRQHandler,Default_Handler + + .weak TIMER4_IRQHandler + .thumb_set TIMER4_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak TIMER5_IRQHandler + .thumb_set TIMER5_IRQHandler,Default_Handler + + .weak TIMER6_IRQHandler + .thumb_set TIMER6_IRQHandler,Default_Handler + + .weak DMA1_Channel0_IRQHandler + .thumb_set DMA1_Channel0_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak ENET_IRQHandler + .thumb_set ENET_IRQHandler,Default_Handler + + .weak ENET_WKUP_IRQHandler + .thumb_set ENET_WKUP_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_EWMC_IRQHandler + .thumb_set CAN1_EWMC_IRQHandler,Default_Handler + + .weak USBFS_IRQHandler + .thumb_set USBFS_IRQHandler,Default_Handler diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf new file mode 100644 index 00000000000..680a82f2c24 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ + +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000; +define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000150; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x3000; +define symbol __ICFEDIT_size_heap__ = 0x6000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block HEAP, block CSTACK }; \ No newline at end of file diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s new file mode 100644 index 00000000000..76c359f8a45 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s @@ -0,0 +1,501 @@ +;/*! +; \file startup_gd32f30x_cl.s +; \brief start up file +;*/ + +;/* +; Copyright (C) 2017 GigaDevice + +; 2017-02-10, V1.0.1, firmware for GD32F30x +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; 63:Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; 65:Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK ENET_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_WKUP_IRQHandler + B ENET_WKUP_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + END \ No newline at end of file diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis.h new file mode 100644 index 00000000000..4634758f3e8 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2018 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in GD32F307VG specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "gd32f30x.h" +#include "cmsis_nvic.h" + +#endif /* MBED_CMSIS_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis_nvic.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis_nvic.h new file mode 100644 index 00000000000..ef956c78344 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 68) /* ARM CORE:16 Vectors; MCU Peripherals:68 Vectors */ +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 + + +#endif /* MBED_CMSIS_NVIC_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x.h new file mode 100644 index 00000000000..40534e9435f --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x.h @@ -0,0 +1,362 @@ +/*! + \file gd32f30x.h + \brief general definitions for GD32F30x +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.1, firmware for GD32F30x +*/ + +#ifndef GD32F30X_H +#define GD32F30X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* define GD32F30x */ +#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL) + /* #define GD32F30X_HD */ + /* #define GD32F30X_XD */ + /* #define GD32F30X_CL */ +#endif /* define GD32F30x */ + +#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL) + #error "Please select the target GD32F30x device in gd32f30x.h file" +#endif /* undefine GD32F30x tip */ + + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined HXTAL_VALUE +#ifdef GD32F30X_CL +#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ +#else +#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ +#endif /* HXTAL_VALUE */ +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */ +#if !defined (IRC48M_VALUE) +#define IRC48M_VALUE ((uint32_t)48000000) +#endif /* internal 48MHz RC oscillator value */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32F30x firmware library version number V1.0 */ +#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F30x_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */ +#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ +#define __FPU_PRESENT 0 /*!< FPU present */ +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M4 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ + RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ +#ifdef GD32F30X_HD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ + TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ + TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ + TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ + TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ +#endif /* GD32F30X_HD */ + +#ifdef GD32F30X_XD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ +#endif /* GD32F30X_XD */ + +#ifdef GD32F30X_CL + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ + ENET_IRQn = 61, /*!< ENET global interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ +#endif /* GD32F30X_CL */ + +} IRQn_Type; + +/* includes */ +#include "core_cm4.h" +#include "system_gd32f30x.h" +#include + +#define GD_MBED_USED + +#ifdef GD_MBED_USED +typedef enum +{ + GD_OK = 0x00U, + GD_ERROR = 0x01U, + GD_BUSY = 0x02U, + GD_TIMEOUT = 0x03U +}gd_status_enum; + +typedef enum +{ + OP_STATE_RESET = 0x00U, + OP_STATE_READY = 0x01U, + OP_STATE_BUSY = 0x02U, + OP_STATE_TIMEOUT = 0x03U, + OP_STATE_ERROR = 0x04U, + OP_STATE_ABORT = 0x05U, + OP_STATE_LISTEN = 0x06U, + + OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */ + OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */ + + OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */ + OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */ + + OP_STATE_BUTT +}operation_state_enum; +#endif + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +//typedef enum {FALSE = 0, TRUE = !FALSE} bool; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ +#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32f30x_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x_libopt.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x_libopt.h new file mode 100644 index 00000000000..37f098af194 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x_libopt.h @@ -0,0 +1,40 @@ +/*! + \file gd32f30x_libopt.h + \brief library optional for gd32f30x +*/ + +/* + Copyright (C) 2017 GigaDevice + + 2017-02-10, V1.0.0, firmware for GD32F30x +*/ + +#ifndef GD32F30X_LIBOPT_H +#define GD32F30X_LIBOPT_H + +#include "gd32f30x_rcu.h" +#include "gd32f30x_adc.h" +#include "gd32f30x_can.h" +#include "gd32f30x_crc.h" +#include "gd32f30x_ctc.h" +#include "gd32f30x_dac.h" +#include "gd32f30x_dbg.h" +#include "gd32f30x_dma.h" +#include "gd32f30x_exti.h" +#include "gd32f30x_fmc.h" +#include "gd32f30x_fwdgt.h" +#include "gd32f30x_gpio.h" +#include "gd32f30x_i2c.h" +#include "gd32f30x_pmu.h" +#include "gd32f30x_bkp.h" +#include "gd32f30x_rtc.h" +#include "gd32f30x_sdio.h" +#include "gd32f30x_spi.h" +#include "gd32f30x_timer.h" +#include "gd32f30x_usart.h" +#include "gd32f30x_wwdgt.h" +#include "gd32f30x_misc.h" +#include "gd32f30x_enet.h" +#include "gd32f30x_exmc.h" + +#endif /* GD32F30X_LIBOPT_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/hal_tick.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/hal_tick.h new file mode 100644 index 00000000000..8dd51bed02c --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/hal_tick.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "gd32f30x.h" +#include "cmsis_nvic.h" + +#define TICKER_TIMER TIMER2 +#define TICKER_TIMER_IRQ TIMER2_IRQn +#define TICKER_TIMER_RCU_CLOCK_ENABLE rcu_periph_clock_enable(RCU_TIMER2); +#define TICKER_TIMER_DEBUG_STOP dbg_periph_enable(DBG_TIMER2_HOLD); + +#define TICKER_TIMER_RESET_ENABLE rcu_periph_reset_enable(RCU_TIMER2RST) +#define TICKER_TIMER_RESET_DISABLE rcu_periph_reset_disable(RCU_TIMER2RST) + +/* 16 for 16-bit timer, 32 for 32-bit timer */ +#define TICKER_TIMER_WIDTH_BIT 16 + +/* 0 for CK_APB1, 1 for CK_APB2 */ +#define TICKER_TIMER_CKAPB 1 + +#ifdef __cplusplus +} +#endif + +#endif /* __HAL_TICK_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.c new file mode 100644 index 00000000000..555241dc9f1 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.c @@ -0,0 +1,987 @@ +/*! + \file system_gd32f30x.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F30x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f30x.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M) +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) +//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000) + +/* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) +#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M; +static void system_clock_8m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M; +static void system_clock_120m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL; +static void system_clock_120m_hxtal(void); +#endif /* __SYSTEM_CLOCK_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit (void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* reset the RCU clock configuration to the default reset state */ + /* Set IRC8MEN bit */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* Reset CFG0 and CFG1 registers */ + RCU_CFG0 = 0x00000000U; + RCU_CFG1 = 0x00000000U; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x009f0000U; +#elif defined(GD32F30X_CL) + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00ff0000U; +#endif + + /* reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_IRC8M + system_clock_8m_irc8m(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) + system_clock_120m_irc8m(); + +#elif defined (__SYSTEM_CLOCK_HXTAL) + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) + system_clock_120m_hxtal(); +#endif /* __SYSTEM_CLOCK_IRC8M */ +} + +#ifdef __SYSTEM_CLOCK_IRC8M +/*! + \brief configure the system clock to 8M by IRC8M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select IRC8M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; + + /* wait until IRC8M is selected as system clock */ + while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) +/*! + \brief configure the system clock to 120M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_HXTAL) +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL12; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL18; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL27; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} +#endif /* __SYSTEM_CLOCK_IRC8M */ + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate (void) +{ + uint32_t sws; + uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src; +#ifdef GD32F30X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F30X_CL */ + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { + /* PLL clock source is HXTAL or IRC48M */ + pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); + + if(RCU_PLLPRESRC_HXTAL == pllpresel){ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + }else{ + /* PLL clock source is IRC48 */ + ck_src = IRC48M_VALUE; + } + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE/2U; + } +#elif defined(GD32F30X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src/predv1)*pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F30X_HD and GD32F30X_XD */ + }else{ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE/2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){ + pllmf |= 0x20U; + } + + if( pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + if(pllmf > 61U){ + pllmf = 63U; + } + SystemCoreClock = ck_src*pllmf; + #ifdef GD32F30X_CL + if(15U == pllmf){ + SystemCoreClock = ck_src*6U + ck_src/2U; + } + #endif /* GD32F30X_CL */ + + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.h new file mode 100644 index 00000000000..cb25f122fd1 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32f30x.h + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + GD32F30x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F30X_H +#define SYSTEM_GD32F30X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit (void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F30X_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/analogin_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/analogin_api.c new file mode 100644 index 00000000000..0fda6be8b77 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/analogin_api.c @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "mbed_error.h" + +#define DEV_ADC_ACCURACY_12BIT 0xFFF +#define DEV_ADC_PRECISION_12TO16(val) ((val << 4)| ((val >> 8) & (uint16_t)0x000F)) + +/** Initialize the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param pin The analogin pin name + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + uint32_t periph; + + MBED_ASSERT(obj); + + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + uint32_t function = pinmap_function(pin, PinMap_ADC); + MBED_ASSERT(function != (uint32_t)NC); + + obj->channel = GD_PIN_CHANNEL_GET(function); + MBED_ASSERT(obj->channel <= ADC_CHANNEL_17); + + obj->pin = pin; + + if ((ADC_CHANNEL_17 == obj->channel) || (ADC_CHANNEL_16 == obj->channel)) { + /* no need to config port */ + } else { + pinmap_pinout(pin, PinMap_ADC); + } + + + periph = obj->adc; + + /* when pin >= ADC_TEMP, it indicates that the channel has no external pins */ + if (pin < ADC_TEMP) { + pinmap_pinout(pin, PinMap_ADC); + } + + /* ADC clock enable */ + switch (periph) { + case ADC0: + rcu_periph_clock_enable(RCU_ADC0); + break; + + case ADC1: + rcu_periph_clock_enable(RCU_ADC1); + break; +#ifndef GD32F30X_CL + case ADC2: + rcu_periph_clock_enable(RCU_ADC2); + break; +#endif /* GD32F30X_CL */ + } + + /* ADC clock cannot be greater than 42M */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV6); + + /* ADC configuration */ + adc_data_alignment_config(obj->adc, ADC_DATAALIGN_RIGHT); + adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1); + adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE); + adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE); + adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); + adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE); + + /* ADC enable */ + adc_enable(obj->adc); + adc_calibration_enable(obj->adc); +} + +/** Read the value from analogin pin, represented as an unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16bit value representing the current input voltage + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t reval; + + adc_regular_channel_config(obj->adc, 0, obj->channel, ADC_SAMPLETIME_7POINT5); + + adc_flag_clear(obj->adc, ADC_FLAG_EOC); + /* start Conversion */ + adc_software_trigger_enable(obj->adc, ADC_REGULAR_CHANNEL); + + while (SET != adc_flag_get(obj->adc, ADC_FLAG_EOC)) { + } + /* ADC actual accuracy is 12 bits */ + reval = adc_regular_data_read(obj->adc); + + reval = DEV_ADC_PRECISION_12TO16(reval); + + return reval; +} + +/** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @param obj The analogin object + * @return A floating value representing the current input voltage + */ +float analogin_read(analogin_t *obj) +{ + uint16_t reval; + + adc_regular_channel_config(obj->adc, 0, obj->channel, ADC_SAMPLETIME_7POINT5); + + adc_flag_clear(obj->adc, ADC_FLAG_EOC); + /* start Conversion */ + adc_software_trigger_enable(obj->adc, ADC_REGULAR_CHANNEL); + /* wait for conversion to complete */ + while (SET != adc_flag_get(obj->adc, ADC_FLAG_EOC)) { + } + /* ADC actual accuracy is 12 bits */ + reval = adc_regular_data_read(obj->adc); + + return (float)reval * (1.0f / (float)DEV_ADC_ACCURACY_12BIT); +} + +#endif /* DEVICE_ANALOGIN */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/analogout_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/analogout_api.c new file mode 100644 index 00000000000..8b8dda3dc51 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/analogout_api.c @@ -0,0 +1,158 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogout_api.h" +#include "mbed_assert.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +#define DEV_DAC_ACCURACY_12BIT (0xFFF) // 12 bits +#define DEV_DAC_BITS (12) + +/** Initialize the analogout peripheral + * + * Configures the pin used by analogout. + * @param obj The analogout object to initialize + * @param pin The analogout pin name + */ +void analogout_init(dac_t *obj, PinName pin) +{ + /* get the peripheral name from the pin and assign it to the object */ + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName)NC); + + /* get the pin function and assign the used channel to the object */ + uint32_t function = pinmap_function(pin, PinMap_DAC); + MBED_ASSERT(function != (uint32_t)NC); + + obj->channel = GD_PIN_CHANNEL_GET(function); + MBED_ASSERT(obj->channel <= DAC1); + + /* configure GPIO */ + pinmap_pinout(pin, PinMap_DAC); + + /* save the pin for future use */ + obj->pin = pin; + + /* enable DAC clock */ + rcu_periph_clock_enable(RCU_DAC); + + /* configure DAC */ + dac_wave_mode_config(obj->channel, DAC_WAVE_DISABLE); + dac_trigger_disable(obj->channel); + dac_output_buffer_enable(obj->channel); + analogout_write_u16(obj, 0); +} + +/** Release the analogout object + * + * Note: This is not currently used in the mbed-drivers + * @param obj The analogout object + */ +void analogout_free(dac_t *obj) +{ + /* Reset DAC and disable clock */ + dac_deinit(); + rcu_periph_clock_disable(RCU_DAC); + + /* configure GPIO */ + /* get the pin function and assign the used channel to the object */ + uint32_t function = pinmap_function(obj->pin, PinMap_DAC); + MBED_ASSERT(function != (uint32_t)NC); + + pin_function(obj->pin, function); +} + +/** set the output voltage with specified as a integer + * + * @param obj The analogin object + * @param value The integer-point output voltage to be set + */ +static inline void dev_dac_data_set(dac_t *obj, int value) +{ + dac_data_set(obj->channel, DAC_ALIGN_12B_R, (value & DEV_DAC_ACCURACY_12BIT)); + + dac_enable(obj->channel); + + dac_software_trigger_enable(obj->channel); +} + +/** get the current DAC data + * + * @param obj The analogin object + * @return DAC data + */ +static inline int dev_dac_data_get(dac_t *obj) +{ + return (int)dac_output_value_get(obj->channel); +} + +/** Set the output voltage, specified as a percentage (float) + * + * @param obj The analogin object + * @param value The floating-point output voltage to be set + */ +void analogout_write(dac_t *obj, float value) +{ + if (value < 0.0f) { + /* when the value is less than 0.0, set DAC output date to 0 */ + dev_dac_data_set(obj, 0); + } else if (value > 1.0f) { + /* when the value is more than 1.0, set DAC output date to 0xFFF */ + dev_dac_data_set(obj, (int)DEV_DAC_ACCURACY_12BIT); + } else { + dev_dac_data_set(obj, (int)(value * (float)DEV_DAC_ACCURACY_12BIT)); + } +} + +/** Set the output voltage, specified as unsigned 16-bit + * + * @param obj The analogin object + * @param value The unsigned 16-bit output voltage to be set + */ +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + dev_dac_data_set(obj, value >> (16 - DEV_DAC_BITS)); +} + +/** Read the current voltage value on the pin + * + * @param obj The analogin object + * @return A floating-point value representing the current voltage on the pin, + * measured as a percentage + */ +float analogout_read(dac_t *obj) +{ + uint32_t ret_val = dev_dac_data_get(obj); + return (float)ret_val * (1.0f / (float)DEV_DAC_ACCURACY_12BIT); +} + +/** Read the current voltage value on the pin, as a normalized unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16-bit value representing the current voltage on the pin + */ +uint16_t analogout_read_u16(dac_t *obj) +{ + uint32_t ret_val = dev_dac_data_get(obj); + return (ret_val << 4) | ((ret_val >> 8) & 0x000F); +} + +#endif /* DEVICE_ANALOGOUT */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/can_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/can_api.c new file mode 100644 index 00000000000..70371d6880c --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/can_api.c @@ -0,0 +1,630 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "can_api.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "mbed_error.h" + +#if DEVICE_CAN + +/* BS1[3:0] + 1 + BS2[2:0] + 1 */ +#define DEV_CAN_BT_SEG_MAX 24 +#define DEV_CAN_BT_SEG_MIN 4 + +/* CAN related register mask */ +#define DEV_CAN_BS1_MASK 0x000F0000 +#define DEV_CAN_BS2_MASK 0x00700000 +#define DEV_CAN_BAUDPSC_MASK 0x000003FF +#define DEV_CAN_SJW_MASK 0x03000000 +/* CAN0 interrupt vector number */ +#define CAN0_IRQ_BASE_NUM 19 + +/* CAN1 interrupt vector number */ +#define CAN1_IRQ_BASE_NUM 63 + +static uint32_t can_irq_ids[2] = {0}; +static can_irq_handler irq_callback; + +/** CAN interrupt handle . + * + * @param can_periph CAN0 or CAN1. + * @param id the CANx index . + */ +static void dev_can_irq_handle(uint32_t periph, int id) +{ + uint32_t flag0 = 0, flag1 = 0, flag2 = 0; + + flag0 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF0); + flag1 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF1); + flag2 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF2); + + if (flag0) { + can_flag_clear(periph, CAN_FLAG_MTF0); + } + if (flag1) { + can_flag_clear(periph, CAN_FLAG_MTF1); + } + if (flag2) { + can_flag_clear(periph, CAN_FLAG_MTF2); + } + + /* CAN transmit complete interrupt handle */ + if (flag0 || flag1 || flag2) { + irq_callback(can_irq_ids[id], IRQ_TX); + } + + /* CAN receive complete interrupt handle */ + if (CAN_INTEN_RFNEIE0 == (CAN_INTEN(periph) & CAN_INTEN_RFNEIE0)) { + if (0 != can_receive_message_length_get(periph, CAN_FIFO0)) { + irq_callback(can_irq_ids[id], IRQ_RX); + } + } + + /* CAN error interrupt handle */ + if (SET == can_interrupt_flag_get(periph, CAN_INT_FLAG_ERRIF)) { + /* passive error interrupt handle */ + if (CAN_INTEN_PERRIE == (CAN_INTEN(periph) & CAN_INTEN_PERRIE)) { + if (SET == can_flag_get(periph, CAN_FLAG_PERR)) { + irq_callback(can_irq_ids[id], IRQ_PASSIVE); + } + } + + /* bus-off interrupt handle */ + if (CAN_INTEN_BOIE == (CAN_INTEN(periph) & CAN_INTEN_BOIE)) { + if (SET == can_flag_get(periph, CAN_FLAG_BOERR)) { + irq_callback(can_irq_ids[id], IRQ_BUS); + } + } + + irq_callback(can_irq_ids[id], IRQ_ERROR); + } +} + +/** CAN1 Interrupt Request entry . + * + */ +static void dev_can0_irq_entry(void) +{ + dev_can_irq_handle(CAN0, 0); +} + +/** CAN1 Interrupt Request entry . + * + */ +static void dev_can1_irq_entry(void) +{ + dev_can_irq_handle(CAN1, 1); +} + +/** Config the CAN mode . + * + * @param can_periph CAN0 or CAN1. + * @param mode the mode to be set. + */ +static void dev_can_mode_config(uint32_t can_periph, uint32_t mode) +{ + /* enter the initialization mode, only in initialization mode CAN register can be configured */ + can_working_mode_set(can_periph, CAN_MODE_INITIALIZE); + + CAN_BT(can_periph) &= ~BT_MODE(3); + CAN_BT(can_periph) |= BT_MODE(mode); + + /* enter the normal mode */ + can_working_mode_set(can_periph, CAN_MODE_NORMAL); +} + +/** Config the interrupt . + * + * @param can_periph CAN0 or CAN1. + * @param interrupt The interrupt type. + * @param enable enable or disable. + */ +static void dev_can_interrupt_config(uint32_t can_periph, uint32_t interrupt, uint32_t enable) +{ + if (enable) { + can_interrupt_enable(can_periph, interrupt); + } else { + can_interrupt_disable(can_periph, interrupt); + } +} + +/* This table can be used to calculate bit time +The first value is bit segment 1(BS1[3:0]), the second is bit segment 2(BS2[2:0]) */ +static const int sampling_points[23][2] = { + {0x0, 0x0}, /* 2, 50% */ + {0x1, 0x0}, /* 3, 67% */ + {0x2, 0x0}, /* 4, 75% */ + {0x3, 0x0}, /* 5, 80% */ + {0x3, 0x1}, /* 6, 67% */ + {0x4, 0x1}, /* 7, 71% */ + {0x5, 0x1}, /* 8, 75% */ + {0x6, 0x1}, /* 9, 78% */ + {0x6, 0x2}, /* 10, 70% */ + {0x7, 0x2}, /* 11, 73% */ + {0x8, 0x2}, /* 12, 75% */ + {0x9, 0x2}, /* 13, 77% */ + {0x9, 0x3}, /* 14, 71% */ + {0xA, 0x3}, /* 15, 73% */ + {0xB, 0x3}, /* 16, 75% */ + {0xC, 0x3}, /* 17, 76% */ + {0xD, 0x3}, /* 18, 78% */ + {0xD, 0x4}, /* 19, 74% */ + {0xE, 0x4}, /* 20, 75% */ + {0xF, 0x4}, /* 21, 76% */ + {0xF, 0x5}, /* 22, 73% */ + {0xF, 0x6}, /* 23, 70% */ + {0xF, 0x7}, /* 24, 67% */ +}; + +/** Set the baudrate. + * + * @param freq The frequency value to be set. + * + * @returns + * CAN_BT register value + */ +static unsigned int dev_can_baudrate_set(int freq) +{ + uint32_t reval; + uint16_t baud_psc; + uint16_t baud_psc_max; + uint32_t temp; + uint32_t bt_reg_config; + uint8_t flag; + int bits; + + flag = 0; + + /* computes the value that the CAN_BT register needs to be configured */ + /* (BAUDPSC[9:0] + 1) * ((BS1[3:0] + 1) + (BS2[2:0] + 1) + SJW(always 1)) */ + bt_reg_config = (rcu_clock_freq_get(CK_APB1) / freq); + /* BAUDPSC[9:0] minimum value */ + baud_psc = bt_reg_config / DEV_CAN_BT_SEG_MAX; + /* BAUDPSC[9:0] maximum value */ + baud_psc_max = bt_reg_config / DEV_CAN_BT_SEG_MIN; + + while ((!flag) && (baud_psc < baud_psc_max)) { + baud_psc++; + for (bits = 22; bits > 0; bits--) { + temp = (bits + 3) * (baud_psc + 1); + if (temp == bt_reg_config) { + flag = 1; + break; + } + } + } + + if (flag) { + reval = ((sampling_points[bits][1] << 20) & DEV_CAN_BS2_MASK) + | ((sampling_points[bits][0] << 16) & DEV_CAN_BS1_MASK) + | ((1 << 24) & DEV_CAN_SJW_MASK) + | ((baud_psc << 0) & DEV_CAN_BAUDPSC_MASK); + } else { + /* CAN_BT register reset value */ + reval = 0x01230000; + } + + return reval; +} + +/** init the CAN frequency. + * + * @param rd receive pin. + * @param td transmit pin. + * @param hz The bus frequency in hertz. + */ +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) +{ + CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + obj->can = (CANName)pinmap_merge(can_rd, can_td); + + MBED_ASSERT((int)obj->can != NC); + + if (obj->can == CAN_0) { + rcu_periph_clock_enable(RCU_CAN0); + can_deinit(obj->can); + obj->index = 0; + } else if (obj->can == CAN_1) { + rcu_periph_clock_enable(RCU_CAN0); + rcu_periph_clock_enable(RCU_CAN1); + can_deinit(obj->can); + obj->index = 1; + } else { + return; + } + + /* Configure the CAN pins */ + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); + if (rd != NC) { + pin_mode(rd, PullUp); + } + if (td != NC) { + pin_mode(td, PullUp); + } + + dev_can_mode_config(obj->can, CAN_NORMAL_MODE); + + can_frequency(obj, hz); + + if (obj->can == CAN_0) { + can_filter(obj, 0, 0, CANStandard, 0); + } else { + can_filter(obj, 0, 0, CANStandard, 14); + } +} + +/** init the CAN. + * + */ +void can_init(can_t *obj, PinName rd, PinName td) +{ + can_init_freq(obj, rd, td, 500000); +} + +/** disable CAN. + * + */ +void can_free(can_t *obj) +{ + can_deinit(obj->can); + + if (obj->can == CAN0) { + rcu_periph_clock_disable(RCU_CAN0); + } + + if (obj->can == CAN1) { + rcu_periph_clock_disable(RCU_CAN1); + } +} + +/** Set the frequency of the CAN interface. + * + * @param hz The bus frequency in hertz. + * + * @returns + * 1 if successful, + * 0 otherwise + */ +int can_frequency(can_t *obj, int hz) +{ + int reval; + + /* The maximum baud rate support to 1M */ + if (hz <= 1000000) { + if (SUCCESS == can_working_mode_set(obj->can, CAN_MODE_INITIALIZE)) { + CAN_BT(obj->can) = dev_can_baudrate_set(hz); + } else { + error("the configuration of can frequency is out of range \r\n"); + } + + if (SUCCESS == can_working_mode_set(obj->can, CAN_MODE_NORMAL)) { + reval = 1; + } else { + reval = 0; + } + } + + return reval; +} + +/** init the interrupt. + * + * @param handler the interrupt callback. + * @param id the CANx index. + */ +void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +{ + irq_callback = handler; + can_irq_ids[obj->index] = id; +} + +/** disable the interrupt. + * + */ +void can_irq_free(can_t *obj) +{ + if (CAN0 == obj->can) { + can_interrupt_disable(obj->can, CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 | \ + CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); + } + + if (CAN1 == obj->can) { + can_interrupt_disable(obj->can, CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 | \ + CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); + } + + can_irq_ids[obj->index] = 0; +} + +/** Set the interrupt handle. + * + * @param type The interrupt type. + * @param enable enable or disable. + */ +void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) +{ + uint32_t irq_num; + uint32_t vector = 0; + + if (obj->can == CAN_0) { + vector = (uint32_t)dev_can0_irq_entry; + irq_num = CAN0_IRQ_BASE_NUM; + } + + else if (obj->can == CAN_1) { + vector = (uint32_t)dev_can1_irq_entry; + irq_num = CAN1_IRQ_BASE_NUM; + } + + switch (type) { + case IRQ_RX: + dev_can_interrupt_config(obj->can, CAN_INT_RFNE0, enable); + break; + case IRQ_TX: + dev_can_interrupt_config(obj->can, CAN_INT_TME, enable); + irq_num += 1; + break; + case IRQ_ERROR: + dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_ERRN, enable); + irq_num += 3; + break; + case IRQ_PASSIVE: + dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_PERR, enable); + irq_num += 3; + break; + case IRQ_BUS: + dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_BO, enable); + irq_num += 3; + break; + default: + return; + } + + NVIC_SetVector((IRQn_Type)irq_num, vector); + NVIC_EnableIRQ((IRQn_Type)irq_num); +} + +/** Write a CANMessage to the bus. + * + * @param msg The CANMessage to write. + * + * @returns + * 0 if write failed, + * 1 if write was successful + */ +int can_write(can_t *obj, CAN_Message msg, int cc) +{ + can_trasnmit_message_struct transmit_message; + uint32_t i; + + /* configure frame type: data or remote */ + if (CANData == msg.type) { + transmit_message.tx_ft = CAN_FT_DATA; + } else if (CANRemote == msg.type) { + transmit_message.tx_ft = CAN_FT_REMOTE; + } else { + error("frame type of transmit message is invalid \r\n"); + } + + /* configure frame format: standard or extended */ + if (CANStandard == msg.format) { + transmit_message.tx_ff = CAN_FF_STANDARD; + transmit_message.tx_sfid = msg.id; + } else if (CANExtended == msg.format) { + transmit_message.tx_ff = CAN_FF_EXTENDED; + transmit_message.tx_efid = msg.id; + } else { + error("frame format of transmit message is invalid \r\n"); + } + + transmit_message.tx_dlen = msg.len; + + for (i = 0; i < msg.len; i++) { + transmit_message.tx_data[i] = msg.data[i]; + } + + can_message_transmit(obj->can, &transmit_message); + + return 1; +} + +/** Read a CANMessage from the bus. + * + * @param msg A CANMessage to read to. + * @param handle message filter handle (0 for any message). + * + * @returns + * 0 if no message arrived, + * 1 if message arrived + */ +int can_read(can_t *obj, CAN_Message *msg, int handle) +{ + uint8_t i; + uint8_t fifo_number; + + fifo_number = (uint8_t)handle; + can_receive_message_struct receive_message; + + /* if the frame is not received, retrun 0 */ + if (0 == can_receive_message_length_get(obj->can, CAN_FIFO0)) { + return 0; + } + + can_message_receive(obj->can, fifo_number, &receive_message); + + if (receive_message.rx_ff == CAN_RFIFOMI_FF) { + msg->format = CANExtended; + } else { + msg->format = CANStandard; + } + + if (0 == msg->format) { + msg->id = (uint32_t)0x000007FF & (receive_message.rx_sfid); + } else { + msg->id = (uint32_t)0x1FFFFFFF & (receive_message.rx_efid); + } + + if (receive_message.rx_ft == CAN_RFIFOMI_FT) { + msg->type = CANRemote; + } else { + msg->type = CANData; + } + + msg->len = (uint8_t)receive_message.rx_dlen; + + for (i = 0; i < msg->len; i++) { + msg->data[i] = (uint8_t)receive_message.rx_data[i]; + } + /* If the frame is received successfully, retrun 1 */ + return 1; +} + +/** Reset CAN interface. + * + * To use after error overflow. + */ +void can_reset(can_t *obj) +{ + can_deinit(obj->can); +} + +/** Detects read errors - Used to detect read overflow errors. + * + * @returns number of read errors + */ +unsigned char can_rderror(can_t *obj) +{ + return can_receive_error_number_get(obj->can); +} + +/** Detects write errors - Used to detect write overflow errors. + * + * @returns number of write errors + */ +unsigned char can_tderror(can_t *obj) +{ + return can_transmit_error_number_get(obj->can); +} + +/** Puts or removes the CAN interface into silent monitoring mode. + * + * @param silent boolean indicating whether to go into silent mode or not. + */ +void can_monitor(can_t *obj, int silent) +{ + if (silent) { + dev_can_mode_config(obj->can, CAN_SILENT_MODE); + } else { + dev_can_mode_config(obj->can, CAN_NORMAL_MODE); + } +} + +/** Change CAN operation to the specified mode. + * + * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest). + * + * @returns + * 0 if mode change failed or unsupported, + * 1 if mode change was successful + */ +int can_mode(can_t *obj, CanMode mode) +{ + switch (mode) { + case MODE_NORMAL: + dev_can_mode_config(obj->can, CAN_NORMAL_MODE); + break; + case MODE_SILENT: + dev_can_mode_config(obj->can, CAN_SILENT_MODE); + break; + case MODE_TEST_GLOBAL: + case MODE_TEST_LOCAL: + dev_can_mode_config(obj->can, CAN_LOOPBACK_MODE); + break; + case MODE_TEST_SILENT: + dev_can_mode_config(obj->can, CAN_SILENT_LOOPBACK_MODE); + break; + default: + return 0; + } + + return 1; +} + +/** Filter out incomming messages. + * + * @param id the id to filter on. + * @param mask the mask applied to the id. + * @param format format to filter on (Default CANAny). + * @param handle message filter handle (Optional). + * + * @returns + * 0 if filter change failed or unsupported, + * new filter handle if successful + */ +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ + can_filter_parameter_struct can_filter; + + can_filter.filter_number = handle; + can_filter.filter_mode = CAN_FILTERMODE_MASK; + can_filter.filter_bits = CAN_FILTERBITS_32BIT; + can_filter.filter_fifo_number = CAN_FIFO0; + can_filter.filter_enable = ENABLE; + + switch (format) { + case CANStandard: + /* configure SFID[10:0] */ + can_filter.filter_list_high = id << 5; + can_filter.filter_list_low = 0x0; + /* configure SFID[10:0] mask */ + can_filter.filter_mask_high = mask << 5; + /* both data and remote frames can be received */ + can_filter.filter_mask_low = 0x0; + + break; + + case CANExtended: + /* configure EFID[28:13] */ + can_filter.filter_list_high = id >> 13; + /* configure EFID[12:0] and frame format bit set */ + can_filter.filter_list_low = (0x00FF & (id << 3)) | (1 << 2); + /* configure EFID[28:13] mask */ + can_filter.filter_mask_high = mask >> 13; + /* configure EFID[12:0] and frame format bit mask */ + /* both data and remote frames can be received */ + can_filter.filter_mask_low = (0x00FF & (mask << 3)) | (1 << 2); + + break; + + case CANAny: + error("CANAny mode is not supported \r\n"); + return 0; + + default: + error("parameter is not supported \r\n"); + return 0; + } + + can_filter_init(&can_filter); + can1_filter_start_bank(handle); + + return handle; +} + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/device.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/device.h new file mode 100644 index 00000000000..b542c2bbdde --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/device.h @@ -0,0 +1,25 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library +* Copyright (c) 2006-2018 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif /* MBED_DEVICE_H */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/flash_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/flash_api.c new file mode 100644 index 00000000000..93145eb61ab --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/flash_api.c @@ -0,0 +1,193 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "cmsis.h" + +#define FLASH_SIZE (uint32_t)(FMC_SIZE * 1024) +#define FLASH_BANK0_PAGE_SIZE (0x800) +#define FLASH_BANK1_PAGE_SIZE (0x1000) +#define FLASH_BANK0_END_ADDR (0x0807FFFF) +#define FLASH_BANK1_END_ADDR (0x080FFFFF) +#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE) - 1 +#define WORD_SIZE (4U) + +/* unlock the main FLASH operation + * + * @return 0 for success, -1 for error +*/ +static int32_t flash_unlock(void) +{ + fmc_unlock(); + if (RESET != ((FMC_CTL0 & FMC_CTL0_LK) || (FMC_CTL1 & FMC_CTL1_LK))) { + return -1; + } + return 0; +} + +/* lock the main FLASH operation + * + * @return 0 for success, -1 for error +*/ +static int32_t flash_lock(void) +{ + fmc_lock(); + if (RESET == ((FMC_CTL0 & FMC_CTL0_LK) && (FMC_CTL1 & FMC_CTL1_LK))) { + return -1; + } + return 0; +} + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int32_t flash_state = 0; + flash_unlock(); + + /* clear FLASH flag */ + fmc_flag_clear(FMC_FLAG_BANK0_END); + fmc_flag_clear(FMC_FLAG_BANK0_WPERR); + fmc_flag_clear(FMC_FLAG_BANK0_PGERR); + + /* make sure the address is a right page address */ + if (FMC_READY != fmc_page_erase(address)) { + flash_state = -1; + } + + flash_lock(); + return flash_state; +} + +/** Program pages starting at defined address + * + * The pages should not cross multiple sectors. + * This function does not do any check for address alignments or if size is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + uint32_t *p_data; + p_data = (uint32_t *)data; + uint32_t num = 0; + int32_t flash_state = 0; + flash_unlock(); + + /* clear FLASH flag */ + fmc_flag_clear(FMC_FLAG_BANK0_END); + fmc_flag_clear(FMC_FLAG_BANK0_WPERR); + fmc_flag_clear(FMC_FLAG_BANK0_PGERR); + + if (size % 4) { + num = size / 4 + 1; + } else { + num = size / 4; + } + for (uint32_t i = 0; i < num; i++) { + + if (FMC_READY != fmc_word_program(address, *(p_data + i))) { + flash_state = -1; + break; + } + address += 4; + } + flash_lock(); + return flash_state; +} + +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector + */ +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + uint32_t sector_size = 0; + if ((FLASH_BASE <= address) && (FLASH_BANK0_END_ADDR >= address)) { + sector_size = FLASH_BANK0_PAGE_SIZE; + } else if ((FLASH_BANK0_END_ADDR < address) && (FLASH_END_ADDR >= address)) { + sector_size = FLASH_BANK1_PAGE_SIZE; + } else { + return MBED_FLASH_INVALID_SIZE; + } + return sector_size; +} + +/** Get page size + * + * The page size defines the writable page size + * @param obj The flash object + * @return The size of a page + */ +uint32_t flash_get_page_size(const flash_t *obj) +{ + return WORD_SIZE; +} + +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +#endif /* DEVICE_FLASH */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/gpio_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/gpio_api.c new file mode 100644 index 00000000000..936f0149681 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/gpio_api.c @@ -0,0 +1,149 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gd32f30x_gpio.h" +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +extern const int GD_GPIO_REMAP[]; +extern const int GD_GPIO_SPEED[]; +extern const int GD_GPIO_MODE[]; + +/* Enable GPIO clock and return GPIO base address */ +uint32_t gpio_clock_enable(uint32_t port_idx) +{ + uint32_t gpio_add = 0; + switch (port_idx) { + case PORTA: + gpio_add = GPIOA; + rcu_periph_clock_enable(RCU_GPIOA); + break; + case PORTB: + gpio_add = GPIOB; + rcu_periph_clock_enable(RCU_GPIOB); + break; + case PORTC: + gpio_add = GPIOC; + rcu_periph_clock_enable(RCU_GPIOC); + break; + case PORTD: + gpio_add = GPIOD; + rcu_periph_clock_enable(RCU_GPIOD); + break; + case PORTE: + gpio_add = GPIOE; + rcu_periph_clock_enable(RCU_GPIOE); + break; + default: + error("port number not exist"); + break; + } + return gpio_add; +} + +/** Set the given pin as GPIO + * + * @param pin The pin to be set as GPIO + * @return The GPIO port mask for this pin + */ +uint32_t gpio_set(PinName pin) +{ + + MBED_ASSERT(pin != (PinName)NC); + pin_function(pin, MODE_IN_FLOATING); + /* return pin mask */ + return (uint32_t)(1 << ((uint32_t)pin & 0xF)); +} + +/** Initialize the GPIO pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin to initialize + */ +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + /* fill struct parameter for future use */ + uint32_t port_index = GD_PORT_GET(pin); + uint32_t gpio = gpio_clock_enable(port_index); + obj->mask = gpio_set(pin); + obj->gpio_periph = gpio; +} + +/** Set the input pin mode + * + * @param obj The GPIO object + * @param mode The pin mode to be set + */ +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); +} + +/** Set the output value + * + * @param obj The GPIO object + * @param value The value to be set + */ +void gpio_write(gpio_t *obj, int value) +{ + /* set or reset GPIO pin */ + if (value) { + GPIO_BOP(obj->gpio_periph) = (1 << (uint32_t)GD_PIN_GET(obj->pin)); + } else { + GPIO_BC(obj->gpio_periph) = (1 << (uint32_t)GD_PIN_GET(obj->pin)); + } +} + +/** Read the input value + * + * @param obj The GPIO object + * @return An integer value 1 or 0 + */ +int gpio_read(gpio_t *obj) +{ + /* return state of GPIO pin */ + return ((GPIO_ISTAT(obj->gpio_periph) & obj->mask) ? 1 : 0); +} + +/* Checks if gpio object is connected (pin was not initialized with NC) + * @param pin The pin to be set as GPIO + * @return 0 if port is initialized with NC + **/ +int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +/** Set the pin direction + * + * @param obj The GPIO object + * @param direction The pin direction to be set + */ +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + + /* config GPIO pin as input or output */ + if (direction == PIN_INPUT) { + gpio_para_init(obj->gpio_periph, GD_GPIO_MODE[MODE_IN_FLOATING], GD_GPIO_SPEED[0], (1 << (uint32_t)GD_PIN_GET(obj->pin))); + } else { + gpio_para_init(obj->gpio_periph, GD_GPIO_MODE[MODE_OUT_PP], GD_GPIO_SPEED[0], (1 << (uint32_t)GD_PIN_GET(obj->pin))); + } +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/gpio_irq_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/gpio_irq_api.c new file mode 100644 index 00000000000..ad1061e9f21 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/gpio_irq_api.c @@ -0,0 +1,328 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define EDGE_NONE (0) +#define EDGE_RISE (1) +#define EDGE_FALL (2) + +extern uint32_t gpio_clock_enable(uint32_t port_idx); +static gpio_irq_handler irq_handler; + +typedef struct { + uint32_t exti_idx; + uint32_t exti_gpiox; /* base address of gpio */ + uint32_t exti_pinx; /* pin number */ +} gpio_exti_info_struct; + +/* EXTI0...EXTI15 */ +static gpio_exti_info_struct exti_info_array[16] = {0}; + +/** handle EXTI interrupt in EXTI0 to EXTI15 + + * @param irq_index the line of EXTI(0~15) + */ +static void exti_handle_interrupt(uint32_t irq_index) +{ + gpio_exti_info_struct *gpio_exti = &exti_info_array[irq_index]; + + /* get the port and pin of EXTI */ + uint32_t gpio = (uint32_t)(gpio_exti->exti_gpiox); + uint32_t pin = (uint32_t)(1 << (gpio_exti->exti_pinx)); + + /* clear interrupt flag */ + if (exti_interrupt_flag_get((exti_line_enum)pin) != RESET) { + exti_interrupt_flag_clear((exti_line_enum)pin); + /* check which edge has generated the irq */ + if ((GPIO_ISTAT(gpio) & pin) == 0) { + irq_handler(gpio_exti->exti_idx, IRQ_FALL); + } else { + irq_handler(gpio_exti->exti_idx, IRQ_RISE); + } + } + +} + +/* EXTI0 interrupt handler */ +static void gpio_irq_exti0(void) +{ + exti_handle_interrupt(0); +} +/* EXTI1 interrupt handler */ +static void gpio_irq_exti1(void) +{ + exti_handle_interrupt(1); +} +/* EXTI2 interrupt handler */ +static void gpio_irq_exti2(void) +{ + exti_handle_interrupt(2); +} +/* EXTI3 interrupt handler */ +static void gpio_irq_exti3(void) +{ + exti_handle_interrupt(3); +} +/* EXTI4 interrupt handler */ +static void gpio_irq_exti4(void) +{ + exti_handle_interrupt(4); +} +/* EXTI5 interrupt handler */ +static void gpio_irq_exti5(void) +{ + exti_handle_interrupt(5); +} +/* EXTI6 interrupt handler */ +static void gpio_irq_exti6(void) +{ + exti_handle_interrupt(6); +} +/* EXTI7 interrupt handler */ +static void gpio_irq_exti7(void) +{ + exti_handle_interrupt(7); +} +/* EXTI8 interrupt handler */ +static void gpio_irq_exti8(void) +{ + exti_handle_interrupt(8); +} +/* EXTI9 interrupt handler */ +static void gpio_irq_exti9(void) +{ + exti_handle_interrupt(9); +} +/* EXTI10 interrupt handler */ +static void gpio_irq_exti10(void) +{ + exti_handle_interrupt(10); +} +/* EXTI11 interrupt handler */ +static void gpio_irq_exti11(void) +{ + exti_handle_interrupt(11); +} +/* EXTI12 interrupt handler */ +static void gpio_irq_exti12(void) +{ + exti_handle_interrupt(12); +} +/* EXTI13 interrupt handler */ +static void gpio_irq_exti13(void) +{ + exti_handle_interrupt(13); +} +/* EXTI14 interrupt handler */ +static void gpio_irq_exti14(void) +{ + exti_handle_interrupt(14); +} +/* EXTI15 interrupt handler */ +static void gpio_irq_exti15(void) +{ + exti_handle_interrupt(15); +} + +/** Initialize the GPIO IRQ pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin name + * @param handler The handler to be attached to GPIO IRQ + * @param id The object ID (id != 0, 0 is reserved) + * @return -1 if pin is NC, 0 otherwise + */ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint32_t vector = 0; + gpio_exti_info_struct *gpio_exti; + if (pin == NC) { + return -1; + } + + /* Enable AF Clock */ + rcu_periph_clock_enable(RCU_AF); + + uint32_t port_index = GD_PORT_GET(pin); + uint32_t pin_index = GD_PIN_GET(pin); + /* Enable GPIO clock */ + uint32_t gpio_add = gpio_clock_enable(port_index); + + /* fill EXTI information according to pin_index . + eg. use PORTE_9 as EXTI interrupt, the irq type is EXTI5_9_IRQn */ + if (pin_index == 0) { + vector = (uint32_t)&gpio_irq_exti0; + obj->irq_index = 0; + obj->irq_n = EXTI0_IRQn; + } else if (pin_index == 1) { + vector = (uint32_t)&gpio_irq_exti1; + obj->irq_index = 1; + obj->irq_n = EXTI1_IRQn; + } else if (pin_index == 2) { + vector = (uint32_t)&gpio_irq_exti2; + obj->irq_index = 2; + obj->irq_n = EXTI2_IRQn; + } else if (pin_index == 3) { + vector = (uint32_t)&gpio_irq_exti3; + obj->irq_index = 3; + obj->irq_n = EXTI3_IRQn; + } else if (pin_index == 4) { + vector = (uint32_t)&gpio_irq_exti4; + obj->irq_index = 4; + obj->irq_n = EXTI4_IRQn; + } else if (pin_index == 5) { + vector = (uint32_t)&gpio_irq_exti5; + obj->irq_index = 5; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 6) { + vector = (uint32_t)&gpio_irq_exti6; + obj->irq_index = 6; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 7) { + vector = (uint32_t)&gpio_irq_exti7; + obj->irq_index = 7; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 8) { + vector = (uint32_t)&gpio_irq_exti8; + obj->irq_index = 8; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 9) { + vector = (uint32_t)&gpio_irq_exti9; + obj->irq_index = 9; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 10) { + vector = (uint32_t)&gpio_irq_exti10; + obj->irq_index = 10; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 11) { + vector = (uint32_t)&gpio_irq_exti11; + obj->irq_index = 11; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 12) { + vector = (uint32_t)&gpio_irq_exti12; + obj->irq_index = 12; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 13) { + vector = (uint32_t)&gpio_irq_exti13; + obj->irq_index = 13; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 14) { + vector = (uint32_t)&gpio_irq_exti14; + obj->irq_index = 14; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 15) { + vector = (uint32_t)&gpio_irq_exti15; + obj->irq_index = 15; + obj->irq_n = EXTI10_15_IRQn; + } else { + error("pin not supported for interrupt in.\n"); + return -1; + } + + /* Save informations for future use */ + obj->event = EDGE_NONE; + obj->pin = pin; + + gpio_exti = &exti_info_array[obj->irq_index]; + gpio_exti->exti_idx = id; + gpio_exti->exti_gpiox = gpio_add; + gpio_exti->exti_pinx = pin_index; + + irq_handler = handler; + + /* Enable EXTI interrupt */ + NVIC_SetVector(obj->irq_n, vector); + gpio_irq_enable(obj); + + return 0; +} + +/** Release the GPIO IRQ PIN + * + * @param obj The gpio object + */ +void gpio_irq_free(gpio_irq_t *obj) +{ + gpio_exti_info_struct *gpio_exti = &exti_info_array[obj->irq_index]; + + /* Disable EXTI interrupt */ + gpio_irq_disable(obj); + /* Reset struct of exti information */ + gpio_exti->exti_idx = 0; + gpio_exti->exti_gpiox = 0; + gpio_exti->exti_pinx = 0; +} + +/** Enable/disable pin IRQ event + * + * @param obj The GPIO object + * @param event The GPIO IRQ event + * @param enable The enable flag + */ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + if (event == IRQ_RISE) { + if (enable) { + exti_init((exti_line_enum)(1 << GD_PIN_GET(obj->pin)), EXTI_INTERRUPT, EXTI_TRIG_RISING); + /* Clear interrupt enable bit, rising/falling bit */ + } else { + EXTI_INTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_RTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_FTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + } + } + if (event == IRQ_FALL) { + if (enable) { + exti_init((exti_line_enum)(1 << (GD_PIN_GET(obj->pin))), EXTI_INTERRUPT, EXTI_TRIG_FALLING); + /* Clear interrupt enable bit, rising/falling bit */ + } else { + EXTI_INTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_RTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_FTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + } + } +} + +/** Enable GPIO IRQ + * + * This is target dependent, as it might enable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_enable(gpio_irq_t *obj) +{ + /* Select EXTI Source */ + gpio_exti_source_select(GD_PORT_GET(obj->pin), GD_PIN_GET(obj->pin)); + exti_interrupt_enable((exti_line_enum)(1 << GD_PIN_GET(obj->pin))); + NVIC_EnableIRQ(obj->irq_n); +} + +/** Disable GPIO IRQ + * + * This is target dependent, as it might disable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_disable(gpio_irq_t *obj) +{ + /* Clear EXTI line configuration */ + exti_interrupt_disable((exti_line_enum)(1 << GD_PIN_GET(obj->pin))); + NVIC_DisableIRQ(obj->irq_n); + NVIC_ClearPendingIRQ(obj->irq_n); + obj->event = EDGE_NONE; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/i2c_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/i2c_api.c new file mode 100644 index 00000000000..91a463f11cc --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/i2c_api.c @@ -0,0 +1,653 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#if DEVICE_I2C_ASYNCH +#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) +#else +#define I2C_S(obj) (struct i2c_s *) (obj) +#endif + +#define BUSY_TIMEOUT ((SystemCoreClock / obj_s->freq) * 2 * 10) +#define FLAG_TIMEOUT (0x1000U) + +/** Reset I2C peripheral by hardware method. Most of the implementation enable RCU reset. + * + * @param obj The I2C object + */ +static void i2c_hw_reset(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + switch (obj_s->i2c) { + case I2C_0: + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + + case I2C_1: + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + } +} + +/** Initialize the I2C peripheral. It sets the default parameters for I2C + * peripheral, and configures its specifieds pins. + * + * @param obj The I2C object + * @param sda The sda pin + * @param scl The scl pin + */ +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + struct i2c_s *obj_s = I2C_S(obj); + + /* find the I2C by pins */ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + + obj_s->sda = sda; + obj_s->scl = scl; + obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT(obj_s->i2c != (I2CName)NC); + + switch (obj_s->i2c) { + case I2C_0: + /* enable I2C0 clock and configure the pins of I2C0 */ + obj_s->index = 0; + rcu_periph_clock_enable(RCU_I2C0); + + break; + + case I2C_1: + /* enable I2C1 clock and configure the pins of I2C1 */ + obj_s->index = 1; + rcu_periph_clock_enable(RCU_I2C1); + + break; + + default: + break; + } + + /* configure the pins of I2C */ + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + /* 100 KHz as the default I2C frequence */ + i2c_frequency(obj, 100000); + + obj_s->state = (operation_state_enum)I2C_STATE_NONE; + obj_s->previous_state_mode = I2C_STATE_NONE; + obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; + +#if DEVICE_I2CSLAVE + /* I2C master by default */ + obj_s->slave = 0; +#endif +} + +/** Configure the I2C frequency + * + * @param obj The I2C object + * @param hz Frequency in Hz + */ +void i2c_frequency(i2c_t *obj, int hz) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = BUSY_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) && (--timeout != 0)); + + /* reset to clear pending flags */ + i2c_hw_reset(obj); + + /* disable I2C peripheral */ + i2c_disable(obj_s->i2c); + + /* configure I2C frequence */ + i2c_clock_config(obj_s->i2c, hz, I2C_DTCY_2); + + /* configure I2C address mode and slave address */ + i2c_mode_addr_config(obj_s->i2c, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0); + + /* enable I2C peripheral */ + i2c_enable(obj_s->i2c); +} + +/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop() + * + * @param obj The I2C object + */ +void i2c_reset(i2c_t *obj) +{ + i2c_stop(obj); +} + +/** Send START command + * + * @param obj The I2C object + */ +int i2c_start(i2c_t *obj) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + /* clear I2C_FLAG_AERR Flag */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_AERR); + + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { + if ((timeout--) == 0) { + return (int)GD_BUSY; + } + } + + /* ensure the i2c has been stopped */ + timeout = FLAG_TIMEOUT; + while ((I2C_CTL0(obj_s->i2c) & I2C_CTL0_STOP) == I2C_CTL0_STOP) { + if ((timeout--) == 0) { + return (int)GD_ERROR; + } + } + + /* generate a START condition */ + i2c_start_on_bus(obj_s->i2c); + + /* ensure the i2c has been started successfully */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { + if ((timeout--) == 0) { + return (int)GD_ERROR; + } + } + + return (int)GD_OK; +} + +/** Send STOP command + * + * @param obj The I2C object + */ +int i2c_stop(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + /* generate a STOP condition */ + i2c_stop_on_bus(obj_s->i2c); + + /* wait for STOP bit reset */ + while ((I2C_CTL0(obj_s->i2c) & I2C_CTL0_STOP)); + + return 0; +} + +/** Read one byte + * + * @param obj The I2C object + * @param last Acknoledge + * @return The read byte + */ +int i2c_byte_read(i2c_t *obj, int last) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + if (last) { + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + } else { + /* enable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + } + + /* wait until the byte is received */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)) == RESET) { + if ((timeout--) == 0) { + return -1; + } + } + + return (int)I2C_DATA(obj_s->i2c); +} + +/** Write one byte + * + * @param obj The I2C object + * @param data Byte to be written + * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout. + */ +int i2c_byte_write(i2c_t *obj, int data) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + I2C_DATA(obj_s->i2c) = (uint8_t)data; + + /* wait until the byte is transmitted */ + timeout = FLAG_TIMEOUT; + while (((i2c_flag_get(obj_s->i2c, I2C_FLAG_TBE)) == RESET) && + ((i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)) == RESET)) { + if ((timeout--) == 0) { + return 2; + } + } + + return 1; +} + +/** Blocking reading data + * + * @param obj The I2C object + * @param address 7-bit address (last bit is 1) + * @param data The buffer for receiving + * @param length Number of bytes to read + * @param stop Stop to be generated after the transfer is done + * @return Number of read bytes + */ +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + struct i2c_s *obj_s = I2C_S(obj); + uint32_t count = 0U; + int timeout = 0; + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || + obj_s->global_trans_option == I2C_LAST_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_FIRST_FRAME; + } + } else if (obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->global_trans_option == I2C_NEXT_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_NEXT_FRAME; + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME) { + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->previous_state_mode != I2C_STATE_MASTER_BUSY_RX) { + /* generate a START condition */ + i2c_start_on_bus(obj_s->i2c); + + /* ensure the i2c has been started successfully */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + + /* send slave address */ + i2c_master_addressing(obj_s->i2c, address, I2C_RECEIVER); + + if (1 == length) { + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + /* send a stop condition to I2C bus*/ + } else if (2 == length) { + /* send a NACK for the next data byte which will be received into the shift register */ + i2c_ackpos_config(obj_s->i2c, I2C_ACKPOS_NEXT); + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + } else { + /* enable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + } + + /* wait until I2C_FLAG_ADDSEND flag is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + } + + /* clear ADDSEND */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + } + + obj_s->state = (operation_state_enum)I2C_STATE_MASTER_BUSY_RX; + + for (count = 0; count < length; count++) { + if (length > 2 && count == length - 3) { + while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)); + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + } else if (2 == length && count == 0) { + while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)); + } + + while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)); + data[count] = i2c_data_receive(obj_s->i2c); + } + + obj_s->previous_state_mode = obj_s->state; + + /* if not sequential read, then send stop */ + if (stop) { + i2c_stop(obj); + } + + return count; +} + +/** Blocking sending data + * + * @param obj The I2C object + * @param address 7-bit address (last bit is 0) + * @param data The buffer for sending + * @param length Number of bytes to write + * @param stop Stop to be generated after the transfer is done + * @return + * zero or non-zero - Number of written bytes + * negative - I2C_ERROR_XXX status + */ +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + struct i2c_s *obj_s = I2C_S(obj); + gd_status_enum status = GD_OK; + uint32_t count = 0; + int timeout = 0; + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || + obj_s->global_trans_option == I2C_LAST_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_FIRST_FRAME; + } + } else if (obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->global_trans_option == I2C_NEXT_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_NEXT_FRAME; + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME) { + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->previous_state_mode != I2C_STATE_MASTER_BUSY_TX) { + /* generate a START condition */ + i2c_start_on_bus(obj_s->i2c); + + /* ensure the i2c has been started successfully */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + + /* send slave address */ + i2c_master_addressing(obj_s->i2c, address, I2C_TRANSMITTER); + + /* wait until I2C_FLAG_ADDSEND flag is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + } + + /* clear ADDSEND */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + } + + obj_s->state = (operation_state_enum)I2C_STATE_MASTER_BUSY_TX; + + for (count = 0; count < length; count++) { + status = (gd_status_enum)i2c_byte_write(obj, data[count]); + if (status != 1) { + i2c_stop(obj); + return count; + } + } + + obj_s->previous_state_mode = obj_s->state; + + /* if not sequential write, then send stop */ + if (stop) { + i2c_stop(obj); + } + + return count; +} + +#if DEVICE_I2CSLAVE + +/** Configure I2C address. + * @param obj The I2C object + * @param idx Currently not used + * @param address The address to be set + * @param mask Currently not used + */ +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + struct i2c_s *obj_s = I2C_S(obj); + + /* disable I2C peripheral */ + i2c_disable(obj_s->i2c); + /* I2C clock configure */ + i2c_clock_config(obj_s->i2c, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(obj_s->i2c, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, address); + /* enable I2C0 */ + i2c_enable(obj_s->i2c); + /* enable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive + * @return non-zero if a value is available + */ +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + struct i2c_s *obj_s = I2C_S(obj); + + if (enable_slave) { + obj_s->slave = 1; + } else { + obj_s->slave = 0; + } +} + +/* the same as the definition in I2CSlave.h class I2CSlave */ +#define NoData 0 /* the slave has not been addressed */ +#define ReadAddressed 1 /* the master has requested a read from this slave (slave as transmitter) */ +#define WriteGeneral 2 /* the master is writing to all slave */ +#define WriteAddressed 3 /* the master is writing to this slave (slave as receiver) */ + +/** Check to see if the I2C slave has been addressed. + * @param obj The I2C object + * @return The status - 1 - read addresses, 2 - write to all slaves, + * 3 write addressed, 0 - the slave has not been addressed + */ +int i2c_slave_receive(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + int ret = NoData; + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + + if (i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + if (i2c_flag_get(obj_s->i2c, I2C_FLAG_RXGC)) { + ret = WriteGeneral; + } + + if (i2c_flag_get(obj_s->i2c, I2C_FLAG_TRS)) { + ret = ReadAddressed; + } else { + ret = WriteAddressed; + } + } + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + + return (ret); +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param data The buffer for receiving + * @param length Number of bytes to read + * @return non-zero if a value is available + */ +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + struct i2c_s *obj_s = I2C_S(obj); + int count = 0; + int timeout = 0; + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + + /* wait until ADDSEND bit is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + /* clear ADDSEND bit */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + + while (0 < length) { + /* wait until the RBNE bit is set */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + *data = i2c_data_receive(obj_s->i2c); + data++; + length--; + count++; + } + /* wait until the STPDET bit is set */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_STPDET)) { + timeout++; + if (timeout > 100) { + return count; + } + } + /* clear the STPDET bit */ + i2c_enable(obj_s->i2c); + + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + + return count; +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param data The buffer for sending + * @param length Number of bytes to write + * @return non-zero if a value is available + */ +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + struct i2c_s *obj_s = I2C_S(obj); + int count = 0; + int timeout = 0; + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + /* wait until ADDSEND bit is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + /* clear ADDSEND bit */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + while (length > 0) { + /* wait until the TBE bit is set */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_TBE)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + i2c_data_transmit(obj_s->i2c, *data); + data++; + length--; + count++; + } + /* the master doesn't acknowledge for the last byte */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_AERR)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + /* clear the bit of AERR */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_AERR); + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + + return count; +} +#endif /* DEVICE_I2CSLAVE */ + +#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/mbed_overrides.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/mbed_overrides.c new file mode 100644 index 00000000000..84f0022a8f0 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/mbed_overrides.c @@ -0,0 +1,154 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gd32f30x.h" +#include "cmsis.h" +#include "hal_tick.h" + +int mbed_sdk_inited = 0; + +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +#if TICKER_TIMER_WIDTH_BIT == 16 +extern void ticker_16bits_timer_init(void); +#else +extern void ticker_32bits_timer_init(void); +#endif + +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while (1) { + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while (0U == (PMU_CS & PMU_CS_HDRF)) { + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while (0U == (PMU_CS & PMU_CS_HDSRF)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +/** + * SDK hook for running code before ctors or OS + * + * This is a weak function which can be overridden by a target's + * SDK to allow code to run after ram is initialized but before + * the OS has been started or constructors have run. + * + * Preconditions: + * - Ram is initialized + * - NVIC is setup + */ +/** + * This function is called after RAM initialization and before main. + */ +void mbed_sdk_init() +{ + /* Update the SystemCoreClock */ + SystemCoreClockUpdate(); + nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0); + + /* configure 1ms tick */ +#if TICKER_TIMER_WIDTH_BIT == 16 + ticker_16bits_timer_init(); +#else + ticker_32bits_timer_init(); +#endif + + system_clock_120m_hxtal(); + + SystemCoreClockUpdate(); + + mbed_sdk_inited = 1; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/objects.h b/targets/TARGET_Gigadevice/TARGET_GD32F30X/objects.h new file mode 100644 index 00000000000..c585d24b453 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/objects.h @@ -0,0 +1,181 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct gpio_s gpio_t; + +struct gpio_s { + uint32_t mask; + PinName pin; + __IO uint32_t gpio_periph; +}; + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +#if DEVICE_ANALOGOUT +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; +#endif + +struct can_s { + CANName can; + int index; +}; + +struct pwmout_s { + PWMName pwm; + uint32_t cnt_unit; + uint8_t ch; +}; + +struct serial_s { + /* basic information */ + UARTName uart; + int index; + PinName pin_tx; + PinName pin_rx; + + /* configure information */ + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + + /* operating parameters */ + uint16_t rx_size; + uint8_t *tx_buffer_ptr; + uint8_t *rx_buffer_ptr; + __IO uint16_t tx_count; + __IO uint16_t rx_count; + + __IO uint32_t error_code; + __IO operation_state_enum tx_state; + __IO operation_state_enum rx_state; + +#if DEVICE_SERIAL_ASYNCH + uint32_t events; +#endif +#if DEVICE_SERIAL_FC + uint32_t hw_flow_ctl; + PinName pin_rts; + PinName pin_cts; +#endif +}; + +struct spi_s { + spi_parameter_struct spi_struct; + IRQn_Type spi_irq; + SPIName spi; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + /* basic information */ + I2CName i2c; + uint8_t index; + PinName sda; + PinName scl; + int i2c_inited; /* flag used to indicate whether the i2c has been initialized */ + + /* configure information */ + int freq; /* i2c frequence */ + uint32_t addr_bit_mode; /* 7 bits or 10 bits */ + uint32_t slave_addr0; + uint32_t slave_addr1; + uint16_t transfer_size; + uint8_t *buffer_pointer; + + /* operating parameters */ + __IO operation_state_enum state; + __IO i2c_mode_enum mode; + __IO uint32_t previous_state_mode; + __IO uint32_t i2c_target_dev_addr; + __IO uint32_t event_count; + __IO uint32_t transfer_count; + __IO uint32_t transfer_option; + __IO uint32_t error_code; + + /* I2C DMA information */ + uint32_t tx_dma_periph; + dma_channel_enum tx_dma_channel; + uint32_t rx_dma_periph; + dma_channel_enum rx_dma_channel; + + IRQn_Type event_i2cIRQ; + IRQn_Type error_i2cIRQ; + uint32_t global_trans_option; + volatile uint8_t event; + +#if DEVICE_I2CSLAVE + uint8_t slave; + volatile uint8_t pending_slave_tx_master_rx; + volatile uint8_t pending_slave_rx_maxter_tx; +#endif + +#if DEVICE_I2C_ASYNCH + uint32_t address; + uint8_t stop; + uint8_t available_events; +#endif + +}; +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/pinmap.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/pinmap.c new file mode 100644 index 00000000000..2b38f4fe7f2 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/pinmap.c @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" +#include "mbed_error.h" + +extern uint32_t gpio_clock_enable(uint32_t port_idx); + +extern const int GD_GPIO_REMAP[]; +extern const int GD_GPIO_MODE[]; +extern const int GD_GPIO_SPEED[]; + +static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin); + +/** Configure pin (mode, speed, reamp function ) + * + * @param pin gpio pin name + * @param function gpio pin mode, speed, remap function + */ +void pin_function(PinName pin, int function) +{ + MBED_ASSERT(pin != (PinName)NC); + + uint32_t mode = GD_PIN_MODE_GET(function); + uint32_t remap = GD_PIN_REMAP_GET(function); + uint32_t speed = GD_PIN_SPEED_GET(function); + uint32_t port = GD_PORT_GET(pin); + uint32_t gd_pin = 1 << GD_PIN_GET(pin); + + uint32_t gpio = gpio_clock_enable(port); + gpio_para_init(gpio, GD_GPIO_MODE[mode], GD_GPIO_SPEED[speed], gd_pin); + + if (remap != 0) { + rcu_periph_clock_enable(RCU_AF); + gpio_pin_remap_config(GD_GPIO_REMAP[remap], ENABLE); + } +} + +/** Only configure pin mode + * + * @param pin gpio pin name + * @param function gpio pin mode + */ +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t port = GD_PORT_GET(pin); + uint32_t gd_pin = 1 << GD_PIN_GET(pin); + + uint32_t gpio = gpio_clock_enable(port); + if (mode != PullNone) { + gpio_mode_set(gpio, GD_GPIO_MODE[mode], gd_pin); + } +} + +/** configure gpio pin mode + * + * @param gpio_periph gpio port name + * @param mode gpio pin mode + * @param pin gpio pin number + */ +static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin) +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); + + /* configure the eight low port pins with GPIO_CTL0 */ + for (i = 0U; i < 8U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL0(gpio_periph); + + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for (i = 8U; i < 16U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL1(gpio_periph); + + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + + diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/port_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/port_api.c new file mode 100644 index 00000000000..b52dbbf4932 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/port_api.c @@ -0,0 +1,118 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +extern uint32_t gpio_clock_enable(uint32_t port_idx); + +/** Get the pin name from the port's pin number + * + * @param port The port name + * @param pin_n The pin number within the specified port + * @return The pin name for the port's pin number + * BIT[7:4] port number + BIT[3:0] pin number + */ +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)(pin_n + (port << 4)); +} + +/** Initilize the port + * + * @param obj The port object to initialize + * @param port The port name + * @param mask The bitmask to identify which bits in the port should be included (0 - ignore) + * @param dir The port direction + */ +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint32_t port_index = (uint32_t)port; + uint32_t gpio = gpio_clock_enable(port_index); + + obj->port = port; + obj->mask = mask; + obj->direction = dir; + obj->reg_in = &GPIO_ISTAT(gpio); + obj->reg_out = &GPIO_OCTL(gpio); + + port_dir(obj, dir); +} + +/** Set port direction (in/out) + * + * @param obj The port object + * @param dir The port direction to be set + */ +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < 16; i++) { + if (obj->mask & (1 << i)) { + if (dir == PIN_OUTPUT) { + pin_function(port_pin(obj->port, i), MODE_OUT_PP); + } else { + pin_function(port_pin(obj->port, i), MODE_IN_FLOATING); + } + } + } +} + +/** Set the input port mode + * + * @param obj The port object + * @param mode THe port mode to be set + */ +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + for (i = 0; i < 16; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +/** Write value to the port + * + * @param obj The port object + * @param value The value to be set + */ +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +/** Read the current value on the port + * + * @param obj The port object + * @return An integer with each bit corresponding to an associated port pin setting + */ +int port_read(port_t *obj) +{ + if (obj->direction == PIN_OUTPUT) { + return (*obj->reg_out & obj->mask); + } else { + return (*obj->reg_in & obj->mask); + } +} + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/pwmout_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/pwmout_api.c new file mode 100644 index 00000000000..0a19aeb5971 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/pwmout_api.c @@ -0,0 +1,297 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +#define DEV_PWMOUT_APB_MASK 0x00010000U +#define DEV_PWMOUT_APB1 0U +#define DEV_PWMOUT_APB2 1U + +static uint32_t timer_get_clock(uint32_t timer_periph); + +static void dev_pwmout_init(pwmout_t *obj) +{ + timer_oc_parameter_struct timer_ocintpara; + timer_parameter_struct timer_initpara; + + MBED_ASSERT(obj); + uint32_t periph = obj->pwm; + + switch (periph) { + case TIMER0: + rcu_periph_clock_enable(RCU_TIMER0); + break; + + case TIMER1: + rcu_periph_clock_enable(RCU_TIMER1); + break; + + case TIMER2: + rcu_periph_clock_enable(RCU_TIMER2); + break; + + case TIMER3: + rcu_periph_clock_enable(RCU_TIMER3); + break; + + case TIMER4: + rcu_periph_clock_enable(RCU_TIMER4); + break; + + case TIMER7: + rcu_periph_clock_enable(RCU_TIMER7); + break; + case TIMER8: + rcu_periph_clock_enable(RCU_TIMER8); + break; + + case TIMER9: + rcu_periph_clock_enable(RCU_TIMER9); + break; + + case TIMER10: + rcu_periph_clock_enable(RCU_TIMER10); + break; + + case TIMER11: + rcu_periph_clock_enable(RCU_TIMER11); + break; + + case TIMER12: + rcu_periph_clock_enable(RCU_TIMER12); + break; + + case TIMER13: + rcu_periph_clock_enable(RCU_TIMER13); + break; + } + /* configure TIMER base function */ + timer_initpara.prescaler = 119; + timer_initpara.period = 9999; + timer_initpara.clockdivision = 0; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + + timer_init(obj->pwm, &timer_initpara); + + /* configure TIMER channel output function */ + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_ocintpara.outputnstate = TIMER_CCXN_ENABLE; + timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH; + timer_channel_output_config(obj->pwm, obj->ch, &timer_ocintpara); + timer_channel_output_mode_config(obj->pwm, obj->ch, TIMER_OC_MODE_PWM0); + timer_channel_output_fast_config(obj->pwm, obj->ch, TIMER_OC_FAST_DISABLE); + + timer_primary_output_config(obj->pwm, ENABLE); +} + +static uint8_t dev_pwmout_apb_check(uint32_t periph) +{ + uint8_t reval = DEV_PWMOUT_APB1; + + /* check peripherals belongs to APB1 or APB2 */ + if (DEV_PWMOUT_APB_MASK == (periph & DEV_PWMOUT_APB_MASK)) { + reval = DEV_PWMOUT_APB2; + } + + return reval; +} + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + + obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(obj->pwm != (PWMName)NC); + + uint32_t function = pinmap_function(pin, PinMap_PWM); + MBED_ASSERT(function != (uint32_t)NC); + obj->ch = GD_PIN_CHANNEL_GET(function); + /* Peripheral initialization */ + dev_pwmout_init(obj); + /* pin function initialization */ + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t *obj) +{ + timer_channel_output_state_config(obj->pwm, obj->ch, TIMER_CCX_DISABLE); +} + +void pwmout_write(pwmout_t *obj, float value) +{ + uint16_t period; + uint16_t pulse; + + timer_disable(obj->pwm); + /* overflow protection */ + if (value < (float)0.0) { + value = 0.0; + } else if (value > (float)1.0) { + value = 1.0; + } + + period = TIMER_CAR(obj->pwm); + pulse = (uint16_t)(period * value); + + timer_channel_output_pulse_value_config(obj->pwm, obj->ch, pulse); + + timer_enable(obj->pwm); +} + +float pwmout_read(pwmout_t *obj) +{ + float value = 0; + uint16_t period; + uint16_t pulse; + + period = TIMER_CAR(obj->pwm); + + switch (obj->ch) { + case TIMER_CH_0: + pulse = TIMER_CH0CV(obj->pwm); + break; + + case TIMER_CH_1: + pulse = TIMER_CH1CV(obj->pwm); + break; + + case TIMER_CH_2: + pulse = TIMER_CH2CV(obj->pwm); + break; + + case TIMER_CH_3: + pulse = TIMER_CH3CV(obj->pwm); + break; + + default: + error("Error: pwm channel error! \r\n"); + } + + /* calculated waveform duty ratio */ + value = (float)(pulse) / (float)(period); + + if (value > (float)1.0) { + value = (float)1.0; + } + + return value; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +void pwmout_period_us(pwmout_t *obj, int us) +{ + + uint32_t ultemp = 0; + uint32_t timer_clk = 0; + uint32_t period = us - 1; + uint32_t prescaler; + float duty_ratio; + + duty_ratio = pwmout_read(obj); + + timer_disable(obj->pwm); + + timer_clk = timer_get_clock(obj->pwm); + + ultemp = (timer_clk / 1000000); + prescaler = ultemp; + obj->cnt_unit = 1; + + while (period > 0xFFFF) { + obj->cnt_unit = obj->cnt_unit << 1; + period = period >> 1; + prescaler = ultemp * obj->cnt_unit; + } + + if (prescaler > 0xFFFF) { + error("Error: TIMER prescaler value is overflow \r\n"); + } + + timer_autoreload_value_config(obj->pwm, period); + timer_prescaler_config(obj->pwm, prescaler - 1, TIMER_PSC_RELOAD_NOW); + + ultemp = duty_ratio * us; + + pwmout_pulsewidth_us(obj, ultemp); + + timer_enable(obj->pwm); +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + uint32_t pulse; + uint32_t period; + + period = TIMER_CAR(obj->pwm); + pulse = us / obj->cnt_unit; + + if (pulse > period) { + pulse = period; + } + + timer_channel_output_pulse_value_config(obj->pwm, obj->ch, pulse); +} + +static uint32_t timer_get_clock(uint32_t timer_periph) +{ + uint32_t timerclk; + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || (TIMER10 == timer_periph)) { + /* get the current APB2 TIMER clock source */ + if (RCU_APB2_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB2PSC)) { + timerclk = rcu_clock_freq_get(CK_APB2); + } else { + timerclk = rcu_clock_freq_get(CK_APB2) * 2; + } + } else { + /* get the current APB1 TIMER clock source */ + if (RCU_APB1_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB1PSC)) { + timerclk = rcu_clock_freq_get(CK_APB1); + } else { + timerclk = rcu_clock_freq_get(CK_APB1) * 2; + } + } + + return timerclk; +} diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/rtc_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/rtc_api.c new file mode 100644 index 00000000000..6c4df63f7d5 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/rtc_api.c @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_RTC + +#include "rtc_api.h" + +static uint8_t rtc_init_flag = 0; + +/** Initialize the RTC peripheral + * + * Powerup the RTC in perpetration for access. This function must be called + * before any other RTC functions ares called. This does not change the state + * of the RTC. It just enables access to it. + * + * @note This function is safe to call repeatedly - Tested by ::rtc_init_test + */ +void rtc_init(void) +{ + /* make sure RTC only init once */ + if (rtc_init_flag) { + return; + } + rtc_init_flag = 1; + + /* enable PMU and BKPI clocks */ + rcu_periph_clock_enable(RCU_BKPI); + rcu_periph_clock_enable(RCU_PMU); + /* allow access to BKP domain */ + pmu_backup_write_enable(); + /* enable LXTAL */ + rcu_osci_on(RCU_LXTAL); + /* wait till LXTAL is ready */ + rcu_osci_stab_wait(RCU_LXTAL); + /* select RCU_LXTAL as RTC clock source */ + rcu_rtc_clock_config(RCU_RTCSRC_LXTAL); + /* enable RTC Clock */ + rcu_periph_clock_enable(RCU_RTC); + /* wait for RTC registers synchronization */ + rtc_register_sync_wait(); + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + /* set RTC prescaler: set RTC period to 1s */ + rtc_prescaler_set(32767); + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); +} + +/** Deinitialize RTC + * + * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only + * affect the CPU domain and not the time keeping logic. + * After this function is called no other RTC functions should be called + * except for ::rtc_init. + */ +void rtc_free(void) +{ +} + +/** Check if the RTC has the time set and is counting + * + * @retval 0 The time reported by the RTC is not valid + * @retval 1 The time has been set the RTC is counting + */ +int rtc_isenabled(void) +{ + if (RESET == (RTC_CTL & RTC_CTL_RSYNF)) { + return 0; + } else { + return 1; + } +} + +/** Get the current time from the RTC peripheral + * + * @return The current time in seconds + * + * @note Some RTCs are not synchronized with the main clock. If + * this is the case with your RTC then you must read the RTC time + * in a loop to prevent reading the wrong time due to a glitch. + * The test ::rtc_glitch_test is intended to catch this bug. + */ +time_t rtc_read(void) +{ + return (rtc_counter_get()); +} + +/** Write the current time in seconds to the RTC peripheral + * + * @param t The current time to be set in seconds. + */ +void rtc_write(time_t t) +{ + rtc_counter_set((uint32_t)t); + rtc_lwoff_wait(); +} + +#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/serial_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/serial_api.c new file mode 100644 index 00000000000..376f08bac41 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/serial_api.c @@ -0,0 +1,1078 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include +#include "PeripheralPins.h" + +#define USART_NUM (5) + +static uint32_t serial_irq_ids[USART_NUM] = {0}; +static rcu_periph_enum usart_clk[USART_NUM] = {RCU_USART0, RCU_USART1, RCU_USART2, RCU_UART3, RCU_UART4}; +static IRQn_Type usart_irq_n[USART_NUM] = {USART0_IRQn, USART1_IRQn, USART2_IRQn, UART3_IRQn, UART4_IRQn}; + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +#if DEVICE_SERIAL_ASYNCH +#define GET_SERIAL_S(obj) (&((obj)->serial)) +#else +#define GET_SERIAL_S(obj) (obj) +#endif /* DEVICE_SERIAL_ASYNCH */ + +/** Initialize the USART peripheral. + * + * @param obj_s The serial object + */ +static void usart_init(struct serial_s *obj_s) +{ + if (obj_s->index >= USART_NUM) { + return; + } + + /* USART configuration */ + usart_deinit(obj_s->uart); + usart_word_length_set(obj_s->uart, obj_s->databits); + usart_baudrate_set(obj_s->uart, obj_s->baudrate); + usart_stop_bit_set(obj_s->uart, obj_s->stopbits); + usart_parity_config(obj_s->uart, obj_s->parity); +#if DEVICE_SERIAL_FC + if (obj_s->hw_flow_ctl == USART_HWCONTROL_NONE) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_DISABLE); + } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_RTS) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_ENABLE); + } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_CTS) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_ENABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_DISABLE); + } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_RTS_CTS) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_ENABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_ENABLE); + } +#endif /* DEVICE_SERIAL_FC */ + usart_receive_config(obj_s->uart, USART_RECEIVE_ENABLE); + usart_transmit_config(obj_s->uart, USART_TRANSMIT_ENABLE); + usart_enable(obj_s->uart); +} + +/** Initialize the serial peripheral. It sets the default parameters for serial + * peripheral, and configures its specifieds pins. + * + * @param obj The serial object + * @param tx The TX pin name + * @param rx The RX pin name + */ +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + p_obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT(p_obj->uart != (UARTName)NC); + + /* enable UART peripheral clock */ + if (p_obj->uart == UART_0) { + p_obj->index = 0; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_1) { + p_obj->index = 1; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_2) { + p_obj->index = 2; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_3) { + p_obj->index = 3; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_4) { + p_obj->index = 4; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } + + /* configurte the pins */ + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + /* default UART parameters */ + p_obj->baudrate = 9600U; + p_obj->databits = USART_WL_8BIT; + p_obj->stopbits = USART_STB_1BIT; + p_obj->parity = USART_PM_NONE; + +#if DEVICE_SERIAL_FC + p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; +#endif /* DEVICE_SERIAL_FC */ + + p_obj->pin_tx = tx; + p_obj->pin_rx = rx; + + p_obj->tx_state = OP_STATE_BUSY; + p_obj->rx_state = OP_STATE_BUSY; + + usart_init(p_obj); + + p_obj->tx_state = OP_STATE_READY; + p_obj->rx_state = OP_STATE_READY; + + if (p_obj->uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +/** Release the serial peripheral, not currently invoked. It requires further + * resource management. + * + * @param obj The serial object + */ +void serial_free(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + rcu_periph_enum rcu_periph = usart_clk[p_obj->index]; + + /* reset USART and disable clock */ + usart_deinit(p_obj->uart); + rcu_periph_clock_disable(rcu_periph); + + serial_irq_ids[p_obj->index] = 0; + + /* reset the GPIO state */ + pin_function(p_obj->pin_tx, MODE_IN_FLOATING); + pin_function(p_obj->pin_rx, MODE_IN_FLOATING); +} + +/** Configure the baud rate + * + * @param obj The serial object + * @param baudrate The baud rate to be configured + */ +void serial_baud(serial_t *obj, int baudrate) +{ + uint16_t uen_flag = 0U; + struct serial_s *p_obj = GET_SERIAL_S(obj); + + /* store the UEN flag */ + uen_flag = USART_CTL0(USART0) & USART_CTL0_UEN; + + /* disable the USART clock first */ + usart_disable(p_obj->uart); + + usart_baudrate_set(p_obj->uart, baudrate); + + p_obj->baudrate = baudrate; + + /* restore the UEN flag */ + if (RESET != uen_flag) { + usart_enable(p_obj->uart); + } +} + +/** Configure the format. Set the number of bits, parity and the number of stop bits + * + * @param obj The serial object + * @param data_bits The number of data bits + * @param parity The parity + * @param stop_bits The number of stop bits + */ +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint16_t uen_flag = 0U; + struct serial_s *p_obj = GET_SERIAL_S(obj); + + /* store the UEN flag */ + uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; + + /* disable the UART clock first */ + usart_disable(p_obj->uart); + + /* configurate the UART parity */ + switch (parity) { + case ParityOdd: + p_obj->parity = USART_PM_ODD; + usart_parity_config(p_obj->uart, USART_PM_ODD); + break; + + case ParityEven: + p_obj->parity = USART_PM_EVEN; + usart_parity_config(p_obj->uart, USART_PM_EVEN); + break; + + case ParityForced0: + case ParityForced1: + default: + p_obj->parity = USART_PM_NONE; + usart_parity_config(p_obj->uart, USART_PM_NONE); + break; + } + + if (p_obj->parity == USART_PM_NONE) { + if (data_bits == 9) { + usart_word_length_set(p_obj->uart, USART_WL_9BIT); + } else if (data_bits == 8) { + usart_word_length_set(p_obj->uart, USART_WL_8BIT); + } else if (data_bits == 7) { + return; + } + } else { + if (data_bits == 9) { + return; + } else if (data_bits == 8) { + usart_word_length_set(p_obj->uart, USART_WL_9BIT); + } else if (data_bits == 7) { + usart_word_length_set(p_obj->uart, USART_WL_8BIT); + } + } + + if (stop_bits == 2) { + usart_stop_bit_set(p_obj->uart, USART_STB_2BIT); + } else { + usart_stop_bit_set(p_obj->uart, USART_STB_1BIT); + } + + /* restore the UEN flag */ + if (RESET != uen_flag) { + usart_enable(p_obj->uart); + } +} + +/** The serial interrupt handler registration + * + * @param obj The serial object + * @param handler The interrupt handler which will be invoked when the interrupt fires + * @param id The SerialBase object + */ +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + irq_handler = handler; + serial_irq_ids[p_obj->index] = id; +} + +/** This function handles USART interrupt handler + * + * @param usart_index The index of UART + * @param usart_periph The UART peripheral + */ +static void usart_irq(int usart_index, uint32_t usart_periph) +{ + if (serial_irq_ids[usart_index] != 0) { + if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_TC) != RESET) { + usart_interrupt_flag_clear(usart_periph, USART_FLAG_TC); + irq_handler(serial_irq_ids[usart_index], TxIrq); + } + + if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_RBNE) != RESET) { + usart_interrupt_flag_clear(usart_periph, USART_FLAG_RBNE); + irq_handler(serial_irq_ids[usart_index], RxIrq); + } + + if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_ORERR) != RESET) { + usart_interrupt_flag_clear(usart_periph, USART_FLAG_ORERR); + } + } +} + +/** This function handles USART0 interrupt handler + * + */ +static void usart0_irq(void) +{ + usart_irq(0, USART0); +} + +/** This function handles USART1 interrupt handler + * + */ +static void usart1_irq(void) +{ + usart_irq(1, USART1); +} + +/** This function handles USART2 interrupt handler + * + */ +static void usart2_irq(void) +{ + usart_irq(2, USART2); +} + +/** This function handles USART3 interrupt handler + * + */ +static void uart3_irq(void) +{ + usart_irq(3, UART3); +} + +/** This function handles USART4 interrupt handler + * + */ +static void uart4_irq(void) +{ + usart_irq(4, UART4); +} + +/** Configure serial interrupt. This function is used for word-approach + * + * @param obj The serial object + * @param irq The serial IRQ type (RX or TX) + * @param enable Set to non-zero to enable events, or zero to disable them + */ +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + + if (p_obj->uart == USART0) { + irq_n = USART0_IRQn; + vector = (uint32_t)&usart0_irq; + } else if (p_obj->uart == USART1) { + irq_n = USART1_IRQn; + vector = (uint32_t)&usart1_irq; + } else if (p_obj->uart == USART2) { + irq_n = USART2_IRQn; + vector = (uint32_t)&usart2_irq; + } else if (p_obj->uart == UART3) { + irq_n = UART3_IRQn; + vector = (uint32_t)&uart3_irq; + } else if (p_obj->uart == UART4) { + irq_n = UART4_IRQn; + vector = (uint32_t)&uart4_irq; + } + + if (enable) { + if (irq == RxIrq) { + /* Rx IRQ */ + usart_interrupt_enable(p_obj->uart, USART_INT_RBNE); + } else { + /* Tx IRQ */ + usart_interrupt_enable(p_obj->uart, USART_INT_TBE); + } + + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { + if (irq == RxIrq) { + /* Rx IRQ */ + usart_interrupt_disable(p_obj->uart, USART_INT_RBNE); + } else { + /* Tx IRQ */ + usart_interrupt_disable(p_obj->uart, USART_INT_TBE); + } + } +} + +/** Get character. This is a blocking call, waiting for a character + * + * @param obj The serial object + */ +int serial_getc(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + while (!serial_readable(obj)); + return (int)(usart_data_receive(p_obj->uart) & BITS(0, 7 + (p_obj->databits >> 12))); +} + +/** Send a character. This is a blocking call, waiting for a peripheral to be available + * for writing + * + * @param obj The serial object + * @param c The character to be sent + */ +void serial_putc(serial_t *obj, int c) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + while (!serial_writable(obj)); + usart_data_transmit(p_obj->uart, (int)((c) & BITS(0, 7 + (p_obj->databits >> 12)))); +} + +/** Check if the serial peripheral is readable + * + * @param obj The serial object + * @return Non-zero value if a character can be read, 0 if nothing to read + */ +int serial_readable(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return (usart_flag_get(p_obj->uart, USART_FLAG_RBNE) != RESET) ? 1 : 0; +} + +/** Check if the serial peripheral is writable + * + * @param obj The serial object + * @return Non-zero value if a character can be written, 0 otherwise. + */ +int serial_writable(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return (usart_flag_get(p_obj->uart, USART_FLAG_TBE) != RESET) ? 1 : 0; +} + +/** Clear the serial peripheral + * + * @param obj The serial object + */ +void serial_clear(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + p_obj->tx_count = 0U; + p_obj->rx_count = 0U; +} + +/** Set the break + * + * @param obj The serial object + */ +void serial_break_set(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + usart_send_break(p_obj->uart); +} + +/** Clear the break + * + * @param obj The serial object + */ +void serial_break_clear(serial_t *obj) +{ + /* do nothing */ +} + +/** Configure the TX pin for UART function. + * + * @param tx The pin name used for TX + */ +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +#if DEVICE_SERIAL_ASYNCH +/** + * Enable the serial events + * + * @param obj The serial object + * @param event The events to be configured + */ +static void serial_event_enable(serial_t *obj, int event) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + p_obj->events |= event; + +} + +/** + * Disable the serial events + * + * @param obj The serial object + * @param event The events to be configured + */ +static void serial_event_disable(serial_t *obj, int event) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + p_obj->events &= ~event; +} + +/** + * Preprocess the USART tx interrupt + * + * @param obj_s The serial object + * @param pData Pointer to tx buffer + * @param Size Size of tx buffer + * @return Returns the status + */ +gd_status_enum usart_tx_interrupt_preprocess(struct serial_s *obj_s, uint8_t *pData, uint16_t Size) +{ + if (obj_s->tx_state == OP_STATE_READY) { + if ((pData == NULL) || (Size == 0U)) { + return GD_ERROR; + } + + obj_s->tx_buffer_ptr = pData; + obj_s->tx_count = Size; + obj_s->error_code = USART_ERROR_CODE_NONE; + obj_s->tx_state = OP_STATE_BUSY_TX; + + usart_interrupt_enable(obj_s->uart, USART_INT_TBE); + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** + * Preprocess the USART rx interrupt + * + * @param obj_s The serial object + * @param pData Pointer to rx buffer + * @param Size Size of rx buffer + * @return Returns the status + */ +gd_status_enum usart_rx_interrupt_preprocess(struct serial_s *obj_s, uint8_t *pData, uint16_t Size) +{ + if (obj_s->rx_state == OP_STATE_READY) { + if ((pData == NULL) || (Size == 0U)) { + return GD_ERROR; + } + + obj_s->rx_buffer_ptr = pData; + obj_s->rx_size = Size; + obj_s->rx_count = Size; + obj_s->error_code = USART_ERROR_CODE_NONE; + obj_s->rx_state = OP_STATE_BUSY_RX; + + usart_interrupt_enable(obj_s->uart, USART_INT_PERR); + usart_interrupt_enable(obj_s->uart, USART_INT_ERR); + usart_interrupt_enable(obj_s->uart, USART_INT_RBNE); + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** Begin asynchronous TX transfer. The used buffer is specified in the serial object, + * tx_buff + * + * @param obj The serial object + * @param tx The transmit buffer + * @param tx_length The number of bytes to transmit + * @param tx_width Deprecated argument + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param hint A suggestion for how to use DMA with this transfer + * @return Returns number of data transfered, otherwise returns 0 + */ +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + IRQn_Type irq = usart_irq_n[p_obj->index]; + + if ((tx_length == 0) || (tx_width != 8)) { + return 0; + } + + if (serial_tx_active(obj)) { + /* some transmit is in progress */ + return 0; + } + + obj->tx_buff.buffer = (void *)tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + + /* disable all events first */ + serial_event_disable(obj, SERIAL_EVENT_TX_ALL); + /* enable the specific event */ + serial_event_enable(obj, event); + + /* enable interrupt */ + /* clear pending IRQ */ + NVIC_ClearPendingIRQ(irq); + /* disable the IRQ first */ + NVIC_DisableIRQ(irq); + /* set the priority and vector */ + NVIC_SetPriority(irq, 1); + NVIC_SetVector(irq, (uint32_t)handler); + /* enable IRQ */ + NVIC_EnableIRQ(irq); + + if (usart_tx_interrupt_preprocess(p_obj, (uint8_t *)tx, tx_length) != GD_OK) { + return 0; + } + + return tx_length; +} + +/** Begin asynchronous RX transfer (enable interrupt for data collecting) + * The used buffer is specified in the serial object - rx_buff + * + * @param obj The serial object + * @param rx The receive buffer + * @param rx_length The number of bytes to receive + * @param rx_width Deprecated argument + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param handler The serial handler + * @param char_match A character in range 0-254 to be matched + * @param hint A suggestion for how to use DMA with this transfer + */ +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + IRQn_Type irq = usart_irq_n[p_obj->index]; + + if ((rx_length == 0) || (rx_width != 8)) { + return; + } + + /* disable all events first */ + serial_event_disable(obj, SERIAL_EVENT_RX_ALL); + /* enable the specific event */ + serial_event_enable(obj, event); + + obj->char_match = char_match; + + if (serial_rx_active(obj)) { + /* some reception is in progress */ + return; + } + + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + + /* enable interrupt */ + /* clear pending IRQ */ + NVIC_ClearPendingIRQ(irq); + /* disable the IRQ first */ + NVIC_DisableIRQ(irq); + /* set the priority(higher than Tx) and vector */ + NVIC_SetPriority(irq, 0); + NVIC_SetVector(irq, (uint32_t)handler); + /* enable IRQ */ + NVIC_EnableIRQ(irq); + + usart_rx_interrupt_preprocess(p_obj, (uint8_t *)rx, rx_length); +} + +/** Attempts to determine if the serial peripheral is already in use for TX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_tx_active(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return ((p_obj->tx_state == OP_STATE_BUSY_TX) ? 1 : 0); +} + +/** Attempts to determine if the serial peripheral is already in use for RX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_rx_active(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return ((p_obj->rx_state == OP_STATE_BUSY_RX) ? 1 : 0); +} + +/** Handle the serial rx interrupt + * + * @param obj_s The serial object + * @return Returns the status + */ +static gd_status_enum usart_rx_interrupt(struct serial_s *obj_s) +{ + uint16_t *temp; + + if (obj_s->rx_state == OP_STATE_BUSY_RX) { + if (obj_s->databits == USART_WL_9BIT) { + temp = (uint16_t *) obj_s->rx_buffer_ptr; + if (obj_s->parity == USART_PM_NONE) { + /* 9-bit data, none parity bit */ + *temp = (uint16_t)(USART_DATA(obj_s->uart) & (uint16_t)0x01FF); + obj_s->rx_buffer_ptr += 2U; + } else { + /* 9-bit data, with parity bit */ + *temp = (uint16_t)(USART_DATA(obj_s->uart) & (uint16_t)0x00FF); + obj_s->rx_buffer_ptr += 1U; + } + } else { + if (obj_s->parity == USART_PM_NONE) { + /* 8-bit data, none parity bit */ + *obj_s->rx_buffer_ptr++ = (uint8_t)(USART_DATA(obj_s->uart) & (uint8_t)0x00FF); + } else { + /* 8-bit data, with parity bit */ + *obj_s->rx_buffer_ptr++ = (uint8_t)(USART_DATA(obj_s->uart) & (uint8_t)0x007F); + } + } + + if (--obj_s->rx_count == 0U) { + usart_interrupt_disable(obj_s->uart, USART_INT_RBNE); + usart_interrupt_disable(obj_s->uart, USART_INT_PERR); + usart_interrupt_disable(obj_s->uart, USART_INT_ERR); + + obj_s->rx_state = OP_STATE_READY; + } + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** Handle the serial tx interrupt + * + * @param obj_s The serial object + * @return Returns the status + */ +static gd_status_enum usart_tx_interrupt(struct serial_s *obj_s) +{ + uint16_t *temp; + + if (obj_s->tx_state == OP_STATE_BUSY_TX) { + if (obj_s->databits == USART_WL_9BIT) { + temp = (uint16_t *) obj_s->tx_buffer_ptr; + USART_DATA(obj_s->uart) = (uint16_t)(*temp & (uint16_t)0x01FF); + if (obj_s->parity == USART_PM_NONE) { + obj_s->tx_buffer_ptr += 2U; + } else { + obj_s->tx_buffer_ptr += 1U; + } + } else { + USART_DATA(obj_s->uart) = (uint8_t)(*obj_s->tx_buffer_ptr++ & (uint8_t)0x00FF); + } + + if (--obj_s->tx_count == 0U) { + /* disable USART_INT_TBE interrupt */ + usart_interrupt_disable(obj_s->uart, USART_INT_TBE); + + /* enable USART_INT_TC interrupt */ + usart_interrupt_enable(obj_s->uart, USART_INT_TC); + } + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** Handle the serial tx complete interrupt + * + * @param obj_s The serial object + */ +void usart_tx_complete_interrupt(struct serial_s *obj_s) +{ + usart_interrupt_disable(obj_s->uart, USART_INT_TC); + + obj_s->tx_state = OP_STATE_READY; +} + +/** Handle all the serial interrupt request + * + * @param obj_s The serial object + */ +void usart_irq_handler(struct serial_s *obj_s) +{ + uint32_t err_flags = 0U; + + /* no error occurs */ + err_flags = (USART_STAT0(obj_s->uart) & (uint32_t)(USART_FLAG_PERR | USART_FLAG_FERR | USART_FLAG_ORERR | USART_FLAG_NERR)); + if (err_flags == RESET) { + /* check whether USART is in receiver mode or not */ + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_RBNE) != RESET) { + usart_rx_interrupt(obj_s); + + return; + } + } + + /* some errors occur */ + if ((err_flags != RESET) && + (((USART_CTL2(obj_s->uart) & USART_INT_ERR) != RESET) || + ((USART_CTL0(obj_s->uart) & (USART_INT_RBNE | USART_INT_PERR)) != RESET))) { + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_PERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_PERR; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_ERR_NERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_NERR; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_ERR_FERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_FERR; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_ERR_ORERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_ORERR; + } + + if (obj_s->error_code != USART_ERROR_CODE_NONE) { + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_RBNE) != RESET) { + usart_rx_interrupt(obj_s); + } + } + + return; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_TBE) != RESET) { + usart_tx_interrupt(obj_s); + return; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_TC) != RESET) { + usart_tx_complete_interrupt(obj_s); + return; + } +} + +/** The asynchronous TX and RX handler. + * + * @param obj The serial object + * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0 + */ +int serial_irq_handler_asynch(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + volatile uint8_t i = 0; + volatile int return_val = 0; + uint8_t *p_buf = (uint8_t *)(obj->rx_buff.buffer); + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_PERR) != RESET) { + usart_interrupt_flag_clear(p_obj->uart, USART_INT_FLAG_PERR); + return_val |= (SERIAL_EVENT_RX_PARITY_ERROR & p_obj->events); + p_obj->error_code |= USART_ERROR_CODE_PERR; + } + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_ERR_FERR) != RESET) { + usart_interrupt_flag_clear(p_obj->uart, USART_INT_FLAG_ERR_FERR); + return_val |= (SERIAL_EVENT_RX_FRAMING_ERROR & p_obj->events); + p_obj->error_code |= USART_ERROR_CODE_FERR; + } + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_ERR_ORERR) != RESET) { + usart_interrupt_flag_clear(p_obj->uart, USART_INT_FLAG_ERR_ORERR); + return_val |= (SERIAL_EVENT_RX_OVERRUN_ERROR & p_obj->events); + p_obj->error_code |= USART_ERROR_CODE_ORERR; + } + + if (return_val & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR | + SERIAL_EVENT_RX_OVERRUN_ERROR)) { + return return_val; + } + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_TC) != RESET) { + if ((p_obj->events & SERIAL_EVENT_TX_COMPLETE) != 0) { + return_val |= (SERIAL_EVENT_TX_COMPLETE & p_obj->events); + } + } + + usart_irq_handler(p_obj); + + if (p_obj->rx_size != 0) { + obj->rx_buff.pos = p_obj->rx_size - p_obj->rx_count; + } + + if ((p_obj->rx_count == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { + return_val |= (SERIAL_EVENT_RX_COMPLETE & p_obj->events); + } + + if (p_obj->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { + if (p_buf != NULL) { + for (i = 0; i < obj->rx_buff.pos; i++) { + if (p_buf[i] == obj->char_match) { + obj->rx_buff.pos = i; + return_val |= (SERIAL_EVENT_RX_CHARACTER_MATCH & p_obj->events); + serial_rx_abort_asynch(obj); + break; + } + } + } + } + + return return_val; +} + +/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and + * flushes the TX hardware buffer if TX FIFO is used + * + * @param obj The serial object + */ +void serial_tx_abort_asynch(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + usart_interrupt_disable(p_obj->uart, USART_INT_TC); + usart_interrupt_disable(p_obj->uart, USART_INT_TBE); + + usart_flag_clear(p_obj->uart, USART_FLAG_TC); + + p_obj->tx_count = 0; + p_obj->tx_state = OP_STATE_READY; +} + +/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and + * flushes the RX hardware buffer if RX FIFO is used + * + * @param obj The serial object + */ +void serial_rx_abort_asynch(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + /* disable interrupts */ + usart_interrupt_disable(p_obj->uart, USART_INT_RBNE); + usart_interrupt_disable(p_obj->uart, USART_INT_PERR); + usart_interrupt_disable(p_obj->uart, USART_INT_ERR); + + /* clear USART_FLAG_RBNE flag */ + usart_flag_clear(p_obj->uart, USART_FLAG_RBNE); + + /* clear errors flag */ + usart_flag_clear(p_obj->uart, USART_FLAG_PERR); + usart_flag_clear(p_obj->uart, USART_FLAG_FERR); + usart_flag_clear(p_obj->uart, USART_FLAG_ORERR); + /* clear RBNE flag */ + USART_DATA(p_obj->uart); + + /* reset rx transfer count */ + p_obj->rx_count = 0; + + /* reset rx state */ + p_obj->rx_state = OP_STATE_READY; +} + +#endif /* DEVICE_SERIAL_ASYNCH */ + +#if DEVICE_SERIAL_FC +/** Configure the serial for the flow control. It sets flow control in the hardware + * if a serial peripheral supports it, otherwise software emulation is used. + * + * @param obj The serial object + * @param type The type of the flow control. Look at the available FlowControl types. + * @param rxflow The TX pin name + * @param txflow The RX pin name + */ +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + uint16_t uen_flag = 0U; + struct serial_s *p_obj = GET_SERIAL_S(obj); + /* store the UEN flag */ + uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; + + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + + p_obj->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); + MBED_ASSERT(p_obj->uart != (UARTName)NC); + + /* disable USART to modify CTS/RTS configuration */ + usart_disable(p_obj->uart); + + if (type == FlowControlNone) { + p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); + } + + if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName)NC); + p_obj->hw_flow_ctl = USART_HWCONTROL_RTS; + p_obj->pin_rts = rxflow; + pinmap_pinout(rxflow, PinMap_UART_RTS); + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); + } + + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName)NC); + p_obj->hw_flow_ctl = USART_HWCONTROL_CTS; + p_obj->pin_cts = txflow; + pinmap_pinout(txflow, PinMap_UART_CTS); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); + } + + if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_rts != (UARTName)NC); + MBED_ASSERT(uart_cts != (UARTName)NC); + p_obj->hw_flow_ctl = USART_HWCONTROL_RTS_CTS; + p_obj->pin_rts = rxflow; + p_obj->pin_cts = txflow; + pinmap_pinout(txflow, PinMap_UART_CTS); + pinmap_pinout(rxflow, PinMap_UART_RTS); + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); + } + + /* restore the UEN flag */ + if (RESET != uen_flag) { + usart_enable(p_obj->uart); + } +} + +#endif /* DEVICE_SERIAL_FC */ + +#if DEVICE_SLEEP +/** Check whether the serial is in busy state + * + * @return 0: all the serial is free to use, 1: some serial is in busy in transfer + */ +int serial_busy_state_check(void) +{ +#if defined(USART0) + if ((USART_CTL0(USART0) & USART_CTL0_UEN) && !(USART_STAT0(USART0) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(USART1) + if ((USART_CTL0(USART1) & USART_CTL0_UEN) && !(USART_STAT0(USART1) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(USART2) + if ((USART_CTL0(USART2) & USART_CTL0_UEN) && !(USART_STAT0(USART2) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(UART3) + if ((USART_CTL0(UART3) & USART_CTL0_UEN) && !(USART_STAT0(UART3) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(UART4) + if ((USART_CTL0(UART4) & USART_CTL0_UEN) && !(USART_STAT0(UART4) & USART_STAT0_TC)) { + return 1; + } +#endif + + /* no serial is in busy state */ + return 0; +} +#endif /* DEVICE_SLEEP */ + +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/sleep.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/sleep.c new file mode 100644 index 00000000000..d4ccc122a89 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/sleep.c @@ -0,0 +1,189 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, Gigadevice + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Gigadevice nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#if DEVICE_SLEEP + +#include "sleep_api.h" +#include "us_ticker_api.h" +#include "mbed_critical.h" +#include "mbed_error.h" + +extern void ticker_timer_data_save(void); +extern void ticker_timer_data_restore(void); +extern int serial_busy_state_check(void); + +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while (1) { + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while (0U == (PMU_CS & PMU_CS_HDRF)) { + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while (0U == (PMU_CS & PMU_CS_HDSRF)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + + +/** Send the microcontroller to sleep + * + * The processor is setup ready for sleep, and sent to sleep. In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * The wake-up time shall be less than 10 us. + * + */ +void hal_sleep(void) +{ + /* Disable Interrupts */ + core_util_critical_section_enter(); + + /* Enter SLEEP mode */ + pmu_to_sleepmode(WFI_CMD); + + /* Enable Interrupts */ + core_util_critical_section_exit(); +} + + +/** Send the microcontroller to deep sleep + * + * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode + * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks. + * All state is still maintained. + * + * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer. + * + * The wake-up time shall be less than 10 ms. + */ +void hal_deepsleep(void) +{ + if (0 != serial_busy_state_check()) { + return; + } + + /* Disable Interrupts */ + core_util_critical_section_enter(); + + ticker_timer_data_save(); + + /* Enter DEEP SLEEP mode */ + rcu_periph_clock_enable(RCU_PMU); + pmu_to_deepsleepmode(PMU_LDO_NORMAL, WFI_CMD); + + /* Reconfigure the PLL after weak up */ + system_clock_120m_hxtal(); + + ticker_timer_data_restore(); + + /* Enable Interrupts */ + core_util_critical_section_exit(); +} + +#endif /* DEVICE_SLEEP */ diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/spi_api.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/spi_api.c new file mode 100644 index 00000000000..f168007f57c --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/spi_api.c @@ -0,0 +1,372 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "spi_api.h" + +#if DEVICE_SPI +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#define SPI_S(obj) (( struct spi_s *)(obj)) + +/** Get the frequency of SPI clock source + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] spi_freq The SPI clock source freguency + * @param[in] obj The SPI object + */ +static int dev_spi_clock_source_frequency_get(spi_t *obj) +{ + int spi_freq = 0; + struct spi_s *spiobj = SPI_S(obj); + + switch ((int)spiobj->spi) { + case SPI0: + /* clock source is APB2 */ + spi_freq = rcu_clock_freq_get(CK_APB2); + break; + case SPI1: + /* clock source is APB1 */ + spi_freq = rcu_clock_freq_get(CK_APB1); + break; + case SPI2: + /* clock source is APB1 */ + spi_freq = rcu_clock_freq_get(CK_APB1); + break; + default: + error("SPI clock source frequency get error"); + break; + } + return spi_freq; +} + +/** Initialize the SPI structure + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + */ +static void dev_spi_struct_init(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + + spi_disable(spiobj->spi); + spi_para_init(spiobj->spi, &obj->spi_struct); + spi_enable(spiobj->spi); +} + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + * @param[in] mosi The pin to use for MOSI + * @param[in] miso The pin to use for MISO + * @param[in] sclk The pin to use for SCLK + * @param[in] ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + struct spi_s *spiobj = SPI_S(obj); + + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + /* return SPIName according to PinName */ + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT(spiobj->spi != (SPIName)NC); + + /* Set iqr type */ + if (spiobj->spi == SPI0) { + rcu_periph_clock_enable(RCU_SPI0); + spiobj->spi_irq = SPI0_IRQn; + } + if (spiobj->spi == SPI1) { + rcu_periph_clock_enable(RCU_SPI1); + spiobj->spi_irq = SPI1_IRQn; + } + if (spiobj->spi == SPI2) { + rcu_periph_clock_enable(RCU_SPI2); + spiobj->spi_irq = SPI2_IRQn; + } + + /* config GPIO mode of SPI pins */ + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + spiobj->pin_miso = miso; + spiobj->pin_mosi = mosi; + spiobj->pin_sclk = sclk; + spiobj->pin_ssel = ssel; + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + spiobj->spi_struct.nss = SPI_NSS_HARD; + } else { + spiobj->spi_struct.nss = SPI_NSS_SOFT; + } + + /* Default values */ + spiobj->spi_struct.device_mode = SPI_MASTER; + spiobj->spi_struct.prescale = SPI_PSC_256; + spiobj->spi_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spiobj->spi_struct.frame_size = SPI_FRAMESIZE_8BIT; + spiobj->spi_struct.endian = SPI_ENDIAN_MSB; + + dev_spi_struct_init(obj); +} + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * @param[in] obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_disable(spiobj->spi); + + /* Disable and deinit SPI */ + if (spiobj->spi == SPI0) { + spi_i2s_deinit(SPI0); + rcu_periph_clock_disable(RCU_SPI0); + } + if (spiobj->spi == SPI1) { + spi_i2s_deinit(SPI1); + rcu_periph_clock_disable(RCU_SPI1); + } + if (spiobj->spi == SPI2) { + spi_i2s_deinit(SPI2); + rcu_periph_clock_disable(RCU_SPI2); + } + /* Deinit GPIO mode of SPI pins */ + pin_function(spiobj->pin_miso, MODE_IN_FLOATING); + pin_function(spiobj->pin_mosi, MODE_IN_FLOATING); + pin_function(spiobj->pin_sclk, MODE_IN_FLOATING); + if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { + pin_function(spiobj->pin_ssel, MODE_IN_FLOATING); + } +} + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. + * The default bit order is MSB. + * @param[in,out] obj The SPI object to configure + * @param[in] bits The number of bits per frame + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] slave Zero for master mode or non-zero for slave mode + */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + struct spi_s *spiobj = SPI_S(obj); + + spiobj->spi_struct.frame_size = (bits == 16) ? SPI_FRAMESIZE_16BIT : SPI_FRAMESIZE_8BIT; + /* Config polarity and phase of SPI */ + switch (mode) { + case 0: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + break; + case 1: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; + break; + case 2: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; + break; + default: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + + break; + } + + if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { + spiobj->spi_struct.nss = SPI_NSS_HARD; + spi_nss_output_enable(spiobj->spi); + } + /* Select SPI as master or slave */ + spiobj->spi_struct.device_mode = (slave) ? SPI_SLAVE : SPI_MASTER; + + dev_spi_struct_init(obj); +} + +static const uint16_t baudrate_prescaler_table[] = {SPI_PSC_2, + SPI_PSC_4, + SPI_PSC_8, + SPI_PSC_16, + SPI_PSC_32, + SPI_PSC_64, + SPI_PSC_128, + SPI_PSC_256 + }; + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz) +{ + struct spi_s *spiobj = SPI_S(obj); + int spi_hz = 0; + uint8_t prescaler_rank = 0; + uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1; + + spi_hz = dev_spi_clock_source_frequency_get(obj) / 2; + + /* Config SPI prescaler according to input frequency*/ + while ((spi_hz > hz) && (prescaler_rank < last_index)) { + spi_hz = spi_hz / 2; + prescaler_rank++; + } + + spiobj->spi_struct.prescale = baudrate_prescaler_table[prescaler_rank]; + dev_spi_struct_init(obj); +} + +/** Write a block out in master mode and receive a value + * + * The total number of bytes sent and received will be the maximum of + * tx_length and rx_length. The bytes written will be padded with the + * value 0xff. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx_buffer Pointer to the byte-array of data to write to the device + * @param[in] tx_length Number of bytes to write, may be zero + * @param[in] rx_buffer Pointer to the byte-array of data to read from the device + * @param[in] rx_length Number of bytes to read, may be zero + * @param[in] write_fill Default data transmitted while performing a read + * @returns + * The number of bytes written and read from the device. This is + * maximum of tx_length and rx_length. + */ +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +/** Write a byte out in master mode and receive a value + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value) +{ + int count = 0; + struct spi_s *spiobj = SPI_S(obj); + + /* wait the SPI transmit buffer is empty */ + while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)) && (count++ < 1000)); + if (count >= 1000) { + return -1; + } else { + spi_i2s_data_transmit(spiobj->spi, value); + } + + count = 0; + /* wait the SPI receive buffer is not empty */ + while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); + if (count >= 1000) { + return -1; + } else { + return spi_i2s_data_receive(spiobj->spi); + } +} + +/** Check if a value is available to read + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if a value is available + */ +int spi_slave_receive(spi_t *obj) +{ + int status; + struct spi_s *spiobj = SPI_S(obj); + /* check whether or not the SPI receive buffer is empty */ + status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE) != RESET) ? 1 : 0); + return status; +} + +/** Get a received value out of the SPI receive buffer in slave mode + * + * Blocks until a value is available + * @param[in] obj The SPI peripheral to read + * @return The value received + */ +int spi_slave_read(spi_t *obj) +{ + int count = 0; + struct spi_s *spiobj = SPI_S(obj); + /* wait the SPI receive buffer is not empty */ + while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); + if (count >= 1000) { + return -1; + } else { + return spi_i2s_data_receive(spiobj->spi); + } +} + +/** Write a value to the SPI peripheral in slave mode + * + * Blocks until the SPI peripheral can be written to + * @param[in] obj The SPI peripheral to write + * @param[in] value The value to write + */ +void spi_slave_write(spi_t *obj, int value) +{ + struct spi_s *spiobj = SPI_S(obj); + /* wait the SPI transmit buffer is empty */ + while (RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)); + spi_i2s_data_transmit(spiobj->spi, value); +} + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if the peripheral is currently transmitting + */ +int spi_busy(spi_t *obj) +{ + int status; + struct spi_s *spiobj = SPI_S(obj); + /* check whether or not the SPI is busy */ + status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TRANS) != RESET) ? 1 : 0); + return status; +} + +#endif diff --git a/targets/TARGET_Gigadevice/TARGET_GD32F30X/us_ticker.c b/targets/TARGET_Gigadevice/TARGET_GD32F30X/us_ticker.c new file mode 100644 index 00000000000..9c82841cce3 --- /dev/null +++ b/targets/TARGET_Gigadevice/TARGET_GD32F30X/us_ticker.c @@ -0,0 +1,386 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gd32f30x.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "hal_tick.h" + +#if TICKER_TIMER_WIDTH_BIT == 16 +uint32_t time_before; +uint32_t total_elapsed_time; +#endif + +/* this variable is set to 1 at the end of mbed_sdk_init function. +the ticker_read_us() function must not be called until the mbed_sdk_init is terminated */ +extern int mbed_sdk_inited; +uint32_t ticker_timer_cnt; +uint32_t ticker_timer_ch0cv; +uint32_t ticker_timer_dmainten; + +void ticker_timer_init(void); +#if TICKER_TIMER_WIDTH_BIT == 16 +void ticker_16bits_timer_init(void); +#else +void ticker_32bits_timer_init(void); +#endif +void ticker_timer_irq_handler(void); +/* get TIMER clock */ +static uint32_t timer_get_clock(uint32_t timer_periph); +uint32_t ticker_tick_get(void); +void ticker_timer_data_save(void); +void ticker_timer_data_save(void); +void ticker_timer_data_restore(void); + +void ticker_timer_init(void) +{ +#if TICKER_TIMER_WIDTH_BIT == 16 + ticker_16bits_timer_init(); +#else + ticker_32bits_timer_init(); +#endif +} + +/** get tick + * + * @return the tick + */ +uint32_t ticker_tick_get(void) +{ +#if TICKER_TIMER_WIDTH_BIT == 16 + uint32_t new_time; + if (mbed_sdk_inited) { + /* Apply the latest time recorded just before the sdk is inited */ + new_time = ticker_read_us(get_us_ticker_data()) + time_before; + time_before = 0; + return (new_time / 1000); + } else { + /* Prevent small values from subtracting large ones + example: + 0x0010-0xFFEE=FFFF0022 , (0xFFFF-0xFFEE+0x10+1=0x22,1 mean CNT=0 tick) + FFFF0022 & 0xFFFF = 0022 + */ + new_time = us_ticker_read(); + total_elapsed_time += (new_time - time_before) & 0xFFFF; + time_before = new_time; + return (total_elapsed_time / 1000); + } +#else // 32-bit timer + if (mbed_sdk_inited) { + return (ticker_read_us(get_us_ticker_data()) / 1000); + } else { + return (us_ticker_read() / 1000); + } +#endif +} + +/** Get frequency and counter bits of this ticker. + */ +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 1000000, + TICKER_TIMER_WIDTH_BIT + }; + return &info; +} + + + +/* config for 32bits TIMER */ +#if TICKER_TIMER_WIDTH_BIT == 16 +/** config the interrupt handler + */ +void ticker_timer_irq_handler(void) +{ + if (SET == timer_interrupt_flag_get(TICKER_TIMER, TIMER_INT_FLAG_CH0)) { + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + us_ticker_irq_handler(); + } +} + +/** initialize the TIMER + */ +void ticker_16bits_timer_init(void) +{ + timer_parameter_struct timer_initpara; + uint32_t timer_clk = timer_get_clock(TICKER_TIMER); + + /* enable ticker timer clock */ + TICKER_TIMER_RCU_CLOCK_ENABLE; + + /* reset ticker timer peripheral */ + TICKER_TIMER_RESET_ENABLE; + TICKER_TIMER_RESET_DISABLE; + + /* TICKER_TIMER configuration */ + timer_initpara.prescaler = (uint32_t)(timer_clk / 1000000) - 1;; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 0xFFFF; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TICKER_TIMER, &timer_initpara); + + /* auto-reload preload disable */ + timer_auto_reload_shadow_disable(TICKER_TIMER); + + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); + + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, ENABLE); + + timer_enable(TICKER_TIMER); + + /* Output compare channel 0 interrupt for mbed timeout */ + NVIC_SetVector(TICKER_TIMER_IRQ, (uint32_t)ticker_timer_irq_handler); + NVIC_EnableIRQ(TICKER_TIMER_IRQ); + + /* if define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json or other file, + hold the TICKER_TIMER counter for debug when core halted + */ +#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TICKER_TIMER_DEBUG_STOP) + TICKER_TIMER_DEBUG_STOP; +#endif + + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); + + /* used by ticker_tick_get() */ + time_before = 0; + total_elapsed_time = 0; +} +/* config for 32bits TIMER */ +#else +/** config the interrupt handler + */ +void ticker_timer_irq_handler(void) +{ + if (SET == timer_interrupt_flag_get(TICKER_TIMER, TIMER_INT_FLAG_CH0)) { + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + us_ticker_irq_handler(); + } +} + +/** initialize the TIMER + */ +void ticker_32bits_timer_init(void) +{ + timer_parameter_struct timer_initpara; + uint32_t timer_clk = timer_get_clock(TICKER_TIMER); + + /* enable ticker timer clock */ + TICKER_TIMER_RCU_CLOCK_ENABLE; + + /* reset ticker timer peripheral */ + TICKER_TIMER_RESET_ENABLE; + TICKER_TIMER_RESET_DISABLE; + + /* TICKER_TIMER configuration */ + timer_initpara.prescaler = (uint32_t)(timer_clk / 1000000) - 1;; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 0xFFFFFFFF; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TICKER_TIMER, &timer_initpara); + + /* auto-reload preload disable */ + timer_auto_reload_shadow_disable(TICKER_TIMER); + + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); + + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, ENABLE); + + timer_enable(TICKER_TIMER); + + /* Output compare channel 0 interrupt for mbed timeout */ + NVIC_SetVector(TICKER_TIMER_IRQ, (uint32_t)ticker_timer_irq_handler); + NVIC_EnableIRQ(TICKER_TIMER_IRQ); + + /* if define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json or other file, + hold the TICKER_TIMER counter for debug when core halted + */ +#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TICKER_TIMER_DEBUG_STOP) + TICKER_TIMER_DEBUG_STOP; +#endif + + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); +} + +#endif /* 16-bit/32-bit timer init */ + +/** Initialize the ticker + * + * Initialize or re-initialize the ticker. This resets all the + * clocking and prescaler registers, along with disabling + * the compare interrupt. + * + * @note Initialization properties tested by ::ticker_init_test + */ +void us_ticker_init(void) +{ + /* TIMER is already initialized in ticker_timer_init() */ + /* disable the TIMER interrupt */ + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); + + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, ENABLE); + + timer_enable(TICKER_TIMER); + +} + +/** Read the current counter + * + * Read the current counter value without performing frequency conversions. + * If no rollover has occurred, the seconds passed since us_ticker_init() + * was called can be found by dividing the ticks returned by this function + * by the frequency returned by ::us_ticker_get_info. + * + * @return The current timer's counter value in ticks + */ +uint32_t us_ticker_read() +{ + /* read TIMER counter value */ + uint32_t count_value = 0U; + count_value = TIMER_CNT(TICKER_TIMER); + return (count_value); +} + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in ticks to be set + * + * @note no special handling needs to be done for times in the past + * as the common timer code will detect this and call + * us_ticker_fire_interrupt() if this is the case + * + * @note calling this function with timestamp of more than the supported + * number of bits returned by ::us_ticker_get_info results in undefined + * behavior. + */ +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + /* configure TIMER channel output pulse value.Only set this value when you interrupt disabled */ + timer_channel_output_pulse_value_config(TICKER_TIMER, TIMER_CH_0, (uint32_t)timestamp); + /* clear TIMER interrupt flag,enable the TIMER interrupt */ + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + timer_interrupt_enable(TICKER_TIMER, TIMER_INT_CH0); +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + */ +void us_ticker_fire_interrupt(void) +{ + /* clear TIMER interrupt flag */ + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + /* channel 0 capture or compare event generation immediately,so CH0IF set for interrupt */ + timer_event_software_generate(TICKER_TIMER, TIMER_EVENT_SRC_CH0G); + /* enable the TIMER interrupt */ + timer_interrupt_enable(TICKER_TIMER, TIMER_INT_CH0); +} + +/** Disable us ticker interrupt + */ +void us_ticker_disable_interrupt(void) +{ + /* disable the TIMER interrupt */ + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); +} + +/** Clear us ticker interrupt + * note: must be called with interrupts disabled function + */ +void us_ticker_clear_interrupt(void) +{ + /* clear TIMER interrupt flag */ + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); +} + +/** save ticker TIMER data when MCU go to deepsleep +*/ +void ticker_timer_data_save(void) +{ + ticker_timer_cnt = TIMER_CNT(TICKER_TIMER); + ticker_timer_ch0cv = TIMER_CH0CV(TICKER_TIMER); + ticker_timer_dmainten = TIMER_DMAINTEN(TICKER_TIMER); +} + +/** restore ticker TIMER data when MCU go out deepsleep +*/ +void ticker_timer_data_restore(void) +{ + TIMER_CNT(TICKER_TIMER) = ticker_timer_cnt; + TIMER_CH0CV(TICKER_TIMER) = ticker_timer_ch0cv; + TIMER_DMAINTEN(TICKER_TIMER) = ticker_timer_dmainten; +} + +/** Deinitialize the us ticker + * + * Powerdown the us ticker in preparation for sleep, powerdown, or reset. + * + * After this function is called, no other ticker functions should be called + * except us_ticker_init(), calling any function other than init is undefined. + * + * @note This function stops the ticker from counting. + */ +void us_ticker_free(void) +{ + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_DISABLE); + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, DISABLE); + /* disable a TIMER */ + timer_disable(TICKER_TIMER); + + us_ticker_disable_interrupt(); +} + +/** get TIMER clock + * @param timer_dev: TIMER device information structrue + the structure is not necessary to be reconfigured after structrue initialization, + the structure parameters altering is automatically configured by core + * @return TIMER clock +*/ +static uint32_t timer_get_clock(uint32_t timer_periph) +{ + uint32_t timerclk; + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || (TIMER10 == timer_periph)) { + /* get the current APB2 TIMER clock source */ + if (RCU_APB2_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB2PSC)) { + timerclk = rcu_clock_freq_get(CK_APB2); + } else { + timerclk = rcu_clock_freq_get(CK_APB2) * 2; + } + } else { + /* get the current APB1 TIMER clock source */ + if (RCU_APB1_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB1PSC)) { + timerclk = rcu_clock_freq_get(CK_APB1); + } else { + timerclk = rcu_clock_freq_get(CK_APB1) * 2; + } + } + + return timerclk; +} diff --git a/targets/TARGET_Gigadevice/mbed_rtx.h b/targets/TARGET_Gigadevice/mbed_rtx.h new file mode 100644 index 00000000000..193a67ec5c5 --- /dev/null +++ b/targets/TARGET_Gigadevice/mbed_rtx.h @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#include + +#if defined(TARGET_GD32F307VG) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20018000UL) +#endif + +#endif + +#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS)) +extern uint32_t __StackLimit[]; +extern uint32_t __StackTop[]; +extern uint32_t __end__[]; +extern uint32_t __HeapLimit[]; +#define HEAP_START ((unsigned char*)__end__) +#define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) +#define ISR_STACK_START ((unsigned char*)__StackLimit) +#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) +#endif + +#endif /* MBED_MBED_RTX_H */ diff --git a/targets/targets.json b/targets/targets.json index 251c7e5d210..a124cf90bd6 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -4459,5 +4459,26 @@ "device_name": "TMPM3H6FWFG", "detect_code": ["7012"], "release_versions": ["5"] + }, + "GD32_Target": { + "inherits": ["Target"], + "public": false, + "extra_labels": ["Gigadevice"], + "supported_toolchains": ["ARM", "IAR", "GCC_ARM"], + "device_has":["USTICKER", "ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL"] + }, + "GD32_F307VG": { + "inherits": ["GD32_Target"], + "supported_form_factors": ["ARDUINO"], + "core": "Cortex-M4", + "extra_labels_add": ["GD32F30X", "GD32F307VG", "GD_EMAC"], + "device_has_add": ["RTC", "I2C", "CAN", "I2CSLAVE", "ANALOGOUT", "SPI", "SPISLAVE", "SERIAL_ASYNCH", "SERIAL_FC", "EMAC", "FLASH", "SLEEP"], + "detect_code": ["1701"], + "macros_add": ["GD32F30X_CL"], + "release_versions": ["5"], + "device_name": "GD32F307VG", + "overrides": { + "network-default-interface-type": "ETHERNET" + } } } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index 9278679b8c9..c0a75e63b0c 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -1 +1 @@ -{"S6E2H16E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H16G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1290NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG11B120F128IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC029LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG13P733F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P733F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P733F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMA5D26": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D26.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D27": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D27.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D24": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D24.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2H16F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMA5D22": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D22.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D23": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D23.svd", "processor": {"fpu": "DP_FPU"}}, "HT32F12345_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "IOTKit_CM33_FP_MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.1.0.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF317S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG390F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG390F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG290F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG290F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF317T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFR32BG14P632F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "AMAPH1KK-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 8192]], "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F423RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1237H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "N572P072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "TMPM3HNFYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF106R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F1655_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF415N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF106N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722RC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "HT32F1755_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F429ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4400-F64x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM383FSEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "AC30M1364": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG230F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG230F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F109F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG890F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG890F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LM3S2601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P133F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P133F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P133F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6422": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6422.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S6420": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6420.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG13P733F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P733F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P733F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MQ5xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ5DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ5.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "LM3S600": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s600.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK22FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F105R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK22FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM066FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M066.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F412VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B140F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NM1120ZC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "IOTKit_CM33_MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.1.0.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF328S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF328T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFR32BG1P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG942F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG942F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG13P632F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TLE9879QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MKV11Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV11Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKV11Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "HT32F52344_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D21": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D21.svd", "processor": {"fpu": "DP_FPU"}}, "STM32L451CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK02FN64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "arm/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK02FN64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MK02F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC1301-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKS20FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS20FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS20F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B510F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF529T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "Z32F06410AES": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF166R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF529S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "HT32F50231_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "GD32F150G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC2201LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC2201\\Include\\NUC2201.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG232F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG232F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK63FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK63FN1M0VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK63F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC230VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TMPM3H6FUDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F150G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F2755_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMA5D28": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D28.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F071RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK24FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK24FN1M0VLQ12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK24F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F2755_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO130KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "SN32F707F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMv8MML_DSP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M2351SIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "TMPM3H4FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMHA1G14AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "samha1ab/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1ab/svd/ATSAMHA1G14AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG11B320F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M4TKRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32LG295F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG295F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9844QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285274112, 4096]], "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844.FLM": {"default": "1", "ramsize": null, "size": "0xF000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE9844_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100F000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0x10000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM3H4FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG225F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG225F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF128S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM395FWAXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM395_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFR32BG1P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF128T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK22DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S308": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s308.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "nRF51422_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51422_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51422_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F50241": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "HC32F146J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32F146JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK60DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM061FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M061.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F52253_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG900F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG900F256"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG900F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG220F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52352_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1202-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK52DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK52D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG220F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7661BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMSC000": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMSC000/Include/ARMSC000.h", "define": "ARMSC000"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC000.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM462F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK82FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK82F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK82FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK82F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK82F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "MKE04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": "0x400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z8VWJ4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffff00", "size": "0x0400"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKE04Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P532F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P532F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P532F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C129DNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG390F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG390F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAML22N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F766J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MIMX8MQ7xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "M453YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2CC8J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52253": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKV56F1M0xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV56F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "SRAM_OC": {"start": "0x2f000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x100000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV56F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "TM4C1230C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1230C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F121E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F121E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32L031C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5G36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F410CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG1B232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5G31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1292NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ISD9160": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "EZR32WG230F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F267J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B200F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN256VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1102LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M0519VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52344_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4327": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F446ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F302CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F446ZC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1654": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKE14Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM": {"start": "0x1fffe000", "size": "0x8000"}}, "debug": "MKE14Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MKE16F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE16F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE16F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F303VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F777BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5R31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1236D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1236D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B420F2048IL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG230F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1102UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG330F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG330F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL05Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM376FDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MAX71617": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71616": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "EFR32MG1P232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG230F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG230F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F1653": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFB42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Z32F06423EKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TLE9873QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 45056]], "algorithm": {"Flash/TLE9873.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100AFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0xAFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM3HNFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM380FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TLE9845QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285257728, 4096]], "algorithm": {"Flash/TLE9845.FLM": {"default": "1", "ramsize": null, "size": "0xB000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9845_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100B000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG942F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG942F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32HG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32FG13P231F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F407IE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG11B120F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9867QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B140F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11C12FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC200SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG220F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1778": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F122H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F411RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1774": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1777": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1776": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F411CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM3H3FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC240SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2C29H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52341_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG390F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG390F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5752": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5752.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F427II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M4TKVG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NM1120XB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Mini54ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMD21G16L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21G16L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52231_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MT2523x": {"core": "Cortex-M4", "vendor": "MediaTek:129", "sectors": [[134217728, 4096]], "algorithm": {"tools/keil/mt2523/2523_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x04008000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.6.1.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt2523/Include/mt2523.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x00400000"}, "IRAM2": {"start": "0x04008000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00400000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "208000000"}}, "STM32F410C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC11A12FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMD21G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F50241_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F378VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1J14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1J14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFR32MG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMDA1J14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1J14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "XMC1402-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M058LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F446RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32LG330F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2412": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2412.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EZR32LG330F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MML_DSP_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM067FWQG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M067.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32TG822F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG822F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C129XNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129XNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMR21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F108F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H3FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C58J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S050": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "S6E2C3AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG395F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG395F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32G880F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G880F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F407VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX7D2": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D2_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "MCIMX7D5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "EFM32TG11B320F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX7D7": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D7_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NANO112LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG895F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG895F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG990F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG990F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG980F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG980F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC472HI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "ATSAME70J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TLE9842QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285245440, 4096]], "algorithm": {"Flash/TLE9842_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x11008000"}, "Flash/TLE9842.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x9000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EFM32GG11B840F1024GL192": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL192.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H4FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52243_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F479AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F407VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HC32L156K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L156KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4088FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC130LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F100RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1120TB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ADSP-CM419F-BCZ_M0": {"core": "Cortex-M0", "vendor": "Analog Devices:1", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x200F0000", "size": "0x00008000"}}, "debug": "SVD/CM41x_M0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "M453LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC1100-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F479ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32TG11B320F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HC32L156KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L156KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1101LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D35": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D35.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D34": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D34.svd", "processor": {"fpu": "DP_FPU"}}, "TM4C1231H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D36": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F450VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S2911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F038C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG895F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG895F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG895F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HC32L150KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32FG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B420F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B820F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F423CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC11U12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG11B340F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M052ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC126LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM384FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM38x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M384.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F469ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32GG11B110F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F479IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC442KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EFM32G290F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G290F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1232D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1232D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM4G8F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC844M201JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F767BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1200ZBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F423VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32G222F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD09C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD09_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD09\\ATSAMD09C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4CMS16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F038K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M052ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG900F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG900F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMV71N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32LG990F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG990F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0519SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L432KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK11DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK11DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L081CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL28Z512xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512_KL28.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL28Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL28Z512VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL28Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fff8000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}}, "debug": "MKL28Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF112R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM368FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG13P732F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F1755_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11C22FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKS22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS22FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS22F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B520F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO102SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "HT32F52220_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B100F128IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC472VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "GD32F330K4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "GD32F330K6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "TMPM3H2FSDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMV70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "XMC1302-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL36Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4104-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF314R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L152C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG942F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG942F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG295F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG295F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21E18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC802M011JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "STM32L152V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAM4SD32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD32B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L443RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L100C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F217IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F706J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG14P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P632F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F112E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F112E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK26FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK26F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK26FN2M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK26F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK26F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F52241_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1765_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2DH5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC811M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00002000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/LPC811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFM32LG840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF105N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M451MRD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG1P131F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD09D14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD09_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD09\\ATSAMD09D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F150R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1313FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L476ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG13P632F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F150R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM4S4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5D56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F52220_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF464K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4S4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F121H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F121H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG890F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG890F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG980F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG980F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G6FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG1P131F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F210E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F210E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F22366_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "XMC1202-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C1AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B820F2048IL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC8N04FHI24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8N04_30.FLM": {"default": "1", "ramsize": null, "size": "0x00007800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC8N04.h", "define": "LPC8N04FHI24"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00007800"}}, "debug": "SVD/LPC8N04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "8000000"}}, "LPC1114FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F232H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4317": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4310": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC1114FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4313": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAMD21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21J18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52341": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2B93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2b93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MIMX8MD6xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MB9BF528T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF528S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "NUC123ZD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32G880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1823EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1P132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L151UC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC140VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F50230_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L462VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1B232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9AF341L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54113J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF341N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1251": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1224FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LPC11E11FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF516S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F1253": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32BG12P232F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF62NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF62NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF406R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC472KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "STM32F101CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF406N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1225FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S5P36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3H1FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C18H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF516R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32G842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52230_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S800": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827UB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC120RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MK22FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S801": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s801.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2C19L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG11B520F128IM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54P19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKL02Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffff00", "size": "0x0400"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "Generic_NUC400_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TM4C1294KCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1294KCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1402-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F401RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32GG840F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG840F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M451MLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LPC804M111JDH24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFR32BG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F12365_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "SN32F707BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4700-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9BN2": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U14FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L431KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9BN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG14P732F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC100VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Generic_NUC200_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC123SD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F051T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1120EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMDA0E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MBL/Include/ARMv8MBL.h", "define": "ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32L152RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G200F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32G/EFM32G200F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1755_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "SN32F765J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG290F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG290F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKW21D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P133F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "Mini51XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S5P3B": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1768": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1769": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM366FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1763": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "Mini52FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F101C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1766": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKE16F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE16F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE16F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32GG380F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG380F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1765": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S5747": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5747.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L475JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG14P532F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P532F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P532F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L475JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NM1200LBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11U35FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P231F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM3HPFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F378CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1785": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1786": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1787": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x000020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x000004000"}, "IRAM2": {"start": "0x20080000", "size": "0x000004000"}, "IROM1": {"start": "0x00080000", "size": "0x000020000"}}, "debug": "SVD/SAM3U/ATSAM3U2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAM4LS2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L063R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1788": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG1B132F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4200-Q48x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "N572F072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MCIMX7U5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NUC121ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MCIMX7U3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "STM32L071RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG980F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG980F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG940F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG940F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F131H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F131H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4LS2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32H743VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32WG990F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG990F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L471RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B840F1024IL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L471RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC240SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F450ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "NUC2201SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC2201\\Include\\NUC2201.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F723ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11U34FHN33/311": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC220LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9AFB41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F412CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1114FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L052K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B231F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B231F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BFD18S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAML21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG822F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG822F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM367FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG14P231F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG280F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG280F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM369FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TM4C123BE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG350F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG350F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F215VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM3H2FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F756IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S1F11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK65FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "arm/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "NUC122ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "ATSAM4LS8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKS20FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS20FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS20F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C49L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC812M101JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F767ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M452VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9BF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F479ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF315R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9AF312K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG321F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG321F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM3H2FUDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11E14FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F413VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32PG12B500F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini54XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1233H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1302-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F778AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2CC9J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "Mini51LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LPC11A14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1G21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1g21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1115JET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC220LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P332F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L053C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMR21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108CZ": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [134481920, 16]], "algorithm": {"Flash/STM32W108_192.FLM": {"default": "1", "ramsize": null, "size": "0x30000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x08000000", "size": "0x30000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2D55GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L053C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC122ZC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "XMC1201-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S30": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1231H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [134481920, 16]], "algorithm": {"Flash/STM32W108_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32W108CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F437II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114LVFHN24/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F264S/X": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK10FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54102J512": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54102J512UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54102_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F413CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1V131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F350K8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "ATSAMV71N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ARMCM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM372FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3H0FMDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_8.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/M3H0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG890F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG890F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M0519SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S1332": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F231E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F231E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM3N1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9879QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM368FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TLE9867QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "NM1520LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F301C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK21DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E1A11B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAM4LC8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3748": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3748.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO102LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "MB9BF321K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM037FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M037.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKL26Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GK6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NM1820EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2GK6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F437ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV42F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F437ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1517JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F12366_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NUC120LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F150K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21E18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B420F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAMD21J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0518SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW31Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6X4": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC1112FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6X1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X3": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "S6E2D35GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32G232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG13P632F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1200TBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1401-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C5AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F103ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4R5VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B320F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B320F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B320F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20N/ATSAMC20N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF512R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L100RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S3634": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123AE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123AE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1112FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2GM6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini51LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F103V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F50241_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "M054ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF512N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S1850": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1850.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG280F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG280F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52354": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20N/ATSAMC20N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4320": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4323": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4322": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4325": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F302CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG990F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HC32F146F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32F146FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG295F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG295F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32GG940F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG940F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3A8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3A8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TMPM3H1FPUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 16384], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_48.FLM": {"default": "1", "ramsize": null, "size": "0x0000C000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x0000C000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK64FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK64FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK64F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5K31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG1V131F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKE18F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE18F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE18F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD51J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F777VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM3U1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "Mini57TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32WG880F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG880F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG14P732F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P732F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P732F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L486JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ADSP-CM419F-BCZ_M4": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[285212672, 4096], [285736960, 4096]], "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "0", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M4/CM41x_M4_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.pdsc", "memory": {"IROM2": {"start": "0x11001000", "size": "0x000FF000"}, "IRAM1": {"start": "0x10000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20010000", "size": "0x00018000"}, "IROM1": {"start": "0x11000000", "size": "0x00001000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S5G56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1404-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV10Z32xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKV_P32_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKV10Z1287.h", "define": "MKV10Z64xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LM3S1911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B420F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F12366_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F446VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F722IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM367FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG1B132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F245J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAM3A4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3A4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMD11C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD11_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HC32L110C6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC804M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFM32WG895F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG895F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Z32F12811ARS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F469IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C28J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12345_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1114FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11E36FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S2B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "NUC120RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG232F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG232F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C59H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF465K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F1252": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF465L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL81Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKL_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL81Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL81Z128VMP7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL81Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fffa000", "size": "0x018000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL81Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAMV70Q19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [4194304, 8192], [4194304, 8192], [4194304, 8192], [536870896, 16], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70Q19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "Mini51TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAM4CMP32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMP32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3H5FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S5C31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG1P132F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F705J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4400-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "S6E2DF5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L4R5QI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM370FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG395F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG395F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M485KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "XMC1301-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F131E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F131E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO112VC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMV71N19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71N19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TM4C123GE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C29J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L162ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM4LC2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG895F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG895F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG14P231F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG880F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG880F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK40DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SKEAZN16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO110KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF311K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768], [537657344, 8192]], "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG840F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG840F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG220F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451MRC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC120LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Mini58LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ARMCM0P": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h", "define": "ARMCM0P_MPU"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LM3S2776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M052LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B510F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC131SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG13P732F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD10D13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL04Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2G28J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F773T": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G210F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G210F128"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G210F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MAX71637": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71636": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MK21DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG840F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG840F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 8192], [32768, 16384], [65536, 32768], [131072, 65536], [524288, 8192], [557056, 16384], [589824, 32768], [655360, 65536]], "algorithm": {"Flash/TMPM440_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "LM4F111B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F111B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F0008_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM3H5FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11D14AM": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE18F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE18F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE18F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD11D14AS": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21N/ATSAMC21N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1294NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A04UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini52TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32GG11B840F1024IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAME51J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C129CNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1403-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F122E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F122E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK64FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK64FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MK64F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9L71": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l71.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG14V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14V/Include/em_device.h", "define": "EFR32FG14V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14V/EFR32FG14V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F415OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32LG380F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG380F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1302-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMS70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC11U35FET48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC240VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F1656_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33MA384A": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 256]], "algorithm": {"AC33MA384A/Flashloader/AC33Mx384A_384.flm": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33MA384A\\Core\\include\\AC33Mx384A.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33MA384A\\SVD\\AC33Mx384A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B820F2048GL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P431F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HC32L110B6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110B.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32FG1V131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG308F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG308F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1549JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG942F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG942F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024GL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF341M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3X4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC11E67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG890F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G6FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC123SC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M481LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "ATSAMD21G18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21G18AU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F773S": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F732VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M2351ZIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "XMC1302-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F078CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3826": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s3826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12366_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC43S20": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG980F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG980F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F405ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B95": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b95.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114LVFHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9B96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32G230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52331_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L051R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1B132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM3HQFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4108-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L051R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1520RD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L083RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK11DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMG54J19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAMDA0G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1V131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L152VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG12P232F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKM33Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF114R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F50220_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "PAC5250": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H46F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11U24FET48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D35J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG895F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG895F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG880F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG880F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM461_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B110F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L452VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG222F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAME70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L452VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9GN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9gn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1231C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1231C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG14P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG825F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG825F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG11B820F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P732F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F303R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M0516LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF312R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F303R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230RC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F469NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1224FBD64/121": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC4104-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LPC51U68": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC51U68_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC51U68_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC51U68JBD64"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC51U68_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC51U68.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B540F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMDA0J14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F2641J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD64/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "MK20DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F330F6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "GD32F130K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F407ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B420F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM365FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M365.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM0plus": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM0plus/Include/CMSDK_CM0plus.h", "define": "CMSDK_CM0plus"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0plus.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "GD32F130K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3H3FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F130K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1510LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B520F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6Y7": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F302R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C129DNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "R7S72100": {"core": "Cortex-A9", "vendor": "Renesas:117", "sectors": [[0, 4096]], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.RZ_DFP.1.1.0.pack", "compile": {"header": "Device/Include/RZ_A1H.h", "define": "RZ_A1H"}, "pdsc_file": "http://www.keil.com/pack/Keil.RZ_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x18000000", "size": "0x800000"}}, "processor": {"fpu": "DP_FPU"}}, "MCIMX6Y2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y0": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32L073VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F12366_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "SMM-SSE-200": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.V2M-MPS2_SSE_200_BSP.1.0.3.pack", "compile": {"header": "Device/V2M-MPS2-SSE-200/SMM-SSE-200/Include/mps2_sse_200.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.V2M-MPS2_SSE_200_BSP.pdsc", "memory": {}, "debug": "SVD/MPS2_SSE_200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "20000000"}}, "STM32F779NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV44F64xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32FG1V131F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F072CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF524K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF524L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF524M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF466N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F407ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMR21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5B91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5b91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DL13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "EFM32TG11B140F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1P132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF466R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG995F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG995F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EZR32WG330F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK21FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG995F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG995F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54628J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54628_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54628J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54628_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54628.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF514N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG842F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG842F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32HG108F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG108F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C123GH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32MG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC121SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F072C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52243_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123ZD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32BG14P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P732F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F52342_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC123LC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32BG1P232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMC21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD10C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO100SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32WG840F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG840F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SA16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG290F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG290F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F030K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3HNFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DSA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC845M301JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MB9BF404R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C4AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF404N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4800-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "GD32F350C4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "EFM32TG11B520F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2G36J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32MG13P832F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P832F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P832F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2G36H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKM14Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F758F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350C8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "NANO110RD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MIMXRT1051": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 262144]], "algorithm": {"Flash/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.1.0.2.pack", "compile": {"header": "Device/Include/MIMXRT1052.h", "define": "MIMXRT1052"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IRAM2": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MIMXRT1051.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F765II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MIMXRT1052": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 262144]], "algorithm": {"Flash/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.1.0.2.pack", "compile": {"header": "Device/Include/MIMXRT1052.h", "define": "MIMXRT1052"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IRAM2": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MIMXRT1052.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M4LEDLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG842F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG842F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC131LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "nRF51802_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F52241": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L475ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF428S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "DS_CM3": {"core": "Cortex-M3", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.1.1.0.pack", "compile": {"header": "Device/DS_CM3/Include/DS_CM3.h", "define": "DS_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.pdsc", "memory": {}, "debug": "SVD/DS_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC4333": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4330": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "SN32F774T": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F774S": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ARMv8MML_DSP_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F132H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051R4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1E15AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "samha1b/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1b/svd/ATSAMHA1E15AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F051R6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV46F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV46F256VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV46F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F358VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MIMXRT1052xxxxB": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096], [1610612736, 262144]], "algorithm": {"arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}, "arm/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1052_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1052DVL6B"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1052_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x040000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MIMXRT1052.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "600000000"}}, "EFM32G200F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G200F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG13P732F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U24FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1225FBD64/321": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "EFR32FG1P131F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F350CB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "nRF51824_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32GG11B310F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B310F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B310F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MKV10Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV10Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV10Z1287.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "EFR32MG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P231F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S8730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8733": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8733.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M451LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EZR32HG320F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1765": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M452LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG840F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG840F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO100SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S8933": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8933.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NM1823ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S8930": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8930.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG232F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG232F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "A31G122": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536866816, 128]], "algorithm": {"A31G12x/Flashloader/A31G12x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G12x/Flashloader/A31G12x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G12x/Core/include/A31G12x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "A31G12x/SVD/A31G12x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "A31G123": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536866816, 128]], "algorithm": {"A31G12x/Flashloader/A31G12x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G12x/Flashloader/A31G12x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G12x/Core/include/A31G12x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "A31G12x/SVD/A31G12x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C129ENCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1345FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK60DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MCIMX7S5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "MKW41Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG232F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG232F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U4E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256], [1048576, 256]], "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M052ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1100-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1112FHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM4050": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM4x50.FLM": {"default": "1", "ramsize": null, "size": "0x7F000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM4050.h", "define": "__ADUCM4050__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x7F000"}}, "debug": "SVD/ADuCM4050.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "52000000"}}, "LPC54607J256BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EZR32HG220F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1857": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1850": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1853": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC18S50": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM0": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM0/Include/CMSDK_CM0.h", "define": "CMSDK_CM0"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TLE9861QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 32768]], "algorithm": {"Flash/TLE9861.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC18S57": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1549JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F450IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM4F211H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F211H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F450IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M058LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F450II": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC54618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "MB9BF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1B131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF121J": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9B120J_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xJ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC20J18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P232F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F0008_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFR32MG1P232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKV31F128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F128VLL10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV31F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "HT32F52344_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21E19A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E19A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C129XKCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129XKCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F130C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F130C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3N00B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N00A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC54606J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54606J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54606.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM3H4FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2G38J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NM1820LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC4108-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5762": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5762.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M052ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F038F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F102R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F767F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M481SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32ZG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F779II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG942F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG942F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F100C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1112FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52352": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK24FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F25612_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK24FN256VDC12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK24F25612.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F22366_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MKM33Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAME54N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKL15Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6753": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6753.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3X4E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "NUC100RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M2S005": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LPC11U34FBD48/311": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF141N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1B232F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E1A12B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG230F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG230F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG330F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S57": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC43S50": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "EFR32BG1B132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC140LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L021F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4500-F144x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54016": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54016_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54016JET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54016_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54016.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S8938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P233F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F413MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG14P733F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P733F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P733F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L485JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L485xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F413MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54606J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32L443CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F303C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME51J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EZR32WG330F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE14F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32LG330F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F091RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F102RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G890F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G890F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2276": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2276.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32ZG108F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1233C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1233C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM475FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9844-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285274112, 4096]], "algorithm": {"Flash/TLE9844_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100F000"}, "Flash/TLE9844_2.FLM": {"default": "1", "ramsize": null, "size": "0xF000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0x10000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMC21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52253_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M0516ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMV70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F1653_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1517JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG232F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG232F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F072RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F150C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33M6128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1343FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2GK8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A12FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4076FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F150C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3U4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256], [1048576, 256]], "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32LG895F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG895F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F071VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF565K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG14V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14V/Include/em_device.h", "define": "EFR32FG14V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14V/EFR32FG14V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD51N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NANO100NE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF344N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1120DC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF322K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F410T8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TLE9877QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF322L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF322M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ISD9360": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "M4TKLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKL46Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL46Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL46Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L062K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L062xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L062x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFR32FG1V132F32GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F32GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKL24Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S3654": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U14FET48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S3651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52341_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1251B": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF115R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM3H2FSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F103T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32BG1B232F256GM56": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM56.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5U91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5u91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451MSD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F103T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F723IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F101R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "HT32F50241_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F101R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "XMC1302-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LM3S1651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM330_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F437VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A02UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F265J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC131LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32WG230F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52243_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1P332F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L073CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F350R4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "GD32F350R6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LM4F122H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F350R8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "GD32F170C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C2AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MK53DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B520F128IQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1104UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L073CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F405ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4R5AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW31Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG995F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG995F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9792": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9792.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG880F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM366FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SP32A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4SP_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4SP/sam4sp.h", "define": "__SAM4SP32A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4SP/ATSAM4SP32A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1P732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "Z32F12811ATS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK12DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350RB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "EFM32GG11B120F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F415ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F1654_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF156R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1316FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1V132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U14FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F247F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827YB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L162RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3HPFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG310F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG310F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMR21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF467R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C123GH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32L476ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF467N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F101RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM068FWXBG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M068.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Z32F06410AKS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53N19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B540F64IQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "AC33M8128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3HNFZDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TMPM4G6F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG13P232F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P232F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P232F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F768F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123GH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC802M001JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFR32FG13P233F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P233F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P233F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C1297NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1297NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F745IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "IOTKit_ARMv8MBL": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MBL/Include/IOTKit_ARMv8MBL.h", "define": "IOTKit_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L152VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC200SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MK20DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P132F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC824M201JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC824.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F105VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LPC54005": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54005_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54005JET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54005_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54005.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC802M001JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "STM32F777ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM343FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S815": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s815.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD10D14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG51N18": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51N18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L063C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S3N26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s3n26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF516T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG11B520F128GM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F248BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54616J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32WG942F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG942F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129CNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF405R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54607J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54607J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54607.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "A31G111": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536867328, 128]], "algorithm": {"A31G11x/Flashloader/A31G11x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G11x/Flashloader/A31G11x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G11x/Core/include/A31G11x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "A31G11x/SVD/A31G11x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M4TKVE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L082KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F12365_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F103RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF156N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG14P232F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SKEAZN32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "SN32F759F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54101J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54101J512UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54101.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF405N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L082KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1115FET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F358CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFA31N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM362F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M362.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG842F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG842F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG280F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG280F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AFA41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4S16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B520F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472HG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "MB9BF429S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32LG330F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG330F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF429T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "M054ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M052LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F378RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG12P431F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L152R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M481SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC100LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV58F1M0xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV58F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "SRAM_OC": {"start": "0x2f000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x100000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV58F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "HT32F52220": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32MG14P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B110F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "AC33GA256": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024]], "algorithm": {"AC33GA256/Flashloader/AC33GA256_CDFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33GA256\\Core\\include\\AC33GA256.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33GA256\\SVD\\AC33GA256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32JG12B500F1024IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120DB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3H4FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A11FHN33/001": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1435": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005C00"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1435.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TMPM341FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM341_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "S6E2C2AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG360F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG360F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2H46E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG900F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG900F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG350F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG350F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini54TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LM3S5791": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5791.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C39H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM3H4FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1320LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1320_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1320_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1320_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NM1320AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO103SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1202-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG13P732F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4800-E196x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM364F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M364.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ARMCM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC812M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F413RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F038G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MIMX8MD7xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "NUC120VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "K32W022S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W022S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MK20DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32L053R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F246BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1549JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M0564RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Musca": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [[2097152, 65536]], "algorithm": {"Flash/MT25QL512_DC.FLM": {"default": "1", "ramsize": "0x00020000", "size": "0x10040000", "ramstart": "0x20000000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.Musca_A1_BSP.1.0.2.pack", "compile": {"header": "Device/Include/system_cmsdk_musca.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.Musca_A1_BSP.pdsc", "memory": {}, "debug": "SVD/Musca.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F091CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450ZI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F405OE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32WG360F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG360F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMHA1G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "samha1a/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1a/svd/ATSAMHA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG222F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F439NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "GD32F450ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MAX32652": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "M2S010": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "MAX32650": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MAX32651": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "nRF51801_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F439NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAML22N16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22N16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK70FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG295F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG295F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S32K142": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"addon_cmsis/Flash/S32K142_P256_2KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "platform/devices/S32K142/S32K142.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32L072RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF321M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF321L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1547JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MK20DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO120LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MKE02Z64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1236H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1236H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1112FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L051T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1112FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F413RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F301R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC824M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC824.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F301R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L072RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME51N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NM1120FC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L051T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3H5FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF116S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC54101J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E1A12C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF116T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L152RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1402-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG332F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32L152RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "NUC240SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LPC54114J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM333FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM33x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32LG330F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF218S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF218T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H743BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MB9AF131N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HC32F003C4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F003.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.1.0.0.pack", "compile": {"header": "Device/Include/HC32F003.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32F003.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L4S7AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4TKRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32TG825F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG825F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128GQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKE02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}, "arm/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "M0519LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F706BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F048G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG995F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG995F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1232C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1232C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MVF50NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMHA1E16AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "samha1b/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1b/svd/ATSAMHA1E16AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFR32MG12P432F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMC20J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D55GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F767VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4078FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M0518LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F031K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME53N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "ARMCM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "NANO112SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "AC30M1332": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32PG1B200F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM4G9F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM37AFSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M37A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF118S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF118T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC220SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMD21G15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F746VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG11B420F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F031E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6633": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6633.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32GG380F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG380F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF121M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG990F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG990F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C38L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG995F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG995F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F170R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM374FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M374.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF141L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF141M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3S1A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S1B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKL26Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL26Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL26Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HC32F146KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32F146KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM3HMFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "N572F065": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\N572F065_v3.svd", "processor": {"clock": "48000000"}}, "LPC844M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "HT32F50220_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG11B820F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H44F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H44G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L4A6ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2H44E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54113J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32LG940F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG940F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW35Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO103LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F746VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L162VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F779AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E36FHN33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMC21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32L031F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B540F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "BlueNRG-1": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[268697600, 2048]], "algorithm": {"Flash/STBlueNRG1.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x28000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.1.1.1.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x28000"}}, "debug": "SVD/BlueNRG1.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MCIMX7D3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NANO120SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "BlueNRG-2": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[268697600, 2048]], "algorithm": {"Flash/STBlueNRG2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG-2_DFP.1.0.0.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG-2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x40000"}}, "debug": "SVD/BlueNRG2.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MB9BF564L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "MB9BF564K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F50230_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF156M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "R-IN32M3-EC": {"core": "Cortex-M3", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [33554432, 65536], [268435456, 8192], [268435456, 131072], [268500992, 65536]], "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_EC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "AC33M4064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B420F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123AH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123AH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKL14Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}, "arm/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC802M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFM32PG1B200F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC122LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "HT32F5826": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F5826"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F5826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TM4C1299KCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1299KCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F756J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF312L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54608J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54608_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54608J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54608_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54608.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO130SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "HT32F1755": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini54XFHC": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW20Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW20Z4.h", "define": "MKW20Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW20Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F058C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4350": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MK64FN1M0VLL12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.2.3.0.pack", "compile": {"header": "platform/devices/fsl_device_registers.h", "define": "CPU_MK64FN1M0VLL12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "platform/devices/MK64F12/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4353": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO102LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LPC4357": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MT7687F": {"core": "Cortex-M4", "vendor": "MediaTek:129", "sectors": [[268435456, 4096]], "algorithm": {"tools/keil/mt7687/7687_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.6.1.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt7687/Include/mt7687.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x00100000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00200000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "192000000"}}, "TM4C1233E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54607J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54607J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54607.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKV42F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "LPC54101J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4502-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2DH5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F350K4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "NM1100FAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM343F10XBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV42F64xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "MKM14Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P131F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F401VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "Mini55TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F423MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKL34Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL34Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL34Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL34Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL34Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6G1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "S6E2C3AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX6G3": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TMPM462F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54018": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54018_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54018JET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54018_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54018.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG14P231F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC505YLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "S6E2C58L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HC32L150K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1138": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1138.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK60FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK60FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MCIMX6G0": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32LG230F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1133": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1133.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "APOLLO512-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK50DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NANO130SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ARMCM23": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "QN9083A": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083B": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083C": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAMC20G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG13P231F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG842F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG842F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKV56F512xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV56F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x080000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV56F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "NANO120LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM4F211E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F211E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U35FHI33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F745VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG225F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG225F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F767VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM4LC2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B200F128GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F217ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2533": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2533.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32GG880F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG880F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG395F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG395F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F769BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL26Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL26Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL26Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4R5ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F110E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F110E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L073VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "STM32L471VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAML21J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G9FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAML21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG942F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG942F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK28FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28F15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK28FN2M0VMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28F15_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK28F15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "LPC11U34FBD48/421": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "HC32L110C4UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F246J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U34FHN33/421": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32HG322F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG322F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F50230_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HT32F52231_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC230SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2HG6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1342FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HC32L150F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC4402-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini51FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMC20E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1F16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG330F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG330F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMDA1E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMG51G18": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51G18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L083VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1820ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32G280F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G280F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F231H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F231H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM073FSDUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M073.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F405ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32ZG210F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32HG308F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG308F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1100-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AU9110LF3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/AU9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}, "Flash/AU9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/AU9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAM4LS4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4LS4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S7ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F469AE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "APOLLO256-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L083VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG230F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG230F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L4S9ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NANO100KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NANO103ZD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1225FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TMPM332FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C5AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M482LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFR32MG13P632F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M2S025": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "MKL24Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H5FSDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123SC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L152C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9D96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini58ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TLE9877QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C1299NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1299NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M453VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4N8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM4N8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG13P932F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P932F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P932F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L162QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG12B500F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1313FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC200SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11A14FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG840F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG840F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4500-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF368M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1764": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG14P632F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P632F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P632F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G8F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2D55J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL25Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F1765_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F207ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "PAC5220": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D31": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "NUC029FAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AE\\Include\\NUC029FAE.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NUC029AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "PAC5223": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NM1120EC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV10Z16xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKV_P16_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKV10Z1287.h", "define": "MKV10Z64xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MKW21Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "GD32F450VI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9AF131M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF131L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F427VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3U1E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1313FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF131K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BFD17S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "XMC1404-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BFD17T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52241_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKW22D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF567R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4LC4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32WG330F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF366K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4078FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL25Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S70": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF567N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF567M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC120VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKM33Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "M058SZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMV70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32MG12P232F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F215ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "M484SIDAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LPC11U23FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG995F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG995F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F215ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FDH20/002": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA0G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FBD48/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF117S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M453YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L152C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M452LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M0564LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M451VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM4F110H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F110H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L021G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4072FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK22FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12365_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LM3S9D90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF617S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF617T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H753XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32GG11B820F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20J17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1301-Q040x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F2451BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U37FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32PG1B200F128IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32WG895F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG895F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VE3DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B520F128GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG14P732F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAME53J20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F417VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L431VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG309F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG309F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F070F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L486VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L031E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM13Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM13Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F330R8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32LG280F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG280F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F733IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4315": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "QN9080A": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "QN9080C": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9080B": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54102J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U13FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKL43Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL43Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL43Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1512": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM3HMFDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U36FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF518S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F042C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "RC10001": {"core": "Cortex-M0", "vendor": "RelChip:146", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.relchip.com/Keil/RelChip.RC10000.1.0.0.pack", "compile": {"header": "Device/Include/RC10001.h"}, "pdsc_file": "http://www.relchip.com/Keil/RelChip.RC10000.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD/RC10001.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "4000000"}}, "STM32L031K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L031K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F330RB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "MKM34Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKV58F512xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV58F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x080000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV58F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S6952": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6952.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4CP16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF155R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG13P732F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMG55G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL27Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x400fe000", "size": "0x0200"}, "SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL27Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMR21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B820F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF521M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6V7": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32BG1B232F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S2608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6V2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC804M101JDH24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "MB9BF521K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF142N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM072FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M072.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG230F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4367": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "ARMCM33_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32LG395F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG395F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B540F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM372FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC8H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1R26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG330F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG330F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B320F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B320F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B320F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C29L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M451MRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MK22FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F042K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U35FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TC35678FXG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "TMPM367FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E1A11C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1112FHN24/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P832F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P832F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P832F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG13P632F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F50231_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L471VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R7AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG230F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "APOLLO256-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F1656": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG232F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG232F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1P133F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ARMCM33": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ADuCM361": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 512]], "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD/ADuCM361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "ADuCM360": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 512]], "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD/ADuCM360.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32LG990F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG990F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P431F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P431F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P431F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F212E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F212E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG14P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM390FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM39x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG290F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG290F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MIMX8MQ6xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MKL04Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "N571P032": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N571E000.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\N571P032_v3.svd", "processor": {"clock": "23000000"}}, "TMPM367FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M483SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32L152QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5956": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5956.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TC35679IFTG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "SN32F757F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MVF51NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NN151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "NANO120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM3S5951": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5951.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF315M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1404-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1937": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1937.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAM4E8E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG230F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LPC4078FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F479VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L152VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK02FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK02FN64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MK02F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F112C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F112C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F102C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4A6AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG842F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG842F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F102C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG1B200F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F102C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F111H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F111H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F190T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini55LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M481LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "XMC1201-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Z32F06423AKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF305N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG1P132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C1230H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1230H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MIMXRT1051xxxxB": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096], [1610612736, 262144]], "algorithm": {"arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}, "arm/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1051_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1051DVL6B"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1051_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x040000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MIMXRT1051.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "600000000"}}, "HT32F0008_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32TG11B340F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "A31G112": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536867328, 128]], "algorithm": {"A31G11x/Flashloader/A31G11x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G11x/Flashloader/A31G11x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G11x/Core/include/A31G11x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "A31G11x/SVD/A31G11x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC822M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC822.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NUC130VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B120F128GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V032F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V032F256GM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V032F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M052LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV31F512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F51212_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F512VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F51212_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MKV31F51212.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4S5QI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM3H5FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C59L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4SA16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG230F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG230F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK66FX1M0VMD18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK66F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "M0564LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO100LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F417IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC810M021FN8": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x00001000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/LPC810.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC123ZC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM4F122C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F122C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MVF50NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "EFR32BG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKE15Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE15Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}}, "debug": "MKE15Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMHA1G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}, "samha1a/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1a/svd/ATSAMHA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MVF60NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "EFR32FG1V232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1B231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2C18J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1115JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129LNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129LNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG222F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32MG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MD7xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MB9BF505N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F102CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL16Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD48/121": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F318C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM4G9F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54616J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54616J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54616.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S9B92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L432KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "CMSDK_CM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN256VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF116M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC220LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO110RE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32TG11B540F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK12DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1B21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1b21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E14FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F098CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM36BFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "PAC5210": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG11B540F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC126RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKW24D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW24D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32WG230F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF616S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK70FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF616T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32HG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32WG230F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG230F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2DH5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG11B420F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF618T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC120RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L452RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L452RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF618S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME51N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC11E68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG995F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG995F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32JG1B100F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC220VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F350C6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "SN32F236J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54618J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54618_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54618J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54618_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54618.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM366FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4E16E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4E16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1547JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32G800F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G800F128"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G800F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S67": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1232H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1232H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F105RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF154M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF154N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO102ZB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAM4S4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV70J19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70J19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "GD32F330K8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NANO120ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F401RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C129ENCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG110F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG110F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "AC30M1464": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1530VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B540F64IM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1654_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L081KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F031G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F0008_24QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F031G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF154R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11C14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6ZXR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZXR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C32E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32E_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4C32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW40Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW40Z4.h", "define": "MKW40Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW40Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L073RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L021D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "version": "0.1.0", "STM32L073RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG980F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG980F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG980F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG980F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "K32W042S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W042S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG295F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG295F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD18T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL33Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL33Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52241_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD20J14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4402-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F746IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BFD16T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S2D93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s2d93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F131C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F131C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMHA1E14AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "samha1b/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1b/svd/ATSAMHA1E14AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "Mini51XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BFD16S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32GG11B520F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C38H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK11DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F746IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG110F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1520RC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F50220_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "ATSAMD21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK51DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF566R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG14P231F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2HE6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF506N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG13P632F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF506R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC126VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F217VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC21J18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG230F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG230F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MKE04Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE04Z1284.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L476RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B110F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L476RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG14P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG332F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG332F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4C4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1751": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1751.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK60DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF314M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F2755_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B840F1024IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F318K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4504-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG390F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG390F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4337": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32L151CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV10Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV10Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKV10Z1287.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "XMC1404-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11A13FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F232E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M452LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L475ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F239F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4370": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32TG210F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF428T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32L041K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK20FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NANO130KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF105R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF568R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG940F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG940F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F268F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112LVFHI33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMHA1G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "samha1a/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1a/svd/ATSAMHA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF568N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F358RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF568M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL13Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL13Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL13Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ARMSC300": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMSC300/Include/ARMSC300.h", "define": "ARMSC300"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F765BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1653_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32FG14P232F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TMPM380FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F120H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F120H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4076FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1404-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM4LS4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMDA1G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C129EKCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129EKCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32JG1B200F256GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L486QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK10DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC442JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "STM32L100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011K3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC100LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L011K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1439": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1439.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DF5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ADuCM320i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320i.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF61NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NN151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "M451LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG940F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG940F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51822_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F412ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52354_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DH5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL82Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKL_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL82Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL82Z128VMP7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL82Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fffa000", "size": "0x018000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL82Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "96000000"}}, "EZR32WG230F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F205RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S10": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32PG1B200F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F205RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1810": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "NUC505DS13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC1812": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1813": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1815": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1817": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L162RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L475VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2U93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s2u93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NM1120TC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM036FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M036.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NM1520LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L162ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAML22J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1231D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AFB44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC4088FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1B232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F407VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L041E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F429IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC130LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F121B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F121B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F2755": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NM1120XC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC220LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC029TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1124JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x08000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F50220": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F091VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52230_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L471JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L471JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM4G9FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MVF50NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S9C97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9c97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F098RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 8192], [32768, 16384], [65536, 32768], [131072, 65536], [524288, 8192], [557056, 16384], [589824, 32768], [655360, 65536]], "algorithm": {"Flash/TMPM440_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "M487KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F767NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG11B120F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM462F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC4504-F144x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R9VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4R9I_EVAL.FLM": {"default": "0", "ramsize": null, "size": "0x04000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3S8B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EZR32WG230F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54605J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54605J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54605.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM074FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M074.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1302-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "SSE-200-MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.V2M-MPS3_SSE_200_BSP.1.0.0.pack", "compile": {"header": "Device/V2M-MPS3-SSE-200/SMM-SSE-200/Include/mps3_sse_200.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.V2M-MPS3_SSE_200_BSP.pdsc", "memory": {}, "debug": "SVD/MPS3_SSE_200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V131F32GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F32GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EZR32LG230F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "Mini58TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32WG230F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746BE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32WG230F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG360F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG360F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF368R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C49J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF368N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4N16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "Mini57XDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HC32M140J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32M140JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S8738": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8738.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ADuCM3027": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "ATSAMC21N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21N/ATSAMC21N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F50230_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG390F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG390F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52342_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1635": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1635.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM3029": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "STM32F100VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MKW21Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F130H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F130H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "SN32F7651BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L476ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F439BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32TG11B320F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini54TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "K32W032S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W032S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F110B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F110B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9G97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9g97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F50231_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C123BH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC130RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO130KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2C5AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F469NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F415VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "Mini51TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32ZG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F373C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG330F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG330F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GM8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM3HNFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F50220_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO100KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF505R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "nRF52832_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "IOTKit_CM23": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM23/Include/IOTKit_CM23.h", "define": "IOTKit_CM23"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L433VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21J17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF115M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMC20G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini55ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F072V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1V132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M058SSAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F413VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M487SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "MB9BF168N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF168M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F405VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F439BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F765ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF168R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAME70N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32HG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2GM8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM475FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EZR32WG230F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAM4N8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG332F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG332F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M485SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F101VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32H753VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32F101VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM383FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F301K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG14P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1960": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1960.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F52253_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F301K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F723VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F769BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF412R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMA5D33": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D33.svd", "processor": {"fpu": "DP_FPU"}}, "HC32F005C6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F005.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.1.0.0.pack", "compile": {"header": "Device/Include/HC32F005.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32F005.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC123ZC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC4200-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG110F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B540F64IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF412N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HC32L157KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L157KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAML22N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMV70Q20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70Q20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKL16Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SH32F205": {"core": "Cortex-M3", "vendor": "Sinowealth:149", "sectors": [[0, 2048]], "algorithm": {"Flash/SH32F2xx.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.sinowealth.com/ftp/tool/Arm32/Sinowealth.SH32Fxxx_DFP.1.0.0.pack", "compile": {"header": "Device/Include/sh32f2xx.h", "define": "SH32F2XX"}, "pdsc_file": "http://www.sinowealth.com/ftp/tool/Arm32/Sinowealth.SH32Fxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\sh32f2xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AFA32L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG890F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F423ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKW01Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW01Z4.h", "define": "MKW01Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKW01Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P431F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1100-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F120B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F120B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HC32L157K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L157KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3N0B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S817": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s817.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "M453VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "A33G526": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024], [251658240, 1024]], "algorithm": {"A33G52x/Flashloader/A33G527_DFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x0F000000"}, "A33G52x/Flashloader/A33G527_CFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "A33G52x\\Core\\include\\A33G52x.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "A33G52x\\SVD\\A33G52x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "A33G527": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024], [251658240, 1024]], "algorithm": {"A33G52x/Flashloader/A33G527_DFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x0F000000"}, "A33G52x/Flashloader/A33G527_CFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "A33G52x\\Core\\include\\A33G52x.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "A33G52x\\SVD\\A33G52x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LPC812M101JTB16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L151VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P333F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P333F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P333F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L151R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM366FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF122K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3S4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG840F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG840F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3S4A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3N1B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG110F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F334C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF144M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF144L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F107VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334C4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5K36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NANO120ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F479BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO100KC3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32MG12P432F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32FG1P131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9AFA32N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L462CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NANO120KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NANO100NC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S1N11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "R-IN32M4-CL2": {"core": "Cortex-M4", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [268435456, 131072]], "algorithm": {"Flash/R-IN32M4_MX25L6433F.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M4_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.1.0.1.pack", "compile": {"header": "Device/Include/RIN32M4.h", "define": "RIN32M4_CL2"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M4_CL2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG222F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HC32L110B4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110B.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1404-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F302K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M058LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF318S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFR32FG12P431F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S301": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s301.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S300": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s300.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F207VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F439AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B520F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HE4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HE4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1236E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1236E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21G18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1316FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FBD48/323": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32H743AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32JG12B500F1024GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "NM1120ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S1N16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG11B820F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKM38Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM38Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F0006_48LQFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM369FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1751": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F205VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F1755_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG395F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG395F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4312": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NUC505YO13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "MKM33Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_CM4": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC1825": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1827": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC54628J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54628.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LPC1820": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1823": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1822": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MCIMX7S3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "EFR32FG1P133F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG14P632F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK51DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9781": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9781.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL16Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1100-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1112FHI33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32HG322F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG322F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F132C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F132C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3HMFZDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4R9AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF367M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF367N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F411CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32G840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1100FBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG13P231F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L041F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F042G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F439ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L100R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM4G9FDXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO112SB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ARMCM4": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM0": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0/Include/ARMCM0.h", "define": "ARMCM0"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM3": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM3/Include/ARMCM3.h", "define": "ARMCM3"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EZR32WG330F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HC32M140F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32M140FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S328": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s328.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S5T36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s5t36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL36Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M2351KIAAEES": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "EFM32LG380F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG380F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4S5AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EFR32FG13P232F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P232F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P232F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11C14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADSP-CM419F": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[285212672, 4096], [285736960, 4096]], "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.1.3.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x11080000", "size": "0x00080000"}, "IRAM1": {"start": "0x200F0000", "size": "0x00008000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x11000000", "size": "0x00080000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L071KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC240LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "CMSDK_CM3": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM3/Include/CMSDK_CM3.h", "define": "CMSDK_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAMV71N20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71N20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MB9BF216S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NANO100KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EZR32LG230F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F51212_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN512VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F51212_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F51212.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6537": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6537.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9997": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9997.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG11B540F64GQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S2110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF114L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF114M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "HT32F1655": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32HG320F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG11B510F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3N1A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1E14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MKL26Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9869QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9869.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAM3S4B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKV11Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV11Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV11Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L083CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F230E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F230E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54101J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L083CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F769F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "XMC1402-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F373RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMG54G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32LG900F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG900F256"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG900F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4E8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F048C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52220_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1125JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL27Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL27Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F205ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C18L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKL43Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL43Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL43Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG222F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF129T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LPC1113FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF144N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK28FN2M0Axxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28FA15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK28FN2M0AVMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28FA15_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x34000000", "size": "0x080000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK28FA15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "EFR32FG1V032F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V032F256GM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V032F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1P131F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2C19H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L072V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "TMPM4G8FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG12P231F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMG55J19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S612": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s612.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F732RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG332F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG332F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15BU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15BU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC472JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "GD32F330G6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1231E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC131SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S617": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s617.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC804M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "MB9AF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG1V132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF50NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "M451MSC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F130C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "GD32F130C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMG53G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E13FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG108F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG11B120F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F190R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3Z26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s3z26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F190R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD51G18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51G18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32TG108F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF522L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF522M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3N0A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330C4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "MB9BF522K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F330C8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "Mini51ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "MK27FN2M0Axxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27FA15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK27FN2M0AVMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27FA15_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x34000000", "size": "0x080000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK27FA15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "TLE9867QXW20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F50231": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HT32F50230": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L4A6VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F330CB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMV70J20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70J20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F756NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "M451SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG230F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG230F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L452CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF132L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32HG309F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG309F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF132K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL13Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL13Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL13Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG110F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4300-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4300_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4300c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4300_series/Include/XMC4300.h", "define": "XMC4300_F100x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x0FFC0"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4300.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S3739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4500-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC442RI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "M0564RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF504R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM470FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F429II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32BG1P232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F405RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F768AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0564VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF504N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKV46F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV46F256VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV46F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "NM1330LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F405RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2C38J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F405RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1402-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK65FX1M0xxx18WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L451VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM330FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L451VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK63FN1M0xxx12WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK63FN1M0VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK63F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1301-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32HG310F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG310F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32FG13P231F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5R36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F50231_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F777II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC20E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF316M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL05Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F111E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F111E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M052LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG395F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG395F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5P31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMCM33_DSP_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MIMXRT1021xxxxx": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096]], "algorithm": {"arm/MIMXRT1021_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1021DAG5A"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x020000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MIMXRT1021.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "500000000"}}, "MK65FN2M0xxx18WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "MKL17Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL17Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S9AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG940F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG940F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M484SGAAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC120RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKL33Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL33Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L433CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L433CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C1232E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1232E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B820F2048GL192": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL192.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112RB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMD51J20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "HT32F52241_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F120E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F120E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32PG12B500F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54113J128": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54113J256UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54113.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "nRF52832_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F302ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC4074FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F235J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52331": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S310": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s310.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK20DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S316": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s316.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S317": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s317.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11E37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S315": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s315.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F207IF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK22DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF415R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMDA1G14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1G14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TMPM3H6FSDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG842F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG842F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52352_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71Q19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC1114FBD48/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini54ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M452SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L011E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM341FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM341_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "NUC121LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TLE9842-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285249536, 4096]], "algorithm": {"Flash/TLE9842_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x11009000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9842_2.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0xA000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52354_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1226FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F030C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG210F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MKV44F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD21E16BU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16BU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1P332F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG842F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG842F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F030C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1833": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1830": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW21D256xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1837": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11D14FBD100/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11D14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350K6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LPC18S30": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW36Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM461_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S37": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F22366_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F0008": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK51DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK11DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "XMC1402-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71N21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71N21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F0006": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL14Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF117T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F437IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "nRF52840_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\nrf52840.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F745ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1200-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMS70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F446ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M058LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32LG940F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG940F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H5FUDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F412VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO110SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F410R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4700-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM370FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE02Z16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "ATSAMD51N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L041G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442RG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "NANO102ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM3S818": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s818.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD10C14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG54N19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F042F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MM32x031": {"core": "Cortex-M0", "vendor": "MindMotion:132", "sectors": [[134217728, 1024]], "algorithm": {"Flash/MM32x031_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.1.0.0.pack", "compile": {"header": "Device/Include/MM32x031.h", "define": "MM32x031"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/MM32x031.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B540F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S2671": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2671.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1315FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S2678": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2678.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F745ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1824FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0519LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L4S5VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11U67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC120VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMV71J20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71J20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MK65FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "Generic_Mini51_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F042T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HC32F003C4UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F003.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.1.0.0.pack", "compile": {"header": "Device/Include/HC32F003.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32F003.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM32Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM32Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG13P733F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P733F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P733F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L083RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52344": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM46BF10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM46B_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}, "IRAM2": {"start": "0x20080000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M46B.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F479BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4S9VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5Y36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s5y36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9790": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9790.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F405VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1B132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC120RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L052C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F411VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM470FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1114FHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L052C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF366R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EZR32HG320F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKV30F128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV30F64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV30F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L471ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R7VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG230F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1317FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1225FBD48/321": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC1202-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1V132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M483KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LM3S828": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s828.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini57EDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32G880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MVF60NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "EFM32TG11B540F64GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF366N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1958": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1958.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF366L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF366M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG330F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG330F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG13P732F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF60NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF306N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F107F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F766BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC832M101FDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC83x.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F078VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF306R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4_FP.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "ADuCM320": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4700-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L051C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK60FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "M4TKLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC4500-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9879QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F101T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MK60FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S5C36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG360F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG360F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1112JHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9BN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE06Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE06Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE06Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE06Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "Mini57FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52344_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H0FSDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F130R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H1FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B340F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52231_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1302-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S5D91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32LG360F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG360F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2C49H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M4LEDLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "AC30M1432": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C48H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21E17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F755J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF324L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG14P733F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P733F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P733F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32PG1B100F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO110RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32WG890F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG890F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1230E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1230E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2DF5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4CMS32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMS32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMDA1E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F105V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini52ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAME53J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME53J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32LG390F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG390F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32PG12B500F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1202-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG14P732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M487JIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32JG12B500F1024IL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG390F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG390F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MAX32660": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32660.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32660.flash": {"default": "0", "ramsize": "0x00018000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32660/Include/max32660.h", "define": "MAX32660"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MAX32660/max32660.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "NANO110KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LPC54113J128BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKW36A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD51J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFR32FG1V131F32GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F32GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1114LVFHN24/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U35FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1100DBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1302-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M058SFAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1518JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC54605J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "HT32F52354_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L431RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M2351KIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "EFM32LG332F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG332F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F091CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32JG1B200F256IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF414R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG380F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG380F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF414N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMS70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L486RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9877QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "M452YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M451MLC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG14P231F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NANO100LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32MG1B732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK50DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM333FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM33x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1301-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL43Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL43Z4.h", "define": "MKL43Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MQ6xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "EFM32GG11B510F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM333FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG295F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG295F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1100XBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F745VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG942F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG942F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFR32FG1P131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG13P632F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32FG1P131F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2CC9H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKE15Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE15Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM": {"start": "0x1fffe000", "size": "0x8000"}}, "debug": "MKE15Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1767": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF514R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4N16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SN32F767BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P16_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B340F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71Q21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71Q21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKS22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS22FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS22F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1200TAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NM1530VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HC32L110C4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MKE14F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE14F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32GG11B510F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC123LD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TM4C123BH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F328C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "Mini58FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F212H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F212H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM4G8FDXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3HMFYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG295F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG295F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC472VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TMPM4G7FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1519JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S1165": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1165.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F030R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1162": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1162.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2HE6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L082CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F417ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F12365": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NANO112RC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAML22G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F768BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S9U92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B510F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G222F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G222F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MKL17Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL17Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5662": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5662.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L011D3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L476QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMHA1G15AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "samha1ab/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1ab/svd/ATSAMHA1G15AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F429IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L052R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F401CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "MK53DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK21DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71J19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71J19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32TG225F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG225F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3S8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L052R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F777NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7652BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1P232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32H753BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32PG1B200F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B120F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FBD100": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3J26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3j26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3U2E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U2E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32GG11B840F1024GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P133F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S8630": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8630.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Generic_Nano100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "NUC505DLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC1226FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32L496VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F765IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7741J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK81FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK81F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK81FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK81F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK81F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "STM32F303C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMV71J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "S6E2C39J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF518T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "SKEAZN64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO100SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32GG11B510F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F1765_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1B131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1B632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ISD9130": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF365L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF365K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG880F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG880F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF155N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1656_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TLE9871QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 32768]], "algorithm": {"Flash/TLE9871.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF155M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "Mini52ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M451VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG840F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG840F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG13P932F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P932F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P932F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4088FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058SLAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S102": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s102.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S101": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "S6E2D55G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL27Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x400fe000", "size": "0x0200"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL27Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0516ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC54114J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F733VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MK40DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x0008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC122SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "M453VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG1V131F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG1B132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2CC8L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4CMP16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG1B132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P233F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P233F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P233F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1227FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "M451LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG11B840F1024IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B520F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P732F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F207IC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LS8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F401RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32WG395F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG395F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108HB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG1B132F256GM56": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM56.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1302-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG232F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG232F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54605J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54605J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54605.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKV30F64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV30F64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV30F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMD21E16L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM369FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC20J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF112M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKE02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "arm/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4CP16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16B_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M2S090": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LM3S812": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52342": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAME53J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM4F121C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F121C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC140RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAME53N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M054LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO120LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NUC120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3H6FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M054LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1114FN28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F427IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMV70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F417ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF165K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMDA1E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF165L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3H6FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C1237H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG108F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32WG360F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG360F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAML21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM376FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA0J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B420F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG990F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG990F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MWPR1516xxx": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKPR1516_P16KB.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MWPR1516.h", "define": "MWPR1516xxx"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MWPR1516.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54101J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG1B232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451MLD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2CCAJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12366": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F52231": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52230": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG11B820F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1110FD20": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x1000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0400"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1200LAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW41Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F413ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMV71J21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71J21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKE06Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE06Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE06Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKE06Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "NUC200VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B120F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF521L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMV70N20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70N20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TMPM3HQFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMCM33_DSP_FP_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F334R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG14P532F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P532F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P532F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F031C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C59J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD51P20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F765NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32G842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B120F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG12B500F1024GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F070CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2939": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2939.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51P19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M0516ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF515N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF515R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32LG330F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P8_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00002000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G8FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMV71Q20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71Q20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "M482LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F429BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO100LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "M451LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM3S5P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG380F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG380F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5632": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG14P733F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P733F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P733F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC54606J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54606J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54606.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F303ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L443VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F150C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM411F20XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768], [0, 32768]], "algorithm": {"Flash/TMPM41xA_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM41xB_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM411_unitB.h", "define": "TMPM411F20XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20008000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54102J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG12P231F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P231F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P231F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK20DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG14P233F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P233F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM330FDWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54616J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54616J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54616.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32WG330F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG330F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TC35679FSG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "HT32F12345_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F746BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5D51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F247BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2GK8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4800-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L476VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HC32L110C6UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF468R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD20E17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM3S3W26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s3w26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B840F1024GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1B632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF468M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF468N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG395F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG395F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1R21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "RS14100_1MB": {"core": "Cortex-M4", "vendor": "Redpine Signals:125 ", "sectors": [[134291456, 4096]], "algorithm": {"Flash/RS14100_SF_1MB.FLM": {"default": "1", "ramsize": "0x4000", "size": "0xEE000", "ramstart": "0x00000000", "start": "0x08012000"}}, "debug-interface": [], "pack_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.1.0.2.pack", "compile": {"header": "Driver/Common/chip/inc/RS1xxxx.h"}, "pdsc_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x000000C", "size": "0x2FFF4"}, "IROM1": {"start": "0x08012000", "size": "0xEE000"}}, "debug": "SVD/RS1xxxx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF565L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F469ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1401-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B520F128IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini52XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC140RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32LG842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1290NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C123FH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123FH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC122SC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "ATSAM3N2A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F237F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1621": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1621.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1150": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1150.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1625": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1625.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF417S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1315FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S8530": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8530.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M453RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9BF417T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S8538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG842F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG842F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1V132F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F248F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL33Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL33Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1B132F256GD1": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GD1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L462RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG14P632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L011G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L496AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L011G3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMD21G15L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21G15L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1E14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F765ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M0516ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC4072FET80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG822F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG822F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG332F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG332F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0516LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9AFB44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F767ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32ZG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG380F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG380F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F32GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F32GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4800-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKV44F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "TMPM4G8FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F52243_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F350G6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "ISD9361": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9300_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9300_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9300_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "S6E2D55JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1D21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M482SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LM3S1D26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "GD32F350G4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LM4F212H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMV71J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F2755_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F769IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L475RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32G840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM4G7F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L475RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "IOTKit_ARMv8MML": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MML/Include/IOTKit_ARMv8MML.h", "define": "IOTKit_ARMv8MML"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1J16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1J11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F0006_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52342_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC122LC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "EFM32HG210F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG210F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S2616": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2616.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F1656_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NM1823LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC812M101JD20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S1Z16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s1z16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG330F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4500-E144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1P132F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKL36Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM373FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M373.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAML21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL27Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL27Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1317FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M2S150": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "STM32L071VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9843-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285261824, 4096]], "algorithm": {"Flash/TLE9843_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100C000"}, "Flash/TLE9843_2.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0D000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L071VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L051K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC126LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW35A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1655_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L051K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DH5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM4G9FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32MG1P132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L4R7ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LS8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G9F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F098VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S7VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54113J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54113J256UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.pdsc", "memory": {"SRAM2": {"start": "0x20020000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x20010000", "size": "0x010000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54113.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32H743ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMDA0J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1114FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L4R9ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F746NE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG14P231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32ZG110F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F769AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F405OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32LG230F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P632F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG380F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG380F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32ZG110F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S808": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s808.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F22366": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC11U14FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21J18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL17Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL17Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F072R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F230H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F230H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1237E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF364K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF364L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F215RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D42": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D42.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F215RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "nRF52810_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf52810.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "TM4C1237E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S6911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMD51G19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51G19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L072VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M483SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC120LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F150K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5P56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H14G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H14F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H14E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S32K148": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"addon_cmsis/Flash/S32K148_P1536_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x00000000"}, "addon_cmsis/Flash/S32K148_D512_4KB_SEC.FLM": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x0001F000"}, "IRAM2": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "platform/devices/S32K148/S32K148.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32F469IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKL33Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL33Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1403-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "HC32L150FA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMA5D44": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D44.svd", "processor": {"fpu": "DP_FPU"}}, "STM32L4A6QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D41": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D41.svd", "processor": {"fpu": "DP_FPU"}}, "TMPM3HQFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D43": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D43.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32GG290F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG290F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFR32MG1P632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M0516LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52243": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL16Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC11U24FHI33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L433RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LC2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL17Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL17Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC472KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TM4C123BH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F130F8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO130KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM342FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM342_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00009000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1402-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114JHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD21E15L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130F4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG11B120F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130F6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M481ZIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "TMPM36BF10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040800"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S9971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG825F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG825F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF111K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768], [537657344, 8192]], "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC240LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9AF111N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L4S5ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK12DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330F8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "XMC1201-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AC33M3064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F330F4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S2948": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2948.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9D81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F407ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO110RC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F429BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32WG330F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1202-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MIMX8MQ5xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ5DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ5.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "EFM32GG232F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG232F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F103R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1816": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1816.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F437VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F103R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MVF61NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NS151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F107VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM343FEXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_768.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC240LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMV70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32WG230F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG295F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG295F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "HT32F52352_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM3H1FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF416T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM3HMFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF416R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF416S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1112FD20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD20E18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF342M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SN32F249F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F410TB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG108F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG330F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H6FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1968": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1968.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF416N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EZR32LG330F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG390F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG390F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ML630Q466": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "sectors": [[0, 1024]], "algorithm": {"Flash/ML630Q466.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/ML630Q466.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q464": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "sectors": [[0, 1024]], "algorithm": {"Flash/ML630Q464.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/ML630Q464.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051K8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F051K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4074FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F051K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1330LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1330_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF217T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF217S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMV70N19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70N19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32FG1P132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK27FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27F15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK27FN2M0VMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27F15_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK27F15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "MB9BF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3HNFDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32BG1B232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000B800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF516N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2G38H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TM4C1233H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG11B340F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F107RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F107RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1518JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1548JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM4F210H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F210H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-T038x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF418S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2C28L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF418T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S32K146": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/S32K146_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000F000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "platform/devices/S32K146/S32K146.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "SN32F263X": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S32K144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/S32K144_P512_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "platform/devices/S32K144/S32K144.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32L475QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2G26J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L475QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2G26H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM4F112H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54605J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LM3S1637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Z32F38412ALS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 256]], "algorithm": {"Flash/Z32F3841.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F3841.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F3841.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK10DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F429VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini52TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LPC1112LVFHN24/003": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11U68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F22366_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MKL03Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S37": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "XMC1202-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Generic_NUC100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MIMX8MQ7xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "LPC845M301JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG1V131F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F50241_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKMP256_2KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34Z7.h", "define": "MKM34Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKM34Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32WG280F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG280F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM383FWEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B200F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG330F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK21FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F030F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG990F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F415RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9AFA41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL15Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG330F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG330F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "arm/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK66FX1M0VMD18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK66F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM330FYWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B540F64GM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AFA41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2HG6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F413CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2C2AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F170C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL25Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1W16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s1w16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M484KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F733ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L031G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5656": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5656.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F238F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L031G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F779BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11U24FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2793": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2793.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1401-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MBL/Include/CMSDK_ARMv8MBL.h", "define": "CMSDK_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F469VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C58H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "S6E2C3AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S628": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s628.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG895F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG895F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG895F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F469AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMS70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "APOLLO512-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "NUC130RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52231_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG12P332F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32G200F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G200F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL46Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL46Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL46Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1752": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM3H6FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1756": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1754": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L152RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011F3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1759": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1758": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1342FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L011F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMCA9": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA9/Include/ARMCA9.h", "define": "ARMCA9"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM23_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC1111FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5737": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5737.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5732": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5732.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCA5": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA5/Include/ARMCA5.h", "define": "ARMCA5"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M0518LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ARMCA7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA7/Include/ARMCA7.h", "define": "ARMCA7"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M452VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32LG232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52331_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9843QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285257728, 4096]], "algorithm": {"Flash/TLE9843_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100B000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9843.FLM": {"default": "1", "ramsize": null, "size": "0xB000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM4G8F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM4F132E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F132E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SKEAZN8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/SKEAZN84.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S8962": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8962.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4LEDRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F413ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG11B510F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F1765_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1100-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2D35JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG11B340F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37FBD48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5G51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM3S2730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "RS14100_4MB": {"core": "Cortex-M4", "vendor": "Redpine Signals:125 ", "sectors": [[134291456, 4096]], "algorithm": {"Flash/RS14100_SF_4MB.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x3EE000", "ramstart": "0x00000000", "start": "0x08012000"}}, "debug-interface": [], "pack_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.1.0.2.pack", "compile": {"header": "Driver/Common/chip/inc/RS1xxxx.h"}, "pdsc_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x000000C", "size": "0x2FFF4"}, "IROM1": {"start": "0x08012000", "size": "0x3EE000"}}, "debug": "SVD/RS1xxxx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM3S2A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "HT32F12365_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LM3S2739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK21DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MAX32630": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32630.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.0.0.1.pack", "compile": {"header": "Libraries/Device/Maxim/MAX3263X/Include/max3263x.h", "define": "TARGET=MAX32631"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32630/max32630.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32631": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32630.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.0.0.1.pack", "compile": {"header": "Libraries/Device/Maxim/MAX3263X/Include/max3263x.h", "define": "TARGET=MAX32631"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32630/max32630.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF329T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF329S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK11DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1227FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S6618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54102J256": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54102J512UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54102_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG1P132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM367FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3HPFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1201-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1P132F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G8F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC126RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF167R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F373V8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U36FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F111C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F111C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM366FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2139": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2139.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "EFR32FG12P231F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKW30Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW30Z4.h", "define": "MKW30Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW30Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P532F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P532F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P532F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF167N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF167M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S6100": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "S6E2GH6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2GH6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4S2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG108F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC834M101FHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC83x.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM3X8H": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8H.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "MKL15Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DF5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3X8E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAM3X8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1292NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12345": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M0516LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F110C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F110C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F373VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG980F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG980F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FDH20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H2FUQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F407IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32HG321F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG321F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F407IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32MG1P231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1115FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN128VMP10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG320F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2C39L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B310F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B310F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B310F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF318T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL05Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B120F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG332F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SD16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC4800-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "NANO120SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "XMC1302-T028x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-T028x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ND2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2GH8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF216T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2GH8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F103C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK50DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TC35678FSG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "LM3S6432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF129S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1821FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330G8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S2950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S613": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s613.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F330G4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF517S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF517T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9D92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S615": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s615.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M4LEDRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F479NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32BG1P333F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P333F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P333F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1626": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1626.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG11B140F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S1627": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1627.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54101J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54101J512UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54101.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM3SD8B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3SD8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAMC21J17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F301C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ARMCM0P_MPU": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h", "define": "ARMCM0P_MPU"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MB9BF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2CCAL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAML21E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG332F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG332F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C1AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2CCAH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF316S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF316R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF316T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9L97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AMAPH1KK-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 8192]], "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1113FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L162RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF500R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [16384, 49152], [65536, 65536]], "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M481ZGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32JG1B200F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F722VC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32BG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG11B520F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC845M301JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "TMPM475FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF500N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [16384, 49152], [65536, 65536]], "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF305R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F405VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M482SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32TG11B120F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F120C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F120C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG290F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG290F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11E14FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1294NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1311FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG995F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG995F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5C56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F103ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG12P433F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG980F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG980F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L451RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32H753AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFR32MG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAM4CMP8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM361FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC11U12FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32H753AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MKV31F256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKV31F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L496QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21G17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21G17AU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}}, "debug": "MKE14Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B820F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF467M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1302-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMHA1G16AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "samha1ab/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1ab/svd/ATSAMHA1G16AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG11B320F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F101RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32GG11B840F1024GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3N4B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x06000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3N/ATSAM3N4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC54114J256": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54114_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54114J256UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54114_DFP.pdsc", "memory": {"SRAM2": {"start": "0x20020000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x20010000", "size": "0x010000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54114_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S2918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK80FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK80F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK80FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK80F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK80F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "LM3S1607": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1607.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F439VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK50DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM330FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MIMX8MD6xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "STM32F302VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HC32F005C6UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F005.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.1.0.0.pack", "compile": {"header": "Device/Include/HC32F005.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32F005.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "R-IN32M3-CL": {"core": "Cortex-M3", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [33554432, 65536], [268435456, 8192], [268435456, 131072], [268500992, 65536]], "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_CL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F302VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F205ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F769NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1402-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L442KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L442xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1548JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF367R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F1655_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21G17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33_FP": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC120RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG320F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F52253_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC4400-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NANO100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG940F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG940F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F350G8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "STM32F103T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM4G9F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MK10DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK10DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini51ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMD20G15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446MC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "CMSDK_ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TM4C1237D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM375FSDMG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M375.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3N0C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1J15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LPC11E66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52354_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG11B320F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F330C6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "XMC1202-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32HG320F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1113FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L041C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE04Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKE04Z1284.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L041C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3HMFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini52XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM4G7FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMS70N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100ND3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F398VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F732ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F130E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F130E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1345FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM363F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M363.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S5651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F732IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5652": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5652.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF112L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HC32M140KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32M140KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4078FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H2FWQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F078RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM462F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG12P431F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM369FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF51NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NS151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S8971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8970": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8970.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1230D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1230D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HC32L150JA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11E67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAME54P20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "XMC1100-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MM32x103": {"core": "Cortex-M3", "vendor": "MindMotion:132", "sectors": [[134217728, 1024]], "algorithm": {"Flash/MM32x103_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MM32x103.h", "define": "MM32x103_MD"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/MM32x103.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NM1100XAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32LG230F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "LPC1113FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1401-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC822M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC822.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F479NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F52230_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MAX32621": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32620.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32620.flash": {"default": "0", "ramsize": "0x00020000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.1.0.2.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32620/Include/max32620.h"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32620/max32620.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32620": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32620.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32620.flash": {"default": "0", "ramsize": "0x00020000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.1.0.2.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32620/Include/max32620.h"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32620/max32620.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32626": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32625.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32625.flash": {"default": "0", "ramsize": "0x00028000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.1.0.0.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32625/Include/max32625.h", "define": "MAX32626"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MAX32625/max32625.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32625": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32625.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32625.flash": {"default": "0", "ramsize": "0x00028000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.1.0.0.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32625/Include/max32625.h", "define": "MAX32626"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MAX32625/max32625.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAML21J17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1343FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HC32L156JA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L156JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG280F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG280F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ISD9341": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "EZR32LG230F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM470FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ISD9340": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "Generic_M051_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L083V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123FE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123FE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HC32L150J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HC32L156J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L156JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1317FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1H11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1H16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMV70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC1347FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B420F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2410": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2410.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "R7S72103": {"core": "Cortex-A9", "vendor": "Renesas:117", "sectors": [[0, 4096]], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.RZ_DFP.1.1.0.pack", "compile": {"header": "Device/Include/RZ_A1LU.h", "define": "RZ_A1LU"}, "pdsc_file": "http://www.keil.com/pack/Keil.RZ_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x18000000", "size": "0x800000"}}, "processor": {"fpu": "DP_FPU"}}} \ No newline at end of file +{"S6E2H16E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H16G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1290NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG11B120F128IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC029LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG13P733F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P733F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P733F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMA5D26": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D26.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D27": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D27.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D24": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D24.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2H16F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMA5D22": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D22.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D23": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D23.svd", "processor": {"fpu": "DP_FPU"}}, "HT32F12345_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "IOTKit_CM33_FP_MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.1.0.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF317S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG390F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG390F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG290F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG290F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF317T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFR32BG14P632F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "AMAPH1KK-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 8192]], "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F423RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1237H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "N572P072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "TMPM3HNFYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF106R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F1655_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF415N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF106N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722RC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "HT32F1755_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F429ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4400-F64x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM383FSEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "AC30M1364": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG230F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG230F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F109F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG890F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG890F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LM3S2601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P133F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P133F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P133F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6422": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6422.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S6420": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6420.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG13P733F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P733F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P733F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MQ5xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ5DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ5.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "LM3S600": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s600.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK22FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F105R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK22FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM066FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M066.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F412VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B140F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NM1120ZC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "IOTKit_CM33_MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.1.0.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF328S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF328T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFR32BG1P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG942F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG942F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG13P632F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TLE9879QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MKV11Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV11Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKV11Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "HT32F52344_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D21": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D21.svd", "processor": {"fpu": "DP_FPU"}}, "STM32L451CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK02FN64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "arm/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK02FN64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MK02F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC1301-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKS20FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS20FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS20F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B510F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF529T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "Z32F06410AES": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF166R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF529S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "HT32F50231_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "GD32F150G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC2201LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC2201\\Include\\NUC2201.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG232F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG232F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK63FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK63FN1M0VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK63F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC230VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TMPM3H6FUDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F150G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F2755_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMA5D28": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D28.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F071RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK24FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK24FN1M0VLQ12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK24F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F2755_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO130KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "SN32F707F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMv8MML_DSP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M2351SIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "TMPM3H4FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMHA1G14AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "samha1ab/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1ab/svd/ATSAMHA1G14AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG11B320F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M4TKRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32LG295F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG295F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9844QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285274112, 4096]], "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844.FLM": {"default": "1", "ramsize": null, "size": "0xF000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE9844_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100F000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0x10000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM3H4FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG225F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG225F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF128S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM395FWAXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM395_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFR32BG1P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF128T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK22DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S308": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s308.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "nRF51422_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51422_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51422_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F50241": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "HC32F146J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32F146JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK60DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM061FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M061.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F52253_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG900F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG900F256"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG900F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG220F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52352_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1202-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK52DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK52D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG220F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7661BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMSC000": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMSC000/Include/ARMSC000.h", "define": "ARMSC000"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC000.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM462F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK82FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK82F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK82FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK82F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK82F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "MKE04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": "0x400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z8VWJ4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffff00", "size": "0x0400"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKE04Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P532F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P532F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P532F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C129DNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG390F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG390F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAML22N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F766J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MIMX8MQ7xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "M453YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2CC8J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52253": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKV56F1M0xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV56F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "SRAM_OC": {"start": "0x2f000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x100000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV56F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "TM4C1230C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1230C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F121E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F121E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32L031C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5G36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F410CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG1B232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5G31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1292NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ISD9160": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "EZR32WG230F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F267J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B200F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN256VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1102LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M0519VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52344_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4327": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F446ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F302CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F446ZC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1654": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKE14Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM": {"start": "0x1fffe000", "size": "0x8000"}}, "debug": "MKE14Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MKE16F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE16F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE16F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F303VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F777BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5R31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1236D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1236D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B420F2048IL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG230F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1102UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG330F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG330F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL05Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM376FDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MAX71617": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71616": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "EFR32MG1P232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG230F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG230F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F1653": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFB42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Z32F06423EKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TLE9873QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 45056]], "algorithm": {"Flash/TLE9873.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100AFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0xAFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM3HNFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM380FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TLE9845QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285257728, 4096]], "algorithm": {"Flash/TLE9845.FLM": {"default": "1", "ramsize": null, "size": "0xB000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9845_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100B000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG942F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG942F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32HG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32FG13P231F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F407IE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG11B120F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9867QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B140F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11C12FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC200SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG220F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1778": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F122H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F411RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1774": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1777": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1776": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F411CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM3H3FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC240SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2C29H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52341_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG390F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG390F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5752": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5752.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F427II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M4TKVG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NM1120XB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Mini54ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMD21G16L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21G16L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52231_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MT2523x": {"core": "Cortex-M4", "vendor": "MediaTek:129", "sectors": [[134217728, 4096]], "algorithm": {"tools/keil/mt2523/2523_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x04008000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.6.1.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt2523/Include/mt2523.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x00400000"}, "IRAM2": {"start": "0x04008000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00400000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "208000000"}}, "STM32F410C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC11A12FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMD21G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F50241_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F378VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1J14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1J14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFR32MG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMDA1J14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1J14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "XMC1402-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M058LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F446RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32LG330F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2412": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2412.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EZR32LG330F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MML_DSP_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM067FWQG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M067.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32TG822F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG822F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C129XNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129XNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMR21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F108F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H3FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C58J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S050": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "S6E2C3AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG395F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG395F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32G880F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G880F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F407VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX7D2": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D2_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "MCIMX7D5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "EFM32TG11B320F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX7D7": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D7_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NANO112LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG895F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG895F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG990F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG990F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG980F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG980F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC472HI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "ATSAME70J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TLE9842QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285245440, 4096]], "algorithm": {"Flash/TLE9842_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x11008000"}, "Flash/TLE9842.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x9000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EFM32GG11B840F1024GL192": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL192.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H4FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52243_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F479AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F407VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HC32L156K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L156KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4088FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC130LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F100RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1120TB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ADSP-CM419F-BCZ_M0": {"core": "Cortex-M0", "vendor": "Analog Devices:1", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x200F0000", "size": "0x00008000"}}, "debug": "SVD/CM41x_M0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "M453LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC1100-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F479ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32TG11B320F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HC32L156KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L156KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1101LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D35": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D35.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D34": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D34.svd", "processor": {"fpu": "DP_FPU"}}, "TM4C1231H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D36": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F450VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S2911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F038C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG895F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG895F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG895F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HC32L150KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32FG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B420F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B820F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F423CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC11U12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG11B340F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M052ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC126LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM384FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM38x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M384.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F469ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32GG11B110F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F479IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC442KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EFM32G290F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G290F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1232D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1232D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM4G8F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC844M201JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F767BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1200ZBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F423VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32G222F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD09C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD09_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD09\\ATSAMD09C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4CMS16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F038K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M052ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG900F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG900F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMV71N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32LG990F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG990F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0519SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L432KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK11DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK11DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L081CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL28Z512xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512_KL28.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL28Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL28Z512VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL28Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fff8000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}}, "debug": "MKL28Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF112R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM368FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG13P732F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F1755_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11C22FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKS22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS22FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS22F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B520F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO102SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "HT32F52220_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B100F128IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC472VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "GD32F330K4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "GD32F330K6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "TMPM3H2FSDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMV70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "XMC1302-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL36Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4104-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF314R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L152C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG942F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG942F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG295F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG295F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21E18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC802M011JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "STM32L152V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAM4SD32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD32B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L443RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L100C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F217IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F706J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG14P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P632F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F112E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F112E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK26FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK26F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK26FN2M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK26F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK26F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F52241_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1765_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2DH5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC811M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00002000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/LPC811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFM32LG840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF105N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M451MRD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG1P131F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD09D14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD09_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD09\\ATSAMD09D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F150R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1313FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L476ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG13P632F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F150R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM4S4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5D56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F52220_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF464K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4S4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F121H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F121H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG890F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG890F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG980F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG980F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G6FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG1P131F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F210E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F210E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F22366_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "XMC1202-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C1AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B820F2048IL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC8N04FHI24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8N04_30.FLM": {"default": "1", "ramsize": null, "size": "0x00007800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC8N04.h", "define": "LPC8N04FHI24"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00007800"}}, "debug": "SVD/LPC8N04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "8000000"}}, "LPC1114FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F232H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4317": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4310": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC1114FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4313": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAMD21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21J18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52341": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2B93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2b93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MIMX8MD6xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MB9BF528T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF528S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "NUC123ZD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32G880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1823EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1P132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L151UC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC140VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F50230_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L462VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1B232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9AF341L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54113J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF341N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1251": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1224FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LPC11E11FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF516S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F1253": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32BG12P232F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF62NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF62NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF406R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC472KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "STM32F101CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF406N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1225FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S5P36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3H1FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C18H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF516R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32G842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52230_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S800": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827UB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC120RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MK22FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S801": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s801.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2C19L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG11B520F128IM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54P19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKL02Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffff00", "size": "0x0400"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "Generic_NUC400_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TM4C1294KCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1294KCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1402-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F401RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32GG840F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG840F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M451MLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LPC804M111JDH24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFR32BG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F12365_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "SN32F707BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4700-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9BN2": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U14FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L431KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9BN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG14P732F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC100VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Generic_NUC200_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC123SD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F051T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1120EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMDA0E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MBL/Include/ARMv8MBL.h", "define": "ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32L152RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G200F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32G/EFM32G200F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1755_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "SN32F765J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG290F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG290F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKW21D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P133F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "Mini51XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S5P3B": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1768": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1769": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM366FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1763": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "Mini52FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F101C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1766": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKE16F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE16F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE16F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32GG380F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG380F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1765": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S5747": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5747.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L475JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG14P532F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P532F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P532F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L475JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NM1200LBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11U35FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P231F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM3HPFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F378CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1785": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1786": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1787": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x000020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x000004000"}, "IRAM2": {"start": "0x20080000", "size": "0x000004000"}, "IROM1": {"start": "0x00080000", "size": "0x000020000"}}, "debug": "SVD/SAM3U/ATSAM3U2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAM4LS2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L063R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1788": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG1B132F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4200-Q48x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "N572F072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MCIMX7U5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NUC121ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MCIMX7U3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "STM32L071RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG980F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG980F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG940F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG940F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F131H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F131H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4LS2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32H743VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32WG990F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG990F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L471RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B840F1024IL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L471RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC240SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F450ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "NUC2201SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC2201\\Include\\NUC2201.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F723ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11U34FHN33/311": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC220LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9AFB41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F412CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1114FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L052K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B231F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B231F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BFD18S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAML21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG822F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG822F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM367FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG14P231F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG280F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG280F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM369FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TM4C123BE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG350F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG350F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F215VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM3H2FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F756IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S1F11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK65FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "arm/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "NUC122ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "ATSAM4LS8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKS20FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS20FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS20F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C49L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC812M101JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F767ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M452VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9BF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F479ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF315R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9AF312K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG321F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG321F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM3H2FUDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11E14FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F413VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32PG12B500F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini54XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1233H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1302-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F778AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2CC9J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "Mini51LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LPC11A14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1G21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1g21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1115JET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC220LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P332F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L053C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMR21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108CZ": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [134481920, 16]], "algorithm": {"Flash/STM32W108_192.FLM": {"default": "1", "ramsize": null, "size": "0x30000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x08000000", "size": "0x30000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2D55GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L053C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC122ZC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "XMC1201-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S30": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1231H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [134481920, 16]], "algorithm": {"Flash/STM32W108_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32W108CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F437II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114LVFHN24/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F264S/X": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK10FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54102J512": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54102J512UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54102_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F413CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1V131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F350K8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "ATSAMV71N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ARMCM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM372FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3H0FMDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_8.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/M3H0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG890F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG890F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M0519SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S1332": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F231E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F231E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM3N1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9879QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM368FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TLE9867QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "NM1520LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F301C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK21DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E1A11B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAM4LC8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3748": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3748.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO102LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "MB9BF321K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM037FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M037.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKL26Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GK6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NM1820EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2GK6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F437ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV42F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F437ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1517JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F12366_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NUC120LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F150K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21E18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B420F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAMD21J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0518SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW31Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6X4": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC1112FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6X1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X3": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "S6E2D35GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32G232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG13P632F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1200TBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1401-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C5AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F103ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4R5VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B320F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B320F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B320F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20N/ATSAMC20N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF512R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L100RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S3634": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123AE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123AE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1112FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2GM6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini51LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F103V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F50241_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "M054ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF512N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S1850": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1850.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG280F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG280F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52354": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20N/ATSAMC20N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4320": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4323": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4322": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4325": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F302CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG990F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HC32F146F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32F146FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG295F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG295F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32GG940F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG940F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3A8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3A8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TMPM3H1FPUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 16384], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_48.FLM": {"default": "1", "ramsize": null, "size": "0x0000C000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x0000C000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK64FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK64FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK64F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5K31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG1V131F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKE18F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE18F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE18F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD51J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F777VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM3U1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "Mini57TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32WG880F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG880F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG14P732F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P732F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P732F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L486JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ADSP-CM419F-BCZ_M4": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[285212672, 4096], [285736960, 4096]], "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "0", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M4/CM41x_M4_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.pdsc", "memory": {"IROM2": {"start": "0x11001000", "size": "0x000FF000"}, "IRAM1": {"start": "0x10000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20010000", "size": "0x00018000"}, "IROM1": {"start": "0x11000000", "size": "0x00001000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S5G56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1404-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV10Z32xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKV_P32_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKV10Z1287.h", "define": "MKV10Z64xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LM3S1911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B420F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F12366_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F446VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F722IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM367FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG1B132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F245J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAM3A4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3A4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMD11C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD11_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HC32L110C6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC804M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFM32WG895F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG895F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Z32F12811ARS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F469IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C28J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12345_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1114FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11E36FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S2B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "NUC120RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG232F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG232F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C59H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF465K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F1252": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF465L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL81Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKL_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL81Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL81Z128VMP7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL81Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fffa000", "size": "0x018000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL81Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAMV70Q19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [4194304, 8192], [4194304, 8192], [4194304, 8192], [536870896, 16], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70Q19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "Mini51TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAM4CMP32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMP32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3H5FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S5C31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG1P132F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F705J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4400-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "S6E2DF5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L4R5QI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM370FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG395F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG395F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M485KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "XMC1301-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F131E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F131E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO112VC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMV71N19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71N19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TM4C123GE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C29J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L162ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM4LC2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG895F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG895F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG14P231F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG880F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG880F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK40DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SKEAZN16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO110KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF311K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768], [537657344, 8192]], "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG840F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG840F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG220F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451MRC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC120LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Mini58LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ARMCM0P": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h", "define": "ARMCM0P_MPU"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LM3S2776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M052LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B510F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC131SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG13P732F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD10D13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL04Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2G28J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F773T": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G210F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G210F128"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G210F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MAX71637": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71636": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MK21DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG840F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG840F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 8192], [32768, 16384], [65536, 32768], [131072, 65536], [524288, 8192], [557056, 16384], [589824, 32768], [655360, 65536]], "algorithm": {"Flash/TMPM440_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "LM4F111B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F111B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F0008_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM3H5FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11D14AM": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE18F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE18F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE18F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD11D14AS": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21N/ATSAMC21N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1294NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A04UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini52TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32GG11B840F1024IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAME51J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C129CNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1403-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F122E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F122E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK64FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK64FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MK64F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9L71": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l71.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG14V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14V/Include/em_device.h", "define": "EFR32FG14V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14V/EFR32FG14V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F415OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32LG380F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG380F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1302-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMS70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC11U35FET48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC240VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F1656_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33MA384A": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 256]], "algorithm": {"AC33MA384A/Flashloader/AC33Mx384A_384.flm": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33MA384A\\Core\\include\\AC33Mx384A.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33MA384A\\SVD\\AC33Mx384A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B820F2048GL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P431F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HC32L110B6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110B.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32FG1V131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG308F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG308F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1549JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG942F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG942F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024GL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF341M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3X4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC11E67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG890F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G6FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC123SC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M481LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "ATSAMD21G18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21G18AU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F773S": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F732VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M2351ZIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "XMC1302-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F078CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3826": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s3826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12366_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC43S20": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG980F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG980F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F405ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B95": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b95.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114LVFHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9B96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32G230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52331_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L051R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1B132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM3HQFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4108-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L051R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1520RD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L083RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK11DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMG54J19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAMDA0G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1V131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L152VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG12P232F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKM33Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF114R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F50220_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "PAC5250": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H46F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11U24FET48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D35J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG895F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG895F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG880F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG880F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM461_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B110F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L452VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG222F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAME70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L452VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9GN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9gn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1231C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1231C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG14P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG825F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG825F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG11B820F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P732F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F303R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M0516LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF312R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F303R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230RC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F469NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1224FBD64/121": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC4104-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LPC51U68": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC51U68_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC51U68_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC51U68JBD64"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC51U68_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC51U68.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B540F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMDA0J14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F2641J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD64/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "MK20DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F330F6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "GD32F130K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F407ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B420F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM365FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M365.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM0plus": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM0plus/Include/CMSDK_CM0plus.h", "define": "CMSDK_CM0plus"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0plus.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "GD32F130K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3H3FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F130K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1510LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B520F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6Y7": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F302R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C129DNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "R7S72100": {"core": "Cortex-A9", "vendor": "Renesas:117", "sectors": [[0, 4096]], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.RZ_DFP.1.1.0.pack", "compile": {"header": "Device/Include/RZ_A1H.h", "define": "RZ_A1H"}, "pdsc_file": "http://www.keil.com/pack/Keil.RZ_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x18000000", "size": "0x800000"}}, "processor": {"fpu": "DP_FPU"}}, "MCIMX6Y2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y0": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32L073VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F12366_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "SMM-SSE-200": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.V2M-MPS2_SSE_200_BSP.1.0.3.pack", "compile": {"header": "Device/V2M-MPS2-SSE-200/SMM-SSE-200/Include/mps2_sse_200.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.V2M-MPS2_SSE_200_BSP.pdsc", "memory": {}, "debug": "SVD/MPS2_SSE_200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "20000000"}}, "STM32F779NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV44F64xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32FG1V131F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F072CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF524K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF524L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF524M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF466N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F407ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMR21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5B91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5b91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DL13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "EFM32TG11B140F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1P132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF466R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG995F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG995F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EZR32WG330F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK21FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG995F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG995F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54628J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54628_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54628J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54628_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54628.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF514N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG842F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG842F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32HG108F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG108F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C123GH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32MG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC121SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F072C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52243_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123ZD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32BG14P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P732F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F52342_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC123LC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32BG1P232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMC21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD10C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO100SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32WG840F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG840F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SA16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG290F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG290F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F030K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3HNFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DSA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC845M301JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MB9BF404R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C4AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF404N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4800-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "GD32F350C4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "EFM32TG11B520F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2G36J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32MG13P832F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P832F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P832F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2G36H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKM14Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F758F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350C8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "NANO110RD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MIMXRT1051": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 262144]], "algorithm": {"Flash/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.1.0.2.pack", "compile": {"header": "Device/Include/MIMXRT1052.h", "define": "MIMXRT1052"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IRAM2": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MIMXRT1051.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F765II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MIMXRT1052": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 262144]], "algorithm": {"Flash/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.1.0.2.pack", "compile": {"header": "Device/Include/MIMXRT1052.h", "define": "MIMXRT1052"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IRAM2": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MIMXRT1052.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M4LEDLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG842F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG842F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC131LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "nRF51802_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F52241": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L475ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF428S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "DS_CM3": {"core": "Cortex-M3", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.1.1.0.pack", "compile": {"header": "Device/DS_CM3/Include/DS_CM3.h", "define": "DS_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.pdsc", "memory": {}, "debug": "SVD/DS_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC4333": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4330": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "SN32F774T": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F774S": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ARMv8MML_DSP_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F132H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051R4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1E15AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "samha1b/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1b/svd/ATSAMHA1E15AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F051R6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV46F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV46F256VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV46F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F358VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MIMXRT1052xxxxB": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096], [1610612736, 262144]], "algorithm": {"arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}, "arm/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1052_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1052DVL6B"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1052_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x040000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MIMXRT1052.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "600000000"}}, "EFM32G200F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G200F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG13P732F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U24FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1225FBD64/321": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "EFR32FG1P131F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F350CB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "nRF51824_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32GG11B310F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B310F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B310F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MKV10Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV10Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV10Z1287.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "EFR32MG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P231F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S8730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8733": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8733.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M451LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EZR32HG320F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1765": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M452LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG840F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG840F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO100SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S8933": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8933.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NM1823ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S8930": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8930.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG232F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG232F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "A31G122": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536866816, 128]], "algorithm": {"A31G12x/Flashloader/A31G12x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G12x/Flashloader/A31G12x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G12x/Core/include/A31G12x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "A31G12x/SVD/A31G12x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "A31G123": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536866816, 128]], "algorithm": {"A31G12x/Flashloader/A31G12x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G12x/Flashloader/A31G12x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G12x/Core/include/A31G12x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "A31G12x/SVD/A31G12x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C129ENCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1345FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK60DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MCIMX7S5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "MKW41Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG232F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG232F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U4E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256], [1048576, 256]], "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M052ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1100-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1112FHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM4050": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM4x50.FLM": {"default": "1", "ramsize": null, "size": "0x7F000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM4050.h", "define": "__ADUCM4050__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x7F000"}}, "debug": "SVD/ADuCM4050.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "52000000"}}, "LPC54607J256BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EZR32HG220F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1857": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1850": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1853": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC18S50": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM0": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM0/Include/CMSDK_CM0.h", "define": "CMSDK_CM0"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TLE9861QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 32768]], "algorithm": {"Flash/TLE9861.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC18S57": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1549JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F450IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM4F211H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F211H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F450IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M058LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F450II": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC54618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "MB9BF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1B131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF121J": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9B120J_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xJ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC20J18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P232F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F0008_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFR32MG1P232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKV31F128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F128VLL10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV31F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "HT32F52344_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21E19A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E19A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C129XKCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129XKCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F130C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F130C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3N00B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N00A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC54606J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54606J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54606.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM3H4FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2G38J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NM1820LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC4108-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5762": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5762.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M052ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F038F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F102R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F767F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M481SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32ZG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F779II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG942F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG942F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F100C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1112FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52352": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK24FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F25612_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK24FN256VDC12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK24F25612.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F22366_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MKM33Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAME54N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKL15Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6753": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6753.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3X4E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "NUC100RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M2S005": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LPC11U34FBD48/311": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF141N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1B232F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E1A12B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG230F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG230F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG330F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S57": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC43S50": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "EFR32BG1B132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC140LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L021F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4500-F144x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54016": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54016_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54016JET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54016_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54016.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S8938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P233F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F413MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG14P733F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P733F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P733F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L485JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L485xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F413MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54606J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32L443CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F303C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME51J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EZR32WG330F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE14F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32LG330F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F091RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F102RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G890F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G890F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2276": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2276.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32ZG108F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1233C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1233C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM475FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9844-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285274112, 4096]], "algorithm": {"Flash/TLE9844_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100F000"}, "Flash/TLE9844_2.FLM": {"default": "1", "ramsize": null, "size": "0xF000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0x10000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMC21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52253_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M0516ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMV70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F1653_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1517JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG232F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG232F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F072RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F150C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33M6128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1343FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2GK8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A12FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4076FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F150C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3U4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256], [1048576, 256]], "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32LG895F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG895F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F071VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF565K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG14V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14V/Include/em_device.h", "define": "EFR32FG14V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14V/EFR32FG14V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD51N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NANO100NE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF344N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1120DC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF322K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F410T8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TLE9877QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF322L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF322M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ISD9360": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "M4TKLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKL46Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL46Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL46Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L062K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L062xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L062x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFR32FG1V132F32GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F32GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKL24Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S3654": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U14FET48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S3651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52341_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1251B": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF115R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM3H2FSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F103T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32BG1B232F256GM56": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM56.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5U91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5u91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451MSD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F103T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F723IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F101R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "HT32F50241_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F101R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "XMC1302-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LM3S1651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM330_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F437VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A02UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F265J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC131LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32WG230F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52243_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1P332F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L073CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F350R4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "GD32F350R6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LM4F122H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F350R8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "GD32F170C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C2AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MK53DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B520F128IQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1104UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L073CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F405ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4R5AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW31Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG995F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG995F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9792": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9792.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG880F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM366FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SP32A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4SP_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4SP/sam4sp.h", "define": "__SAM4SP32A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4SP/ATSAM4SP32A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1P732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "Z32F12811ATS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK12DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350RB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "EFM32GG11B120F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F415ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F1654_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF156R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1316FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1V132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U14FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F247F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827YB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L162RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3HPFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG310F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG310F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMR21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF467R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C123GH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32L476ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF467N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F101RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM068FWXBG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M068.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Z32F06410AKS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53N19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B540F64IQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "AC33M8128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3HNFZDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TMPM4G6F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG13P232F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P232F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P232F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F768F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123GH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC802M001JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFR32FG13P233F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P233F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P233F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C1297NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1297NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F745IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "IOTKit_ARMv8MBL": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MBL/Include/IOTKit_ARMv8MBL.h", "define": "IOTKit_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L152VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC200SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MK20DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P132F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC824M201JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC824.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F105VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LPC54005": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54005_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54005JET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54005_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54005.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC802M001JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "STM32F777ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM343FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S815": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s815.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD10D14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG51N18": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51N18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L063C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S3N26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s3n26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF516T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG11B520F128GM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F248BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54616J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32WG942F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG942F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129CNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF405R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54607J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54607J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54607.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "A31G111": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536867328, 128]], "algorithm": {"A31G11x/Flashloader/A31G11x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G11x/Flashloader/A31G11x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G11x/Core/include/A31G11x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "A31G11x/SVD/A31G11x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M4TKVE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L082KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F12365_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F103RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF156N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG14P232F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SKEAZN32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "SN32F759F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54101J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54101J512UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54101.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF405N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L082KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1115FET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F358CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFA31N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM362F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M362.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG842F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG842F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG280F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG280F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AFA41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4S16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B520F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472HG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "MB9BF429S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32LG330F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG330F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF429T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "M054ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M052LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F378RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG12P431F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L152R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M481SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC100LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV58F1M0xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV58F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "SRAM_OC": {"start": "0x2f000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x100000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV58F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "HT32F52220": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32MG14P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B110F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "AC33GA256": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024]], "algorithm": {"AC33GA256/Flashloader/AC33GA256_CDFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33GA256\\Core\\include\\AC33GA256.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33GA256\\SVD\\AC33GA256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32JG12B500F1024IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120DB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3H4FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A11FHN33/001": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1435": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005C00"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1435.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TMPM341FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM341_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "S6E2C2AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG360F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG360F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2H46E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG900F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG900F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG350F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG350F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini54TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LM3S5791": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5791.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C39H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM3H4FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1320LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1320_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1320_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1320_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NM1320AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO103SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1202-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG13P732F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4800-E196x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM364F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M364.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ARMCM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC812M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F413RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F038G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MIMX8MD7xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "NUC120VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "K32W022S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W022S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MK20DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32L053R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F246BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1549JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M0564RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Musca": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [[2097152, 65536]], "algorithm": {"Flash/MT25QL512_DC.FLM": {"default": "1", "ramsize": "0x00020000", "size": "0x10040000", "ramstart": "0x20000000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.Musca_A1_BSP.1.0.2.pack", "compile": {"header": "Device/Include/system_cmsdk_musca.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.Musca_A1_BSP.pdsc", "memory": {}, "debug": "SVD/Musca.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F091CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450ZI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F405OE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32WG360F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG360F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMHA1G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "samha1a/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1a/svd/ATSAMHA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG222F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F439NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "GD32F450ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MAX32652": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "M2S010": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "MAX32650": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MAX32651": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "nRF51801_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F439NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAML22N16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22N16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK70FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG295F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG295F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S32K142": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"addon_cmsis/Flash/S32K142_P256_2KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "platform/devices/S32K142/S32K142.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32L072RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF321M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF321L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1547JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MK20DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO120LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MKE02Z64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1236H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1236H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1112FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L051T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1112FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F413RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F301R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC824M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC824.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F301R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L072RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME51N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NM1120FC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L051T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3H5FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF116S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC54101J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E1A12C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF116T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L152RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1402-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG332F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32L152RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "NUC240SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LPC54114J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM333FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM33x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32LG330F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF218S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF218T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H743BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MB9AF131N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HC32F003C4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F003.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.1.0.0.pack", "compile": {"header": "Device/Include/HC32F003.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32F003.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L4S7AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4TKRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32TG825F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG825F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128GQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKE02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}, "arm/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "M0519LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F706BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F048G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG995F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG995F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1232C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1232C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MVF50NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMHA1E16AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "samha1b/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1b/svd/ATSAMHA1E16AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFR32MG12P432F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMC20J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D55GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F767VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4078FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M0518LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F031K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME53N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "ARMCM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "NANO112SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "AC30M1332": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32PG1B200F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM4G9F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM37AFSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M37A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF118S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF118T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC220SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMD21G15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F746VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG11B420F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F031E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6633": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6633.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32GG380F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG380F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF121M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG990F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG990F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C38L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG995F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG995F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F170R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM374FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M374.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF141L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF141M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3S1A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S1B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKL26Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL26Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL26Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HC32F146KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32F146KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM3HMFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "N572F065": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\N572F065_v3.svd", "processor": {"clock": "48000000"}}, "LPC844M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "HT32F50220_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG11B820F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H44F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H44G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L4A6ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2H44E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54113J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32LG940F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG940F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW35Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO103LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F746VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L162VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F779AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E36FHN33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMC21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32L031F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B540F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "BlueNRG-1": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[268697600, 2048]], "algorithm": {"Flash/STBlueNRG1.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x28000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.1.1.1.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x28000"}}, "debug": "SVD/BlueNRG1.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MCIMX7D3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NANO120SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "BlueNRG-2": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[268697600, 2048]], "algorithm": {"Flash/STBlueNRG2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG-2_DFP.1.0.0.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG-2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x40000"}}, "debug": "SVD/BlueNRG2.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MB9BF564L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "MB9BF564K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F50230_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF156M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "R-IN32M3-EC": {"core": "Cortex-M3", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [33554432, 65536], [268435456, 8192], [268435456, 131072], [268500992, 65536]], "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_EC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "AC33M4064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B420F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123AH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123AH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKL14Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}, "arm/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC802M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFM32PG1B200F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC122LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "HT32F5826": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F5826"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F5826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TM4C1299KCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1299KCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F756J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF312L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54608J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54608_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54608J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54608_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54608.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO130SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "HT32F1755": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini54XFHC": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW20Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW20Z4.h", "define": "MKW20Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW20Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F058C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4350": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MK64FN1M0VLL12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.2.3.0.pack", "compile": {"header": "platform/devices/fsl_device_registers.h", "define": "CPU_MK64FN1M0VLL12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "platform/devices/MK64F12/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4353": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO102LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LPC4357": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MT7687F": {"core": "Cortex-M4", "vendor": "MediaTek:129", "sectors": [[268435456, 4096]], "algorithm": {"tools/keil/mt7687/7687_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.6.1.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt7687/Include/mt7687.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x00100000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00200000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "192000000"}}, "TM4C1233E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54607J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54607J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54607.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKV42F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "LPC54101J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4502-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2DH5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F350K4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "NM1100FAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM343F10XBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV42F64xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "MKM14Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P131F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F401VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "Mini55TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F423MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKL34Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL34Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL34Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL34Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL34Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6G1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "S6E2C3AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX6G3": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TMPM462F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54018": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54018_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54018JET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54018_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54018.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG14P231F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC505YLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "S6E2C58L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HC32L150K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1138": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1138.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK60FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK60FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MCIMX6G0": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32LG230F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1133": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1133.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "APOLLO512-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK50DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NANO130SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ARMCM23": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "QN9083A": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083B": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083C": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAMC20G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG13P231F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG842F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG842F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKV56F512xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV56F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x080000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV56F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "NANO120LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM4F211E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F211E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U35FHI33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F745VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG225F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG225F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F767VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM4LC2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B200F128GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F217ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2533": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2533.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32GG880F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG880F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG395F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG395F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F769BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL26Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL26Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL26Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4R5ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F110E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F110E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L073VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "STM32L471VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAML21J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G9FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAML21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG942F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG942F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK28FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28F15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK28FN2M0VMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28F15_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK28F15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "LPC11U34FBD48/421": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "HC32L110C4UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F246J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U34FHN33/421": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32HG322F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG322F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F50230_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HT32F52231_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC230SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2HG6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1342FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HC32L150F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC4402-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini51FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMC20E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1F16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG330F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG330F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMDA1E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMG51G18": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51G18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L083VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1820ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32G280F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G280F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F231H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F231H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM073FSDUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M073.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F405ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32ZG210F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32HG308F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG308F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1100-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AU9110LF3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/AU9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}, "Flash/AU9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/AU9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAM4LS4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4LS4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S7ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F469AE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "APOLLO256-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L083VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG230F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG230F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L4S9ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NANO100KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NANO103ZD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1225FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TMPM332FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C5AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M482LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFR32MG13P632F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M2S025": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "MKL24Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H5FSDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123SC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L152C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9D96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini58ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TLE9877QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C1299NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1299NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M453VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4N8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM4N8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG13P932F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P932F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P932F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L162QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG12B500F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1313FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC200SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11A14FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG840F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG840F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4500-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF368M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1764": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG14P632F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P632F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P632F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G8F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2D55J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL25Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F1765_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F207ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "PAC5220": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D31": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "NUC029FAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AE\\Include\\NUC029FAE.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NUC029AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "PAC5223": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NM1120EC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV10Z16xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKV_P16_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKV10Z1287.h", "define": "MKV10Z64xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MKW21Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "GD32F450VI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9AF131M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF131L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F427VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3U1E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1313FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF131K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BFD17S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "XMC1404-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BFD17T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52241_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKW22D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF567R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4LC4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32WG330F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF366K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4078FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL25Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S70": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF567N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF567M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC120VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKM33Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "M058SZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMV70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32MG12P232F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F215ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "M484SIDAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LPC11U23FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG995F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG995F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F215ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FDH20/002": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA0G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FBD48/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF117S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M453YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L152C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M452LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M0564LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M451VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM4F110H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F110H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L021G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4072FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK22FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12365_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LM3S9D90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF617S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF617T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H753XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32GG11B820F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20J17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1301-Q040x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F2451BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U37FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32PG1B200F128IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32WG895F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG895F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VE3DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B520F128GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG14P732F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAME53J20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F417VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L431VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG309F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG309F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F070F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L486VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L031E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM13Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM13Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F330R8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32LG280F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG280F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F733IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4315": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "QN9080A": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "QN9080C": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9080B": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54102J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U13FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKL43Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL43Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL43Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1512": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM3HMFDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U36FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF518S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F042C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "RC10001": {"core": "Cortex-M0", "vendor": "RelChip:146", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.relchip.com/Keil/RelChip.RC10000.1.0.0.pack", "compile": {"header": "Device/Include/RC10001.h"}, "pdsc_file": "http://www.relchip.com/Keil/RelChip.RC10000.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD/RC10001.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "4000000"}}, "STM32L031K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L031K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F330RB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "MKM34Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKV58F512xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV58F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x080000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV58F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S6952": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6952.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4CP16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF155R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG13P732F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMG55G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL27Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x400fe000", "size": "0x0200"}, "SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL27Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMR21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B820F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF521M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6V7": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32BG1B232F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S2608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6V2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC804M101JDH24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "MB9BF521K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF142N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM072FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M072.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG230F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4367": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "ARMCM33_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32LG395F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG395F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B540F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM372FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC8H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1R26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG330F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG330F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B320F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B320F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B320F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C29L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M451MRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MK22FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F042K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U35FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TC35678FXG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "TMPM367FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E1A11C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1112FHN24/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P832F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P832F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P832F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG13P632F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F50231_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L471VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R7AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG230F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "APOLLO256-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F1656": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG232F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG232F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1P133F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ARMCM33": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ADuCM361": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 512]], "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD/ADuCM361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "ADuCM360": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 512]], "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD/ADuCM360.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32LG990F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG990F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P431F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P431F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P431F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F212E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F212E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG14P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM390FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM39x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG290F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG290F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MIMX8MQ6xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MKL04Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "N571P032": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N571E000.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\N571P032_v3.svd", "processor": {"clock": "23000000"}}, "TMPM367FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M483SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32L152QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5956": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5956.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TC35679IFTG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "SN32F757F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MVF51NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NN151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "NANO120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM3S5951": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5951.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF315M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1404-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1937": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1937.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAM4E8E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG230F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LPC4078FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F479VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L152VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK02FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK02FN64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MK02F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F112C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F112C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F102C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4A6AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG842F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG842F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F102C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG1B200F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F102C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F111H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F111H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F190T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini55LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M481LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "XMC1201-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Z32F06423AKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF305N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG1P132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C1230H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1230H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MIMXRT1051xxxxB": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096], [1610612736, 262144]], "algorithm": {"arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}, "arm/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1051_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1051DVL6B"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1051_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x040000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MIMXRT1051.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "600000000"}}, "HT32F0008_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32TG11B340F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "A31G112": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536867328, 128]], "algorithm": {"A31G11x/Flashloader/A31G11x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G11x/Flashloader/A31G11x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G11x/Core/include/A31G11x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "A31G11x/SVD/A31G11x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC822M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC822.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NUC130VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B120F128GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V032F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V032F256GM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V032F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M052LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV31F512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F51212_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F512VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F51212_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MKV31F51212.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4S5QI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM3H5FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C59L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4SA16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG230F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG230F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK66FX1M0VMD18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK66F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "M0564LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO100LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F417IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC810M021FN8": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x00001000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/LPC810.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC123ZC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM4F122C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F122C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MVF50NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "EFR32BG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKE15Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE15Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}}, "debug": "MKE15Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMHA1G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}, "samha1a/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1a/svd/ATSAMHA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MVF60NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "EFR32FG1V232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1B231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2C18J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1115JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129LNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129LNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG222F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32MG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MD7xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MB9BF505N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F102CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL16Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD48/121": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F318C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM4G9F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54616J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54616J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54616.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S9B92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L432KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "CMSDK_CM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN256VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF116M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC220LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO110RE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32TG11B540F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK12DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1B21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1b21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E14FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F098CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM36BFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "PAC5210": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG11B540F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC126RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKW24D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW24D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32WG230F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF616S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK70FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF616T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32HG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32WG230F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG230F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2DH5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG11B420F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF618T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC120RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L452RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L452RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF618S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME51N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC11E68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG995F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG995F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32JG1B100F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC220VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F350C6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "SN32F236J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54618J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54618_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54618J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54618_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54618.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM366FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4E16E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4E16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1547JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32G800F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G800F128"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G800F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S67": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1232H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1232H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F105RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF154M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF154N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO102ZB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAM4S4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV70J19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70J19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "GD32F330K8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NANO120ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F401RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C129ENCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG110F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG110F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "AC30M1464": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1530VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B540F64IM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1654_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L081KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F031G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F0008_24QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F031G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF154R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11C14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6ZXR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZXR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C32E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32E_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4C32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW40Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW40Z4.h", "define": "MKW40Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW40Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L073RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L021D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "version": "0.1.0", "STM32L073RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG980F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG980F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG980F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG980F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "K32W042S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W042S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG295F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG295F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD18T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL33Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL33Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52241_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD20J14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4402-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F746IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BFD16T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S2D93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s2d93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F131C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F131C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMHA1E14AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "samha1b/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1b/svd/ATSAMHA1E14AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "Mini51XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BFD16S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32GG11B520F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C38H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK11DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F746IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG110F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1520RC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F50220_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "ATSAMD21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK51DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF566R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG14P231F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2HE6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF506N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG13P632F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF506R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC126VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F217VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC21J18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG230F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG230F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MKE04Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE04Z1284.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L476RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B110F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L476RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG14P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG332F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG332F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4C4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1751": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1751.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK60DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF314M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F2755_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B840F1024IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F318K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4504-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG390F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG390F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4337": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32L151CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV10Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV10Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKV10Z1287.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "XMC1404-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11A13FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F232E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M452LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L475ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F239F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4370": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32TG210F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF428T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32L041K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK20FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NANO130KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF105R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF568R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG940F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG940F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F268F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112LVFHI33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMHA1G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "samha1a/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1a/svd/ATSAMHA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF568N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F358RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF568M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL13Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL13Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL13Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ARMSC300": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMSC300/Include/ARMSC300.h", "define": "ARMSC300"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F765BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1653_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32FG14P232F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TMPM380FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F120H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F120H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4076FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1404-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM4LS4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMDA1G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C129EKCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129EKCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32JG1B200F256GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L486QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK10DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC442JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "STM32L100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011K3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC100LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L011K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1439": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1439.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DF5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ADuCM320i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320i.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF61NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NN151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "M451LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG940F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG940F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51822_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F412ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52354_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DH5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL82Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKL_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL82Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL82Z128VMP7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL82Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fffa000", "size": "0x018000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL82Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "96000000"}}, "EZR32WG230F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F205RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S10": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32PG1B200F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F205RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1810": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "NUC505DS13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC1812": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1813": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1815": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1817": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L162RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L475VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2U93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s2u93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NM1120TC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM036FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M036.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NM1520LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L162ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAML22J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1231D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AFB44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC4088FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1B232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F407VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L041E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F429IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC130LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F121B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F121B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F2755": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NM1120XC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC220LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC029TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1124JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x08000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F50220": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F091VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52230_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L471JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L471JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM4G9FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MVF50NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S9C97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9c97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F098RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 8192], [32768, 16384], [65536, 32768], [131072, 65536], [524288, 8192], [557056, 16384], [589824, 32768], [655360, 65536]], "algorithm": {"Flash/TMPM440_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "M487KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F767NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG11B120F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM462F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC4504-F144x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R9VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4R9I_EVAL.FLM": {"default": "0", "ramsize": null, "size": "0x04000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3S8B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EZR32WG230F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54605J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54605J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54605.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM074FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M074.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1302-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "SSE-200-MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.V2M-MPS3_SSE_200_BSP.1.0.0.pack", "compile": {"header": "Device/V2M-MPS3-SSE-200/SMM-SSE-200/Include/mps3_sse_200.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.V2M-MPS3_SSE_200_BSP.pdsc", "memory": {}, "debug": "SVD/MPS3_SSE_200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V131F32GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F32GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EZR32LG230F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "Mini58TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32WG230F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746BE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32WG230F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG360F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG360F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF368R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C49J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF368N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4N16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "Mini57XDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HC32M140J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32M140JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S8738": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8738.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ADuCM3027": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "ATSAMC21N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21N/ATSAMC21N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F50230_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG390F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG390F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52342_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1635": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1635.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM3029": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "STM32F100VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MKW21Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F130H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F130H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "SN32F7651BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L476ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F439BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32TG11B320F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini54TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "K32W032S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W032S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F110B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F110B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9G97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9g97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F50231_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C123BH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC130RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO130KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2C5AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F469NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F415VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "Mini51TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32ZG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F373C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG330F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG330F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GM8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM3HNFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F50220_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO100KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF505R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "nRF52832_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "IOTKit_CM23": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM23/Include/IOTKit_CM23.h", "define": "IOTKit_CM23"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L433VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21J17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF115M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMC20G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini55ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F072V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1V132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M058SSAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F413VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M487SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "MB9BF168N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF168M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F405VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F439BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F765ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF168R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAME70N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32HG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2GM8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM475FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EZR32WG230F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAM4N8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG332F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG332F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M485SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F101VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32H753VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32F101VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM383FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F301K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG14P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1960": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1960.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F52253_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F301K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F723VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F769BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF412R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMA5D33": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D33.svd", "processor": {"fpu": "DP_FPU"}}, "HC32F005C6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F005.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.1.0.0.pack", "compile": {"header": "Device/Include/HC32F005.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32F005.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC123ZC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC4200-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG110F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B540F64IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF412N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HC32L157KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L157KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAML22N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMV70Q20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70Q20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKL16Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SH32F205": {"core": "Cortex-M3", "vendor": "Sinowealth:149", "sectors": [[0, 2048]], "algorithm": {"Flash/SH32F2xx.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.sinowealth.com/ftp/tool/Arm32/Sinowealth.SH32Fxxx_DFP.1.0.0.pack", "compile": {"header": "Device/Include/sh32f2xx.h", "define": "SH32F2XX"}, "pdsc_file": "http://www.sinowealth.com/ftp/tool/Arm32/Sinowealth.SH32Fxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\sh32f2xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AFA32L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG890F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F423ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKW01Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW01Z4.h", "define": "MKW01Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKW01Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P431F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1100-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F120B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F120B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HC32L157K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L157KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3N0B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S817": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s817.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "M453VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "A33G526": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024], [251658240, 1024]], "algorithm": {"A33G52x/Flashloader/A33G527_DFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x0F000000"}, "A33G52x/Flashloader/A33G527_CFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "A33G52x\\Core\\include\\A33G52x.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "A33G52x\\SVD\\A33G52x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "A33G527": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024], [251658240, 1024]], "algorithm": {"A33G52x/Flashloader/A33G527_DFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x0F000000"}, "A33G52x/Flashloader/A33G527_CFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "A33G52x\\Core\\include\\A33G52x.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "A33G52x\\SVD\\A33G52x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LPC812M101JTB16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L151VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P333F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P333F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P333F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L151R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM366FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF122K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3S4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG840F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG840F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3S4A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3N1B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG110F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F334C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF144M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF144L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F107VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334C4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5K36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NANO120ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F479BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO100KC3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32MG12P432F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32FG1P131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9AFA32N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L462CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NANO120KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NANO100NC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S1N11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "R-IN32M4-CL2": {"core": "Cortex-M4", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [268435456, 131072]], "algorithm": {"Flash/R-IN32M4_MX25L6433F.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M4_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.1.0.1.pack", "compile": {"header": "Device/Include/RIN32M4.h", "define": "RIN32M4_CL2"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M4_CL2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG222F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HC32L110B4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110B.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1404-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F302K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M058LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF318S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFR32FG12P431F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S301": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s301.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S300": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s300.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F207VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F439AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B520F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HE4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HE4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1236E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1236E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21G18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1316FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FBD48/323": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32H743AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32JG12B500F1024GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "NM1120ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S1N16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG11B820F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKM38Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM38Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F0006_48LQFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM369FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1751": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F205VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F1755_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG395F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG395F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4312": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NUC505YO13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "MKM33Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_CM4": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC1825": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1827": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC54628J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54628.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LPC1820": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1823": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1822": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MCIMX7S3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "EFR32FG1P133F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG14P632F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK51DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9781": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9781.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL16Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1100-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1112FHI33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32HG322F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG322F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F132C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F132C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3HMFZDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4R9AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF367M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF367N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F411CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32G840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1100FBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG13P231F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L041F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F042G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F439ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L100R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM4G9FDXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO112SB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ARMCM4": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM0": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0/Include/ARMCM0.h", "define": "ARMCM0"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM3": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM3/Include/ARMCM3.h", "define": "ARMCM3"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EZR32WG330F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HC32M140F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32M140FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S328": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s328.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S5T36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s5t36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL36Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M2351KIAAEES": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "EFM32LG380F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG380F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4S5AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EFR32FG13P232F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P232F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P232F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11C14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADSP-CM419F": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[285212672, 4096], [285736960, 4096]], "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.1.3.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x11080000", "size": "0x00080000"}, "IRAM1": {"start": "0x200F0000", "size": "0x00008000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x11000000", "size": "0x00080000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L071KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC240LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "CMSDK_CM3": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM3/Include/CMSDK_CM3.h", "define": "CMSDK_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAMV71N20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71N20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MB9BF216S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NANO100KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EZR32LG230F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F51212_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN512VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F51212_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F51212.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6537": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6537.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9997": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9997.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG11B540F64GQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S2110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF114L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF114M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "HT32F1655": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32HG320F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG11B510F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3N1A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1E14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MKL26Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9869QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9869.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAM3S4B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKV11Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV11Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV11Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L083CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F230E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F230E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54101J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L083CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F769F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "XMC1402-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F373RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMG54G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32LG900F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG900F256"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG900F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4E8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F048C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52220_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1125JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL27Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL27Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F205ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C18L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKL43Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL43Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL43Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG222F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF129T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LPC1113FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF144N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK28FN2M0Axxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28FA15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK28FN2M0AVMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28FA15_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x34000000", "size": "0x080000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK28FA15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "EFR32FG1V032F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V032F256GM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V032F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1P131F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2C19H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L072V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "TMPM4G8FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG12P231F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMG55J19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S612": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s612.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F732RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG332F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG332F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15BU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15BU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC472JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "GD32F330G6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1231E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC131SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S617": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s617.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC804M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "MB9AF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG1V132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF50NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "M451MSC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F130C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "GD32F130C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMG53G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E13FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG108F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG11B120F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F190R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3Z26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s3z26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F190R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD51G18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51G18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32TG108F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF522L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF522M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3N0A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330C4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "MB9BF522K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F330C8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "Mini51ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "MK27FN2M0Axxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27FA15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK27FN2M0AVMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27FA15_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x34000000", "size": "0x080000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK27FA15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "TLE9867QXW20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F50231": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HT32F50230": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L4A6VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F330CB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMV70J20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70J20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F756NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "M451SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG230F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG230F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L452CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF132L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32HG309F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG309F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF132K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL13Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL13Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL13Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG110F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4300-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4300_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4300c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4300_series/Include/XMC4300.h", "define": "XMC4300_F100x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x0FFC0"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4300.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S3739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4500-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC442RI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "M0564RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF504R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM470FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F429II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32BG1P232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F405RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F768AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0564VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF504N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKV46F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV46F256VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV46F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "NM1330LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F405RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2C38J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F405RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1402-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK65FX1M0xxx18WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L451VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM330FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L451VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK63FN1M0xxx12WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK63FN1M0VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK63F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1301-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32HG310F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG310F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32FG13P231F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5R36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F50231_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F777II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC20E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF316M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL05Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F111E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F111E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M052LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG395F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG395F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5P31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMCM33_DSP_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MIMXRT1021xxxxx": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096]], "algorithm": {"arm/MIMXRT1021_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1021DAG5A"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x020000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MIMXRT1021.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "500000000"}}, "MK65FN2M0xxx18WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "MKL17Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL17Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S9AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG940F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG940F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M484SGAAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC120RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKL33Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL33Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L433CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L433CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C1232E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1232E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B820F2048GL192": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL192.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112RB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMD51J20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "HT32F52241_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F120E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F120E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32PG12B500F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54113J128": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54113J256UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54113.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "nRF52832_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F302ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC4074FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F235J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52331": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S310": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s310.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK20DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S316": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s316.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S317": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s317.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11E37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S315": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s315.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F207IF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK22DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF415R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMDA1G14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1G14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TMPM3H6FSDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG842F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG842F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52352_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71Q19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC1114FBD48/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini54ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M452SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L011E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM341FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM341_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "NUC121LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TLE9842-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285249536, 4096]], "algorithm": {"Flash/TLE9842_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x11009000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9842_2.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0xA000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52354_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1226FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F030C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG210F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MKV44F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD21E16BU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16BU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1P332F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG842F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG842F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F030C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1833": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1830": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW21D256xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1837": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11D14FBD100/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11D14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350K6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LPC18S30": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW36Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM461_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S37": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F22366_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F0008": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK51DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK11DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "XMC1402-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71N21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71N21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F0006": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL14Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF117T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F437IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "nRF52840_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\nrf52840.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F745ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1200-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMS70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F446ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M058LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32LG940F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG940F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H5FUDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F412VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO110SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F410R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4700-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM370FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE02Z16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "ATSAMD51N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L041G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442RG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "NANO102ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM3S818": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s818.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD10C14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG54N19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F042F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MM32x031": {"core": "Cortex-M0", "vendor": "MindMotion:132", "sectors": [[134217728, 1024]], "algorithm": {"Flash/MM32x031_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.1.0.0.pack", "compile": {"header": "Device/Include/MM32x031.h", "define": "MM32x031"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/MM32x031.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B540F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S2671": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2671.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1315FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S2678": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2678.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F745ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1824FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0519LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L4S5VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11U67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC120VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMV71J20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71J20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MK65FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "Generic_Mini51_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F042T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HC32F003C4UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F003.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.1.0.0.pack", "compile": {"header": "Device/Include/HC32F003.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32F003.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM32Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM32Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG13P733F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P733F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P733F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L083RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52344": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM46BF10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM46B_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}, "IRAM2": {"start": "0x20080000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M46B.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F479BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4S9VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5Y36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s5y36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9790": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9790.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F405VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1B132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC120RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L052C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F411VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM470FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1114FHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L052C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF366R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EZR32HG320F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKV30F128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV30F64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV30F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L471ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R7VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG230F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1317FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1225FBD48/321": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC1202-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1V132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M483KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LM3S828": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s828.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini57EDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32G880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MVF60NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "EFM32TG11B540F64GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF366N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1958": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1958.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF366L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF366M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG330F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG330F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG13P732F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF60NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF306N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F107F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F766BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC832M101FDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC83x.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F078VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF306R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4_FP.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "ADuCM320": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4700-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L051C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK60FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "M4TKLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC4500-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9879QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F101T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MK60FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S5C36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG360F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG360F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1112JHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9BN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE06Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE06Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE06Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE06Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "Mini57FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52344_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H0FSDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F130R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H1FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B340F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52231_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1302-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S5D91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32LG360F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG360F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2C49H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M4LEDLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "AC30M1432": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C48H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21E17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F755J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF324L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG14P733F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P733F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P733F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32PG1B100F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO110RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32WG890F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG890F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1230E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1230E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2DF5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4CMS32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMS32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMDA1E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F105V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini52ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAME53J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME53J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32LG390F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG390F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32PG12B500F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1202-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG14P732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M487JIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32JG12B500F1024IL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG390F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG390F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MAX32660": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32660.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32660.flash": {"default": "0", "ramsize": "0x00018000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32660/Include/max32660.h", "define": "MAX32660"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MAX32660/max32660.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "NANO110KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LPC54113J128BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKW36A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD51J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFR32FG1V131F32GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F32GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1114LVFHN24/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U35FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1100DBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1302-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M058SFAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1518JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC54605J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "HT32F52354_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L431RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M2351KIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "EFM32LG332F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG332F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F091CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32JG1B200F256IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF414R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG380F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG380F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF414N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMS70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L486RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9877QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "M452YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M451MLC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG14P231F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NANO100LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32MG1B732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK50DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM333FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM33x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1301-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL43Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL43Z4.h", "define": "MKL43Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MQ6xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "EFM32GG11B510F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM333FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG295F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG295F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1100XBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F745VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG942F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG942F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFR32FG1P131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG13P632F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32FG1P131F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2CC9H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKE15Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE15Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM": {"start": "0x1fffe000", "size": "0x8000"}}, "debug": "MKE15Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1767": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF514R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4N16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SN32F767BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P16_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B340F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71Q21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71Q21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKS22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS22FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS22F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1200TAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NM1530VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HC32L110C4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MKE14F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE14F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32GG11B510F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC123LD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TM4C123BH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F328C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "Mini58FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F212H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F212H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM4G8FDXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3HMFYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG295F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG295F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC472VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TMPM4G7FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1519JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S1165": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1165.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F030R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1162": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1162.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2HE6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L082CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F417ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F12365": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NANO112RC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAML22G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F768BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S9U92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B510F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G222F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G222F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MKL17Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL17Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5662": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5662.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L011D3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L476QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMHA1G15AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "samha1ab/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1ab/svd/ATSAMHA1G15AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F429IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L052R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F401CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "MK53DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK21DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71J19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71J19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32TG225F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG225F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3S8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L052R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F777NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7652BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1P232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32H753BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32PG1B200F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B120F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FBD100": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3J26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3j26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3U2E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U2E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32GG11B840F1024GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P133F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S8630": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8630.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Generic_Nano100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "NUC505DLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC1226FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32L496VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F765IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7741J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK81FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK81F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK81FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK81F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK81F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "STM32F303C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMV71J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "S6E2C39J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF518T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "SKEAZN64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO100SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32GG11B510F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F1765_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1B131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1B632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ISD9130": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF365L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF365K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG880F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG880F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF155N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1656_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TLE9871QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 32768]], "algorithm": {"Flash/TLE9871.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF155M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "Mini52ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M451VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG840F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG840F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG13P932F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P932F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P932F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4088FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058SLAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S102": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s102.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S101": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "S6E2D55G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL27Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x400fe000", "size": "0x0200"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL27Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0516ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC54114J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F733VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MK40DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x0008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC122SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "M453VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG1V131F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG1B132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2CC8L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4CMP16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG1B132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P233F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P233F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P233F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1227FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "M451LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG11B840F1024IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B520F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P732F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F207IC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LS8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F401RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32WG395F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG395F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108HB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG1B132F256GM56": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM56.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1302-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG232F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG232F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54605J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54605J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54605.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKV30F64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV30F64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV30F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMD21E16L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM369FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC20J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF112M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKE02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "arm/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4CP16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16B_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M2S090": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LM3S812": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52342": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAME53J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM4F121C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F121C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC140RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAME53N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M054LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO120LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NUC120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3H6FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M054LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1114FN28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F427IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMV70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F417ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF165K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMDA1E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF165L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3H6FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C1237H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG108F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32WG360F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG360F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAML21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM376FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA0J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B420F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG990F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG990F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MWPR1516xxx": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKPR1516_P16KB.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MWPR1516.h", "define": "MWPR1516xxx"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MWPR1516.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54101J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG1B232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451MLD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2CCAJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12366": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F52231": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52230": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG11B820F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1110FD20": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x1000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0400"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1200LAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW41Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F413ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMV71J21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71J21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKE06Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE06Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE06Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKE06Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "NUC200VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B120F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF521L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMV70N20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70N20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TMPM3HQFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMCM33_DSP_FP_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F334R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG14P532F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P532F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P532F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F031C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C59J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD51P20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F765NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32G842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B120F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG12B500F1024GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F070CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2939": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2939.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51P19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M0516ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF515N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF515R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32LG330F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P8_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00002000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G8FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMV71Q20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71Q20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "M482LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F429BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO100LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "M451LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM3S5P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG380F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG380F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5632": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG14P733F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P733F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P733F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC54606J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54606J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54606.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F303ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L443VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F150C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM411F20XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768], [0, 32768]], "algorithm": {"Flash/TMPM41xA_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM41xB_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM411_unitB.h", "define": "TMPM411F20XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20008000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54102J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG12P231F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P231F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P231F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK20DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG14P233F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P233F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM330FDWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54616J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54616J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54616.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32WG330F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG330F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TC35679FSG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "HT32F12345_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F746BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5D51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F247BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2GK8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4800-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L476VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HC32L110C6UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF468R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD20E17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM3S3W26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s3w26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B840F1024GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1B632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF468M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF468N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG395F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG395F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1R21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "RS14100_1MB": {"core": "Cortex-M4", "vendor": "Redpine Signals:125 ", "sectors": [[134291456, 4096]], "algorithm": {"Flash/RS14100_SF_1MB.FLM": {"default": "1", "ramsize": "0x4000", "size": "0xEE000", "ramstart": "0x00000000", "start": "0x08012000"}}, "debug-interface": [], "pack_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.1.0.2.pack", "compile": {"header": "Driver/Common/chip/inc/RS1xxxx.h"}, "pdsc_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x000000C", "size": "0x2FFF4"}, "IROM1": {"start": "0x08012000", "size": "0xEE000"}}, "debug": "SVD/RS1xxxx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF565L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F469ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1401-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B520F128IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini52XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC140RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32LG842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1290NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C123FH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123FH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC122SC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "ATSAM3N2A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F237F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1621": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1621.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1150": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1150.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1625": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1625.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF417S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1315FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S8530": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8530.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M453RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9BF417T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S8538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG842F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG842F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1V132F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F248F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL33Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL33Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1B132F256GD1": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GD1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L462RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG14P632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L011G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L496AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L011G3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMD21G15L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21G15L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1E14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F765ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M0516ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC4072FET80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG822F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG822F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG332F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG332F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0516LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9AFB44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F767ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32ZG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG380F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG380F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F32GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F32GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4800-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKV44F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "TMPM4G8FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F52243_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F350G6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "ISD9361": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9300_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9300_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9300_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "S6E2D55JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1D21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M482SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LM3S1D26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "GD32F350G4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LM4F212H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMV71J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F2755_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F769IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L475RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32G840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM4G7F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L475RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "IOTKit_ARMv8MML": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MML/Include/IOTKit_ARMv8MML.h", "define": "IOTKit_ARMv8MML"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1J16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1J11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F0006_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52342_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC122LC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "EFM32HG210F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG210F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S2616": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2616.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F1656_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NM1823LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC812M101JD20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S1Z16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s1z16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG330F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4500-E144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1P132F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKL36Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM373FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M373.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAML21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL27Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL27Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1317FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M2S150": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "STM32L071VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9843-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285261824, 4096]], "algorithm": {"Flash/TLE9843_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100C000"}, "Flash/TLE9843_2.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0D000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L071VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L051K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC126LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW35A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1655_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L051K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DH5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM4G9FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32MG1P132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L4R7ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LS8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G9F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F098VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S7VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54113J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54113J256UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.pdsc", "memory": {"SRAM2": {"start": "0x20020000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x20010000", "size": "0x010000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54113.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32H743ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMDA0J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1114FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L4R9ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F746NE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG14P231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32ZG110F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F769AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F405OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32LG230F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P632F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG380F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG380F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32ZG110F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S808": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s808.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F22366": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC11U14FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21J18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL17Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL17Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F072R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F230H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F230H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1237E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF364K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF364L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F215RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D42": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D42.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F215RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "nRF52810_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf52810.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "TM4C1237E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S6911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMD51G19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51G19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L072VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M483SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC120LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F150K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5P56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H14G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H14F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H14E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S32K148": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"addon_cmsis/Flash/S32K148_P1536_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x00000000"}, "addon_cmsis/Flash/S32K148_D512_4KB_SEC.FLM": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x0001F000"}, "IRAM2": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "platform/devices/S32K148/S32K148.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32F469IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKL33Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL33Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1403-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "HC32L150FA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMA5D44": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D44.svd", "processor": {"fpu": "DP_FPU"}}, "STM32L4A6QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D41": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D41.svd", "processor": {"fpu": "DP_FPU"}}, "TMPM3HQFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D43": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D43.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32GG290F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG290F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFR32MG1P632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M0516LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52243": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL16Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC11U24FHI33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L433RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LC2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL17Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL17Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC472KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TM4C123BH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F130F8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO130KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM342FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM342_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00009000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1402-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114JHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD21E15L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130F4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG11B120F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130F6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M481ZIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "TMPM36BF10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040800"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S9971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG825F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG825F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF111K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768], [537657344, 8192]], "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC240LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9AF111N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L4S5ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK12DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330F8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "XMC1201-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AC33M3064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F330F4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S2948": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2948.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9D81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F407ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO110RC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F429BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32WG330F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1202-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MIMX8MQ5xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ5DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ5.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "EFM32GG232F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG232F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F103R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1816": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1816.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F437VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F103R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MVF61NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NS151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F107VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM343FEXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_768.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC240LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMV70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32WG230F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG295F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG295F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "HT32F52352_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM3H1FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF416T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM3HMFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF416R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF416S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1112FD20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD20E18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF342M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SN32F249F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F410TB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG108F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG330F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H6FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1968": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1968.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF416N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EZR32LG330F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG390F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG390F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ML630Q466": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "sectors": [[0, 1024]], "algorithm": {"Flash/ML630Q466.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/ML630Q466.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q464": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "sectors": [[0, 1024]], "algorithm": {"Flash/ML630Q464.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/ML630Q464.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051K8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F051K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4074FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F051K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1330LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1330_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF217T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF217S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMV70N19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70N19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32FG1P132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK27FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27F15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK27FN2M0VMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27F15_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK27F15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "MB9BF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3HNFDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32BG1B232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000B800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF516N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2G38H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TM4C1233H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG11B340F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F107RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F107RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1518JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1548JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM4F210H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F210H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-T038x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF418S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2C28L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF418T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S32K146": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/S32K146_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000F000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "platform/devices/S32K146/S32K146.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "SN32F263X": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S32K144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/S32K144_P512_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "platform/devices/S32K144/S32K144.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32L475QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2G26J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L475QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2G26H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM4F112H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54605J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LM3S1637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Z32F38412ALS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 256]], "algorithm": {"Flash/Z32F3841.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F3841.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F3841.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK10DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F429VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini52TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LPC1112LVFHN24/003": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11U68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F22366_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MKL03Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S37": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "XMC1202-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Generic_NUC100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MIMX8MQ7xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "LPC845M301JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG1V131F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F50241_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKMP256_2KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34Z7.h", "define": "MKM34Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKM34Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32WG280F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG280F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM383FWEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B200F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG330F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK21FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F030F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG990F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F415RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9AFA41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL15Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG330F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG330F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "arm/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK66FX1M0VMD18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK66F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM330FYWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B540F64GM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AFA41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2HG6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F413CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2C2AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F170C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL25Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1W16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s1w16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M484KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F733ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L031G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5656": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5656.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F238F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L031G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F779BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11U24FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2793": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2793.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1401-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MBL/Include/CMSDK_ARMv8MBL.h", "define": "CMSDK_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F469VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C58H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "S6E2C3AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S628": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s628.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG895F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG895F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG895F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F469AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMS70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "APOLLO512-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "NUC130RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52231_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG12P332F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32G200F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G200F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL46Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL46Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL46Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1752": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM3H6FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1756": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1754": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L152RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011F3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1759": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1758": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1342FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L011F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMCA9": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA9/Include/ARMCA9.h", "define": "ARMCA9"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM23_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC1111FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5737": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5737.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5732": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5732.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCA5": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA5/Include/ARMCA5.h", "define": "ARMCA5"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M0518LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ARMCA7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA7/Include/ARMCA7.h", "define": "ARMCA7"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M452VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32LG232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52331_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9843QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285257728, 4096]], "algorithm": {"Flash/TLE9843_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100B000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9843.FLM": {"default": "1", "ramsize": null, "size": "0xB000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM4G8F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM4F132E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F132E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SKEAZN8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/SKEAZN84.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S8962": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8962.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4LEDRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F413ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG11B510F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F1765_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1100-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2D35JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG11B340F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37FBD48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5G51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM3S2730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "RS14100_4MB": {"core": "Cortex-M4", "vendor": "Redpine Signals:125 ", "sectors": [[134291456, 4096]], "algorithm": {"Flash/RS14100_SF_4MB.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x3EE000", "ramstart": "0x00000000", "start": "0x08012000"}}, "debug-interface": [], "pack_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.1.0.2.pack", "compile": {"header": "Driver/Common/chip/inc/RS1xxxx.h"}, "pdsc_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x000000C", "size": "0x2FFF4"}, "IROM1": {"start": "0x08012000", "size": "0x3EE000"}}, "debug": "SVD/RS1xxxx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM3S2A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "HT32F12365_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LM3S2739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK21DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MAX32630": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32630.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.0.0.1.pack", "compile": {"header": "Libraries/Device/Maxim/MAX3263X/Include/max3263x.h", "define": "TARGET=MAX32631"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32630/max32630.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32631": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32630.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.0.0.1.pack", "compile": {"header": "Libraries/Device/Maxim/MAX3263X/Include/max3263x.h", "define": "TARGET=MAX32631"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32630/max32630.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF329T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF329S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK11DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1227FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S6618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54102J256": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54102J512UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54102_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG1P132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM367FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3HPFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1201-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1P132F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G8F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC126RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF167R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F373V8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U36FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F111C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F111C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM366FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2139": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2139.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "EFR32FG12P231F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKW30Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW30Z4.h", "define": "MKW30Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW30Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P532F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P532F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P532F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF167N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF167M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S6100": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "S6E2GH6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2GH6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4S2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG108F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC834M101FHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC83x.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM3X8H": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8H.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "MKL15Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DF5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3X8E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAM3X8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1292NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12345": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M0516LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F110C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F110C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F373VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG980F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG980F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FDH20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H2FUQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F407IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32HG321F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG321F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F407IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32MG1P231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1115FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN128VMP10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG320F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2C39L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B310F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B310F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B310F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF318T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL05Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B120F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG332F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SD16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC4800-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "NANO120SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "XMC1302-T028x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-T028x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ND2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2GH8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF216T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2GH8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F103C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK50DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TC35678FSG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "LM3S6432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF129S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1821FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330G8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S2950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S613": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s613.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F330G4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF517S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF517T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9D92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S615": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s615.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M4LEDRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F479NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32BG1P333F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P333F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P333F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1626": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1626.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG11B140F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S1627": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1627.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54101J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54101J512UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54101.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM3SD8B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3SD8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAMC21J17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F301C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ARMCM0P_MPU": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h", "define": "ARMCM0P_MPU"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MB9BF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2CCAL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAML21E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG332F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG332F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C1AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2CCAH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF316S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF316R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF316T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9L97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AMAPH1KK-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 8192]], "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1113FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L162RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF500R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [16384, 49152], [65536, 65536]], "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M481ZGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32JG1B200F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F722VC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32BG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG11B520F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC845M301JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "TMPM475FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF500N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [16384, 49152], [65536, 65536]], "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF305R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F405VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M482SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32TG11B120F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F120C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F120C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG290F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG290F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11E14FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1294NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1311FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG995F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG995F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5C56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F103ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG12P433F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG980F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG980F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L451RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32H753AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFR32MG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAM4CMP8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM361FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC11U12FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32H753AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MKV31F256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKV31F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L496QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21G17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21G17AU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}}, "debug": "MKE14Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B820F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF467M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1302-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMHA1G16AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "samha1ab/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1ab/svd/ATSAMHA1G16AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG11B320F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F101RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32GG11B840F1024GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3N4B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x06000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3N/ATSAM3N4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC54114J256": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54114_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54114J256UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54114_DFP.pdsc", "memory": {"SRAM2": {"start": "0x20020000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x20010000", "size": "0x010000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54114_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S2918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK80FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK80F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK80FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK80F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK80F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "LM3S1607": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1607.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F439VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK50DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM330FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MIMX8MD6xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "STM32F302VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HC32F005C6UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F005.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.1.0.0.pack", "compile": {"header": "Device/Include/HC32F005.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32F005.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "R-IN32M3-CL": {"core": "Cortex-M3", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [33554432, 65536], [268435456, 8192], [268435456, 131072], [268500992, 65536]], "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_CL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F302VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F205ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F769NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1402-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L442KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L442xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1548JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF367R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F1655_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21G17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33_FP": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC120RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG320F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F52253_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC4400-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NANO100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG940F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG940F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F350G8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "STM32F103T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM4G9F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MK10DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK10DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini51ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMD20G15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446MC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "CMSDK_ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TM4C1237D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM375FSDMG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M375.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3N0C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1J15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LPC11E66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52354_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG11B320F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F330C6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "XMC1202-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32HG320F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1113FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L041C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE04Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKE04Z1284.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L041C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3HMFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini52XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM4G7FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMS70N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100ND3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F398VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F732ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F130E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F130E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1345FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM363F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M363.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S5651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F732IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5652": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5652.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF112L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HC32M140KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32M140KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4078FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H2FWQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F078RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM462F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG12P431F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM369FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF51NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NS151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S8971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8970": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8970.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1230D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1230D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HC32L150JA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11E67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAME54P20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "XMC1100-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MM32x103": {"core": "Cortex-M3", "vendor": "MindMotion:132", "sectors": [[134217728, 1024]], "algorithm": {"Flash/MM32x103_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MM32x103.h", "define": "MM32x103_MD"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/MM32x103.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NM1100XAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32LG230F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "LPC1113FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1401-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC822M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC822.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F479NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F52230_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MAX32621": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32620.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32620.flash": {"default": "0", "ramsize": "0x00020000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.1.0.2.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32620/Include/max32620.h"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32620/max32620.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32620": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32620.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32620.flash": {"default": "0", "ramsize": "0x00020000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.1.0.2.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32620/Include/max32620.h"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32620/max32620.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32626": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32625.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32625.flash": {"default": "0", "ramsize": "0x00028000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.1.0.0.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32625/Include/max32625.h", "define": "MAX32626"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MAX32625/max32625.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32625": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32625.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32625.flash": {"default": "0", "ramsize": "0x00028000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.1.0.0.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32625/Include/max32625.h", "define": "MAX32626"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MAX32625/max32625.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAML21J17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1343FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HC32L156JA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L156JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG280F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG280F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ISD9341": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "EZR32LG230F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM470FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ISD9340": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "Generic_M051_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L083V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123FE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123FE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HC32L150J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HC32L156J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L156JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1317FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1H11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1H16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMV70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC1347FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B420F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2410": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2410.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "R7S72103": {"core": "Cortex-A9", "vendor": "Renesas:117", "sectors": [[0, 4096]], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.RZ_DFP.1.1.0.pack", "compile": {"header": "Device/Include/RZ_A1LU.h", "define": "RZ_A1LU"}, "pdsc_file": "http://www.keil.com/pack/Keil.RZ_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x18000000", "size": "0x800000"}}, "processor": {"fpu": "DP_FPU"}}, "GD32F307VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 2048], [134742016, 4096], [536868879, 16]], "algorithm": "Flash/GD32F30x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F30x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/gd32f30x.h", "define": "GD32F30X_CL"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F30x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F30x_CL.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}} \ No newline at end of file