From 9e6b1246a4919ed29e1193bf96f5c6bc2d578fea Mon Sep 17 00:00:00 2001 From: Bence Kaposzta Date: Fri, 12 Oct 2018 09:13:04 +0200 Subject: [PATCH 01/10] This commit adds EMAC driver for CM3DS that uses an SMSC LAN 9220 Ethernet controller. To ensure proper operation, some methods needed to be updated in the SMSC9220's native driver as well. It passes all related Greentea tests, however when supervised by the Python environment it tends to fail because of Timeout. The current timeout is set to 1200s that seems to be a little bit short to finish all test cases, the timeout happens towards the end of the last test case. Change-Id: I914608c34828b493a80e133cd132537a297bfc84 Signed-off-by: Bence Kaposzta --- .../COMPONENT_SMSC9220/mbed_lib.json | 7 + .../COMPONENT_SMSC9220/smsc9220_emac.cpp | 338 ++++++ .../COMPONENT_SMSC9220/smsc9220_emac.h | 180 +++ .../COMPONENT_SMSC9220/smsc9220_emac_config.h | 42 + .../TARGET_CM3DS_MPS2/device/device_cfg.h | 6 + .../device/drivers/smsc9220_eth.c | 746 ------------ .../device/drivers/smsc9220_eth.h | 170 --- .../device/drivers/smsc9220_eth_drv.c | 1074 +++++++++++++++++ .../device/drivers/smsc9220_eth_drv.h | 548 +++++++++ .../device/platform_devices.c | 10 + .../device/platform_devices.h | 5 + .../TARGET_CM3DS_MPS2/ethernet_api.c | 85 -- .../TARGET_CM3DS_MPS2/mbed_overrides.c | 8 +- targets/targets.json | 8 +- 14 files changed, 2221 insertions(+), 1006 deletions(-) create mode 100644 features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/mbed_lib.json create mode 100644 features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp create mode 100644 features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.h create mode 100644 features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h delete mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c delete mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h create mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.c create mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h delete mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c diff --git a/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/mbed_lib.json b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/mbed_lib.json new file mode 100644 index 00000000000..d54a2784eaa --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/mbed_lib.json @@ -0,0 +1,7 @@ +{ + "name": "smsc9220-emac", + "config": { + "rx-ring-len": 1, + "tx-ring-len": 1 + } +} diff --git a/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp new file mode 100644 index 00000000000..167024e11a3 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2018 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +#include "mbed_interface.h" +#include "mbed_wait_api.h" +#include "mbed_assert.h" +#include "netsocket/nsapi_types.h" +#include "mbed_shared_queues.h" + +#include "smsc9220_emac.h" +#include "smsc9220_eth_drv.h" + +#ifndef SMSC9220_ETH +#error "SMSC9220_ETH should be defined, check device_cfg.h!" +#endif + +#ifndef SMSC9220_Ethernet_Interrupt_Handler +#error "SMSC9220_Ethernet_Interrupt_Handler should be defined to platform's \ +Ethernet IRQ handler!" +#endif + +static SMSC9220_EMAC *board_emac_pointer = NULL; +const struct smsc9220_eth_dev_t* SMSC9220_EMAC::dev = &SMSC9220_ETH_DEV; + +extern "C" void SMSC9220_Ethernet_Interrupt_Handler(void) +{ + if (smsc9220_get_interrupt(SMSC9220_EMAC::dev, + SMSC9220_INTERRUPT_RX_STATUS_FIFO_LEVEL)) { + board_emac_pointer->rx_isr(); + smsc9220_clear_interrupt(SMSC9220_EMAC::dev, + SMSC9220_INTERRUPT_RX_STATUS_FIFO_LEVEL); + smsc9220_disable_interrupt(SMSC9220_EMAC::dev, + SMSC9220_INTERRUPT_RX_STATUS_FIFO_LEVEL); + } +} + +SMSC9220_EMAC::SMSC9220_EMAC() : receiver_thread(LINK_STATUS_THREAD_PRIORITY, + (uint32_t)LINK_STATUS_THREAD_STACKSIZE) +{ +} + +/** \brief Ethernet receive interrupt handler + * + * This function handles the receive interrupt. + */ +void SMSC9220_EMAC::rx_isr() +{ + receiver_thread.flags_set(FLAG_RX); +} + +/** \brief Allocates a emac_mem_buf_t and returns the data from the incoming + * packet. + * + * \return a emac_mem_buf_t filled with the received packet + * (including MAC header) + */ +emac_mem_buf_t *SMSC9220_EMAC::low_level_input() +{ + emac_mem_buf_t *p = NULL; + uint32_t message_length = 0; + + message_length = smsc9220_peek_next_packet_size(dev); + if (message_length == 0) { + return p; + } else { + /* The Ethernet controller cannot remove CRC from the end of the + * incoming packet, thus it should be taken into account when + * calculating the actual message length.*/ + message_length -= CRC_LENGTH_BYTES; + } + + p = _memory_manager->alloc_heap(message_length, SMSC9220_BUFF_ALIGNMENT); + + if (p != NULL) { + _RXLockMutex.lock(); + smsc9220_receive_by_chunks(dev, (char*)_memory_manager->get_ptr(p), + _memory_manager->get_len(p)); + _RXLockMutex.unlock(); + } + + return p; +} + +/** \brief Receiver thread. + * + * Woken by thread flags to receive packets or clean up transmit + * + * \param[in] params pointer to the interface data + */ +void SMSC9220_EMAC::receiver_thread_function(void* params) +{ + struct SMSC9220_EMAC *smsc9220_enet = static_cast(params); + + while(1) { + uint32_t flags = ThisThread::flags_wait_any(FLAG_RX); + + if (flags & FLAG_RX) { + smsc9220_enet->packet_rx(); + } + } +} + +/** \brief Packet reception task + * + * This task is called when a packet is received. It will + * pass the packet to the Network Stack. + */ +void SMSC9220_EMAC::packet_rx() +{ + emac_mem_buf_t *p; + p = low_level_input(); + if(p != NULL) { + _emac_link_input_cb(p); + } + smsc9220_enable_interrupt(dev, SMSC9220_INTERRUPT_RX_STATUS_FIFO_LEVEL); +} + +bool SMSC9220_EMAC::link_out(emac_mem_buf_t *buf) +{ + if(buf == NULL) { + return false; + } else { + uint32_t buffer_chain_length = 0; + enum smsc9220_error_t error = SMSC9220_ERROR_NONE; + /* If buffer is chained or not aligned then + * make a contiguous aligned copy of it */ + if (_memory_manager->get_next(buf) || + reinterpret_cast(_memory_manager->get_ptr(buf)) % + SMSC9220_BUFF_ALIGNMENT) { + emac_mem_buf_t *copy_buf; + copy_buf = _memory_manager->alloc_heap( + _memory_manager->get_total_len(buf), + SMSC9220_BUFF_ALIGNMENT); + if (NULL == copy_buf) { + _memory_manager->free(buf); + return false; + } + + /* Copy to new buffer and free original */ + _memory_manager->copy(copy_buf, buf); + _memory_manager->free(buf); + buf = copy_buf; + } + + buffer_chain_length = _memory_manager->get_total_len(buf); + + _TXLockMutex.lock(); + error = smsc9220_send_by_chunks(dev, + buffer_chain_length, + true, + (const char*)_memory_manager->get_ptr(buf), + _memory_manager->get_len(buf)); + if (error != SMSC9220_ERROR_NONE) { + _TXLockMutex.unlock(); + return false; + } + _TXLockMutex.unlock(); + return true; + } +} + +void SMSC9220_EMAC::link_status_task() +{ + uint32_t phy_basic_status_reg_value = 0; + bool current_link_status_up = false; + + /* Get current status */ + smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_BSTATUS, + &phy_basic_status_reg_value); + + current_link_status_up = (bool)(phy_basic_status_reg_value & + (1ul << (PHY_REG_BSTATUS_LINK_STATUS_INDEX))); + + /* Compare with previous state */ + if (current_link_status_up != _prev_link_status_up) { + _emac_link_state_cb(current_link_status_up); + _prev_link_status_up = current_link_status_up; + } + +} + +bool SMSC9220_EMAC::power_up() +{ + board_emac_pointer = this; + receiver_thread.start(callback(&SMSC9220_EMAC::receiver_thread_function, + this)); + + /* Initialize the hardware */ + enum smsc9220_error_t init_successful = smsc9220_init(dev, &wait_ms); + if (init_successful != SMSC9220_ERROR_NONE) { + return false; + } + + /* Init FIFO level interrupts: use Rx status level irq to trigger + * interrupts for any non-processed packets, while Tx is not irq driven */ + smsc9220_set_fifo_level_irq(dev, SMSC9220_FIFO_LEVEL_IRQ_RX_STATUS_POS, + SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MIN); + smsc9220_set_fifo_level_irq(dev, SMSC9220_FIFO_LEVEL_IRQ_TX_STATUS_POS, + SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MIN); + smsc9220_set_fifo_level_irq(dev, SMSC9220_FIFO_LEVEL_IRQ_TX_DATA_POS, + SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MAX); + + /* Enable Ethernet interrupts in NVIC */ + NVIC_EnableIRQ(ETHERNET_IRQn); + smsc9220_enable_interrupt(dev, SMSC9220_INTERRUPT_RX_STATUS_FIFO_LEVEL); + + /* Trigger thread to deal with any RX packets that arrived + * before receiver_thread was started */ + rx_isr(); + _prev_link_status_up = PHY_STATE_LINK_DOWN; + mbed::mbed_event_queue()->call(mbed::callback(this, + &SMSC9220_EMAC::link_status_task)); + + /* Allow the Link Status task to detect the initial link state */ + wait_ms(10); + _link_status_task_handle = mbed::mbed_event_queue()->call_every( + LINK_STATUS_TASK_PERIOD_MS, + mbed::callback(this, + &SMSC9220_EMAC::link_status_task)); + + return true; +} + +uint32_t SMSC9220_EMAC::get_mtu_size() const +{ + return SMSC9220_ETH_MTU_SIZE; +} + +uint32_t SMSC9220_EMAC::get_align_preference() const +{ + return SMSC9220_BUFF_ALIGNMENT; +} + +void SMSC9220_EMAC::get_ifname(char *name, uint8_t size) const +{ + memcpy(name, SMSC9220_ETH_IF_NAME, (size < sizeof(SMSC9220_ETH_IF_NAME)) ? + size : sizeof(SMSC9220_ETH_IF_NAME)); +} + +uint8_t SMSC9220_EMAC::get_hwaddr_size() const +{ + return SMSC9220_HWADDR_SIZE; +} + +bool SMSC9220_EMAC::get_hwaddr(uint8_t *addr) const +{ + if(smsc9220_read_mac_address(dev, (char*)addr) == SMSC9220_ERROR_NONE) { + return true; + } else { + return false; + } +} + +void SMSC9220_EMAC::set_hwaddr(const uint8_t *addr) +{ + if (!addr) { + return; + } + + memcpy(_hwaddr, addr, sizeof _hwaddr); + uint32_t mac_low = 0; + uint32_t mac_high = 0; + + /* Using local variables to make sure the right alignment is used */ + memcpy((void*)&mac_low, (void*)addr, 4); + memcpy((void*)&mac_high, (void*)(addr+4), 2); + + if (smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_ADDRL, mac_low)) { + return; + } + if (smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_ADDRH, mac_high)) { + return; + } +} + +void SMSC9220_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + _emac_link_input_cb = input_cb; +} + +void SMSC9220_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + _emac_link_state_cb = state_cb; +} + +void SMSC9220_EMAC::add_multicast_group(const uint8_t *addr) +{ + // No action for now +} + +void SMSC9220_EMAC::remove_multicast_group(const uint8_t *addr) +{ + // No action for now +} + +void SMSC9220_EMAC::set_all_multicast(bool all) +{ + // No action for now +} + +void SMSC9220_EMAC::power_down() +{ + // No action for now +} + +void SMSC9220_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + _memory_manager = &mem_mngr; +} + + +SMSC9220_EMAC &SMSC9220_EMAC::get_instance() { + static SMSC9220_EMAC emac; + return emac; +} + +/* Weak so a module can override */ +MBED_WEAK EMAC &EMAC::get_default_instance() { + return SMSC9220_EMAC::get_instance(); +} diff --git a/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.h b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.h new file mode 100644 index 00000000000..58762d4f59f --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2018 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SMSC9220_EMAC_H_ +#define SMSC9220_EMAC_H_ + +#include "EMAC.h" +#include "mbed.h" +#include "rtos/Mutex.h" + +#include "smsc9220_emac_config.h" + +class SMSC9220_EMAC : public EMAC { +public: + SMSC9220_EMAC(); + + static SMSC9220_EMAC &get_instance(); + + /** + * Return maximum transmission unit + * + * @return MTU in bytes + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may + * or may not align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ + virtual uint32_t get_align_preference() const; + + /** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Return interface-supplied HW address + * + * Copies HW address to provided memory, @param addr has to be of correct + * size see @a get_hwaddr_size + * + * HW address need not be provided if this interface does not have its own + * HW address configuration; stack will choose address from central system + * configuration if the function returns false and does not write to addr. + * + * @param addr HW address for underlying interface + * @return true if HW address is available + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is + * provided the stack would normally use that, but it could be overridden, + * eg for test purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ + virtual bool power_up(); + + /** + * Deinitializes the HW + * + */ + virtual void power_down(); + + /** + * Sets a callback that needs to be called for packets received for that + * interface + * + * @param input_cb Function to be register as a callback + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that needs to be called on link status changes for given + * interface + * + * @param state_cb Function to be register as a callback + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Add device to a multicast group + * + * @param address A multicast group hardware address + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + + void rx_isr(); + + static const struct smsc9220_eth_dev_t *dev; + +private: + void packet_rx(); + void link_status_task(); + bool low_level_init_successful(); + emac_mem_buf_t *low_level_input(); + static void receiver_thread_function(void* params); + + rtos::Mutex _TXLockMutex; + rtos::Mutex _RXLockMutex; + bool _prev_link_status_up; + int _link_status_task_handle; + uint8_t _hwaddr[SMSC9220_HWADDR_SIZE]; + + Thread receiver_thread; + EMACMemoryManager *_memory_manager; + emac_link_input_cb_t _emac_link_input_cb; + emac_link_state_change_cb_t _emac_link_state_cb; + +}; + +#endif /* SMSC9220_EMAC_H_ */ diff --git a/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h new file mode 100644 index 00000000000..f8299a84b6e --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SMSC9220_EMAC_CONFIG_H +#define SMSC9220_EMAC_CONFIG_H + +#include "cmsis_os.h" + +#define SMSC9220_HWADDR_SIZE 6U +#define SMSC9220_BUFF_ALIGNMENT 4U + +/* + * Maximum Transfer Unit + * The IEEE 802.3 specification limits the data portion of the 802.3 frame + * to a minimum of 46 and a maximum of 1522 bytes, this is on L2 level. + */ +#define SMSC9220_ETH_MTU_SIZE 1500U +#define SMSC9220_ETH_IF_NAME "smsc9220" + +/** \brief Defines for receiver thread */ +#define FLAG_RX 1U +#define LINK_STATUS_THREAD_PRIORITY (osPriorityNormal) +#define LINK_STATUS_THREAD_STACKSIZE 2048U +#define LINK_STATUS_TASK_PERIOD_MS 200U +#define PHY_STATE_LINK_DOWN false +#define PHY_STATE_LINK_UP true +#define CRC_LENGTH_BYTES 4U + +#endif /* SMSC9220_EMAC_CONFIG_H */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h index dd39c21a0a3..b18568b0d33 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h @@ -58,4 +58,10 @@ #define ARM_UART3 #define ARM_UART4 +/* SMSC9220 Ethernet */ +#ifdef COMPONENT_SMSC9220 +#define SMSC9220_ETH +#define SMSC9220_Ethernet_Interrupt_Handler ETHERNET_IRQHandler +#endif + #endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c deleted file mode 100644 index 0fee077abf6..00000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c +++ /dev/null @@ -1,746 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Code implementation file for the LAN Ethernet interface. - * - * This file is the based on mps2_ethernet_api and Selftest's ETH_MPS2. - * MPS2 Selftest:https://silver.arm.com/browse/VEI10 -> - * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\ - */ - -#include - -#include "mbed_retarget.h" -#include "mbed_wait_api.h" -#include "CM3DS.h" -#include "smsc9220_eth.h" - -#define REG_WRITE_TIME_OUT 50 -#define RESET_TIME_OUT 10 -#define PHY_RESET_TIME_OUT_MS 100 - -/* Forward declarations */ - -static unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data); -static unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data); -static unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned int *data); -static unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned int data); - -static unsigned int smsc9220_read_id(void); -static unsigned int smsc9220_soft_reset(void); -static void smsc9220_set_txfifo(unsigned int val); -static unsigned int smsc9220_wait_eeprom(void); -static void smsc9220_init_irqs(void); -static unsigned int smsc9220_check_phy(void); -static unsigned int smsc9220_reset_phy(void); - -static void smsc9220_advertise_cap(void); -static void smsc9220_enable_xmit(void); -static void smsc9220_enable_mac_xmit(void); -static void smsc9220_enable_mac_recv(void); - -/* SMSC9220 low-level operations */ - -/** - * \brief Read MAC register. - * - * \param[in] regoffset Register offset - * \param[out] data Register value is read - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) -{ - unsigned int val = 0; - unsigned int maccmd = 0; - int time_out = REG_WRITE_TIME_OUT; - - val = SMSC9220->MAC_CSR_CMD; - if(!(val & ((unsigned int)1 << 31))) { /* Make sure there's no pending operation */ - maccmd |= regoffset; - maccmd |= ((unsigned int)1 << 30); /* Indicates read */ - maccmd |= ((unsigned int)1 << 31); /* Start bit */ - SMSC9220->MAC_CSR_CMD = maccmd; /* Start operation */ - - do { - val = SMSC9220->BYTE_TEST; /* A no-op read. */ - wait_ms(1); - time_out--; - } while(time_out && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); - - if(!time_out) { - return 1; - } - else { - *data = SMSC9220->MAC_CSR_DATA; - } - } else { - *data = 0; - } - return 0; -} - -/** - * \brief Write MAC register. - * - * \param[in] regoffset Register offset - * \param[in] data Register value to write - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) -{ - unsigned int read = 0; - unsigned int maccmd = 0; - int time_out = REG_WRITE_TIME_OUT; - - read = SMSC9220->MAC_CSR_CMD; - if(!(read & ((unsigned int)1 << 31))) { /* Make sure there's no pending operation */ - SMSC9220->MAC_CSR_DATA = data; /* Store data. */ - maccmd |= regoffset; - maccmd &= ~((unsigned int)1 << 30); /* Clear indicates write */ - maccmd |= ((unsigned int)1 << 31); /* Indicate start of operation */ - SMSC9220->MAC_CSR_CMD = maccmd; - - do { - read = SMSC9220->BYTE_TEST; /* A no-op read. */ - wait_ms(1); - time_out--; - } while(time_out && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); - - if(!time_out) { - return 1; - } - } else { - printf("Error: SMSC9220 MAC CSR is busy. No data written.\n"); - } - return 0; -} - -/** - * \brief Read PHY register. - * - * \param[in] regoffset Register offset - * \param[out] data Register value is read - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned int *data) -{ - unsigned int val = 0; - unsigned int phycmd = 0; - int time_out = REG_WRITE_TIME_OUT; - - if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val)) { - return 1; - } - - if(!(val & 1)) { /* Not busy */ - phycmd = 0; - phycmd |= (1 << 11); /* 1 to [15:11] */ - phycmd |= ((regoffset & 0x1F) << 6); /* Put regoffset to [10:6] */ - phycmd &= ~(1 << 1); /* Clear [1] indicates read. */ - phycmd |= (1 << 0); /* Set [0] indicates operation start */ - - if (smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd)) { - return 1; - } - - val = 0; - do { - wait_ms(1); - time_out--; - if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val)) { - return 1; - } - } while(time_out && (val & ((unsigned int)1 << 0))); - - if (!time_out) { - return 1; - } else if (smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, data)) { - return 1; - } - } else { - *data = 0; - return 1; - } - return 0; -} - -/** - * \brief Write PHY register. - * - * \param[in] regoffset Register offset - * \param[in] data Register value to write - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned int data) -{ - unsigned int val = 0; - unsigned int phycmd = 0; - int time_out = REG_WRITE_TIME_OUT; - - if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val)) { - return 1; - } - - if(!(val & 1)) { /* Not busy */ - /* Load the data */ - if (smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF))) { - return 1; - } - phycmd = 0; - phycmd |= (1 << 11); /* 1 to [15:11] */ - phycmd |= ((regoffset & 0x1F) << 6); /* Put regoffset to [10:6] */ - phycmd |= (1 << 1); /* Set [1] indicates write. */ - phycmd |= (1 << 0); /* Set [0] indicates operation start */ - /* Start operation */ - if (smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd)) { - return 1; - } - - phycmd = 0; - - do { - wait_ms(1); - time_out--; - if (smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd)){ - return 1; - } - } while(time_out && (phycmd & (1 << 0))); - - if (!time_out) { - return 1; - } - - } else { - printf("Error: SMSC9220 MAC MII is busy. No data written.\n"); - } - return 0; -} - -/** - * \brief Read SMSC9220 ID. - * - * \return ID number - */ -inline static unsigned int smsc9220_read_id(void) -{ - return SMSC9220->ID_REV; -} - -/** - * \brief Initiates a soft reset, returns failure or success. - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_soft_reset(void) -{ - int time_out = RESET_TIME_OUT; - - /* Soft reset */ - SMSC9220->HW_CFG |= 1; - - do { - wait_ms(1); - time_out--; - } while(time_out && (SMSC9220->HW_CFG & 1)); - - if (!time_out) { - return 1; - } - - return 0; -} - -/** - * \brief Set maximum transition unit by Tx fifo size. - * Note: The MTU will be smaller by 512 bytes, - * because the status uses this fixed space. - * - * \param[in] val Size of the fifo in kbytes, 2-14 - */ -static void smsc9220_set_txfifo(unsigned int val) -{ - /* 2kb minimum, 14kb maximum */ - if(val >= 2 && val <= 14) { - SMSC9220->HW_CFG = val << 16; - } -} - -/** - * \brief Wait for EEPROM to be ready to use. - * - * \return 0 if ready, 1 in case of timeout - */ -static unsigned int smsc9220_wait_eeprom(void) -{ - int time_out = REG_WRITE_TIME_OUT; - - do { - wait_ms(1); - time_out--; - } while(time_out && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); - - if (!time_out) { - return 1; - } - - return 0; -} - -/** - * \brief Initialise irqs - */ -static void smsc9220_init_irqs(void) -{ - SMSC9220->INT_EN = 0x0; - SMSC9220->INT_STS = 0xFFFFFFFF; /* clear all interrupts */ - SMSC9220->IRQ_CFG = 0x22000100; /* irq deassertion at 220 usecs and master IRQ enable. */ -} - -/** - * \brief Check PHY ID registers. - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_check_phy(void) -{ - unsigned int phyid1, phyid2; - - if (smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1)) { - return 1; - } - if (smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2)) { - return 1; - } - return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || - (phyid1 == 0x0 && phyid2 == 0x0)); -} - -/** - * \brief Reset PHY - * - * \return 0 in case of success, 1 otherwise - */ -static unsigned int smsc9220_reset_phy(void) -{ - unsigned int read; - - if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { - return 1; - } - - read |= (1 << 15); - if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { - return 1; - } - return 0; -} - - -/** - * \brief Advertise all speeds and pause capabilities - * - * \return 0 in case of success, 1 otherwise - */ -static void smsc9220_advertise_cap(void) -{ - unsigned int aneg_adv = 0; - - smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); - aneg_adv |= 0xDE0; - - smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv); - smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); -} - -/** - * \brief Enable trasmission - */ -inline static void smsc9220_enable_xmit(void) -{ - SMSC9220->TX_CFG = 0x2; -} - -static void smsc9220_enable_mac_xmit(void) -{ - unsigned int mac_cr = 0; - - smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); - - mac_cr |= (1 << 3); /* xmit enable */ - mac_cr |= (1 << 28); /* Heartbeat disable */ - - smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); -} - -/** - * \brief Enable receive - */ -static void smsc9220_enable_mac_recv(void) -{ - unsigned int mac_cr = 0; - - smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); - mac_cr |= (1 << 2); /* Recv enable */ - smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); -} - -/** - * \brief Check device ID. - * - * \return 0 in case of success, 1 otherwise - */ -static int smsc9220_check_id(void) -{ - unsigned int id = smsc9220_read_id(); - - /* If bottom and top halves of the word are the same */ - if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { - return 1; - } - switch(((id >> 16) & 0xFFFF)) { - case 0x9220: - break; - - default: - return 1; - } - - return 0; -} - -/** - * \brief Fill the SMSC9220 TX FIFO with a number of words at an aligned - * address. - * - * \param[in] data Pointer to the aligned data that should be sent. - * \param[in] dwords_to_write Number of data words to write. - */ -static void fill_tx_fifo_aligned(unsigned int *data, - unsigned int dwords_to_write) -{ - while (dwords_to_write > 0) { - SMSC9220->TX_DATA_PORT = *data; - data++; - dwords_to_write--; - } -} - -/** - * \brief Fill the SMSC9220 TX FIFO with a number of words at an unaligned - * address. This function ensures that loading words at that address will - * not generate unaligned access which can trigger an exception to the - * processor. - * - * \param[in] data Pointer to the unaligned data that should be sent. - * \param[in] dwords_to_write Number of data words to write. - */ -static void fill_tx_fifo_unaligned(uint8_t *data, unsigned int dwords_to_write) -{ - /* - * Prevent unaligned word access from data pointer, 4 bytes are copied to - * this variable for each word that need to be sent. - */ - unsigned int tx_data_port_tmp = 0; - uint8_t *tx_data_port_tmp_ptr = (uint8_t *)&tx_data_port_tmp; - - while (dwords_to_write > 0) { - /* Keep the same endianness in data than in the temp variable */ - tx_data_port_tmp_ptr[0] = data[0]; - tx_data_port_tmp_ptr[1] = data[1]; - tx_data_port_tmp_ptr[2] = data[2]; - tx_data_port_tmp_ptr[3] = data[3]; - SMSC9220->TX_DATA_PORT = tx_data_port_tmp; - data += 4; - dwords_to_write--; - } -} - -/*---------------------------------------------------------------------------- - Public API - *----------------------------------------------------------------------------*/ -int smsc9220_init(void) -{ - unsigned int phyreset = 0; - - if(smsc9220_check_id()) { - return 1; - } - - if(smsc9220_soft_reset()) { - return 1; - } - - smsc9220_set_txfifo(5); - - /* Sets automatic flow control thresholds, and backpressure */ - /* threshold to defaults specified. */ - SMSC9220->AFC_CFG = 0x006E3740; - - if(smsc9220_wait_eeprom()) { - return 1; - } - - /* Configure GPIOs as LED outputs. */ - SMSC9220->GPIO_CFG = 0x70070000; - - smsc9220_init_irqs(); - - /* Configure MAC addresses here if needed. */ - - if(smsc9220_check_phy()) { - return 1; - } - - if(smsc9220_reset_phy()) { - return 1; - } - - wait_ms(PHY_RESET_TIME_OUT_MS); - /* Checking whether phy reset completed successfully.*/ - if (smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset)) { - return 1; - } - if(phyreset & (1 << 15)) { - return 1; - } - - smsc9220_advertise_cap(); - smsc9220_establish_link(); /* bit [12] of BCONTROL seems self-clearing. */ - /* Although it's not so in the manual. */ - - /* Interrupt threshold */ - SMSC9220->FIFO_INT = 0xFF000000; - - smsc9220_enable_mac_xmit(); - smsc9220_enable_xmit(); - SMSC9220->RX_CFG = 0; - smsc9220_enable_mac_recv(); - - /* Rx status FIFO level irq threshold */ - SMSC9220->FIFO_INT &= ~(0xFF); /* Clear 2 bottom nibbles */ - - /* This sleep is compulsory otherwise txmit/receive will fail. */ - wait_ms(2000); - return 0; -} - -void smsc9220_enable_interrupt(enum smsc9220_interrupt_source source) -{ - SMSC9220->INT_EN |= (1 << source); -} - -void smsc9220_disable_interrupt(enum smsc9220_interrupt_source source) -{ - SMSC9220->INT_EN &= ~(1 << source); -} - -void smsc9220_clear_interrupt(enum smsc9220_interrupt_source source) -{ - SMSC9220->INT_STS |= (1 << source); -} - -int smsc9220_get_interrupt(enum smsc9220_interrupt_source source) -{ - return (SMSC9220->INT_STS & (1 << source)); -} - -void smsc9220_establish_link(void) -{ - unsigned int bcr = 0; - unsigned int hw_cfg = 0; - - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); - bcr |= (1 << 12) | (1 << 9); - smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr); - smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); - - hw_cfg = SMSC9220->HW_CFG; - hw_cfg &= 0xF0000; - hw_cfg |= (1 << 20); - SMSC9220->HW_CFG = hw_cfg; -} - -int smsc9220_read_mac_address(char *mac) -{ - unsigned int mac_low = 0; - unsigned int mac_high = 0; - - if( !mac ) { - return 1; - } - - /* Read current mac address. */ - if (smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high)) { - return 1; - } - if (smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low)) { - return 1; - } - mac[0] = mac_low & 0xFF; - mac[1] = (mac_low >> 8) & 0xFF; - mac[2] = (mac_low >> 16) & 0xFF; - mac[3] = (mac_low >> 24) & 0xFF; - mac[4] = mac_high & 0xFF; - mac[5] = (mac_high >> 8) & 0xFF; - - return 0; -} - -unsigned int smsc9220_get_tx_data_fifo_size(void) -{ - const unsigned int tx_status_fifo_size = 512; /* fixed allocation in bytes */ - unsigned int tx_fifo_size = SMSC9220->HW_CFG; - tx_fifo_size = (( tx_fifo_size >> 16 ) & 0x0F) * 1024; /* size is set in kbytes */ - return (tx_fifo_size - tx_status_fifo_size); -} - -int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, - const char *data, unsigned int current_size) -{ - static unsigned int ongoing_packet_length = 0; /* size in bytes of the packet is sending */ - static unsigned int ongoing_packet_length_sent = 0; /* size in bytes of the packet has been sent */ - int is_first_segment = 0; /* signing this is the first segment of the packet to be sent */ - int is_last_segment = 0; /* signing this is the last segment of the packet to be sent */ - unsigned int txcmd_a, txcmd_b = 0; - unsigned int dwords_to_write = 0; - unsigned int xmit_inf = 0; - unsigned int tx_buffer_free_space = 0; - unsigned int xmit_stat = 0; - - if (!data) { - return -1; /* Invalid input parameter */ - } - - if (is_new_packet) { - is_first_segment = 1; - ongoing_packet_length = total_packet_length; - ongoing_packet_length_sent = 0; - } else if (ongoing_packet_length != total_packet_length || - ongoing_packet_length_sent >= total_packet_length) { - return -1; /* Invalid input parameter */ - } - - /* Would next chunk fit into buffer? */ - xmit_inf = SMSC9220->TX_FIFO_INF; - tx_buffer_free_space = xmit_inf & 0xFFFF; - if (current_size > tx_buffer_free_space) { - return -1; /* Not enough space in FIFO */ - } - if ((ongoing_packet_length_sent + current_size) == total_packet_length) { - is_last_segment = 1; - } - - txcmd_a = 0; - txcmd_b = 0; - - txcmd_a |= (is_last_segment << 12) | (is_first_segment << 13); /* Last and first segments */ - txcmd_a |= current_size & 0x7FF; /* [10:0] contains length */ - - txcmd_b |= ((current_size & 0xFFFF) << 16); /* [31:16] contains length */ - txcmd_b |= current_size & 0x7FF; /* [10:0] also contains length */ - - SMSC9220->TX_DATA_PORT = txcmd_a; - SMSC9220->TX_DATA_PORT = txcmd_b; - dwords_to_write = (current_size + 3) >> 2; - - /* - * Copy to TX FIFO - * The function to use depends on the alignment of the data pointer on a 32 - * bits boundary. - */ - if (((unsigned int)data % sizeof(uint32_t)) == 0) { - /* Cast is safe because we know data is aligned */ - fill_tx_fifo_aligned((unsigned int *)data, dwords_to_write); - } else { - fill_tx_fifo_unaligned((uint8_t *)data, dwords_to_write); - } - - if (is_last_segment) { - /* pop status port */ - /* for error check it should be checked "at a later time" according to data sheet */ - xmit_stat = SMSC9220->TX_STAT_PORT; - (void)xmit_stat; - } - - ongoing_packet_length_sent += current_size; - return 0; -} - -unsigned int smsc9220_get_rxfifo_data_used_space(void) -{ - unsigned int rxfifo_inf = SMSC9220->RX_FIFO_INF; - return rxfifo_inf & 0xFFFF; -} - -unsigned int smsc9220_receive_by_chunks(char *data, unsigned int dlen) -{ - static unsigned int current_packet_size_words = 0; - unsigned int rxfifo_inf = 0; - unsigned int rxfifo_stat = 0; - unsigned int dlen_word = 0; - unsigned int read_length_word = 0; - unsigned int i = 0; - - if (!data) { - return 0; /* Invalid input parameter */ - } - - if (current_packet_size_words == 0) { - /* First the packet status word should be read, */ - /* which tells the size of the data, */ - /* after the data can be read in synchron. */ - rxfifo_inf = SMSC9220->RX_FIFO_INF; - - if(rxfifo_inf & 0xFFFF) { /* If there's data */ - rxfifo_stat = SMSC9220->RX_STAT_PORT; - if(rxfifo_stat != 0) { /* Fetch status of this packet */ - if(rxfifo_stat & (1 << 15)) { - current_packet_size_words = 0; /* error */ - } - else { - /* Ethernet controller is padding to 32bit aligned data */ - current_packet_size_words = (((rxfifo_stat >> 16) & 0x3FFF) + 3) >> 2; - } - } - } - } - dlen_word = dlen / 4; - read_length_word = (dlen_word < current_packet_size_words) ? dlen_word : current_packet_size_words; - - for (i = 0; i < read_length_word; i++) { - ((unsigned int*)data)[i] = SMSC9220->RX_DATA_PORT; - current_packet_size_words--; - } - return (current_packet_size_words * 4); -} - -unsigned int smsc9220_peek_next_packet_size(void) -{ - unsigned int packet_size = 0; - unsigned int rx_stat_peek = 0; - - if(smsc9220_get_rxfifo_data_used_space()) { - rx_stat_peek = SMSC9220->RX_STAT_PEEK; - packet_size = ((rx_stat_peek >> 16) & 0x3FFF); - } - return (((packet_size + 3) >> 2) << 2); -} - diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h deleted file mode 100644 index 7db54379372..00000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h +++ /dev/null @@ -1,170 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* This file is the re-implementation of mps2_ethernet_api and Selftest's ETH_MPS2. - * MPS2 Selftest:https://silver.arm.com/browse/VEI10 -> - * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\ - */ -#ifndef _SMSC9220_ETH_H_ -#define _SMSC9220_ETH_H_ - -enum smsc9220_interrupt_source { - enum_smsc9220_interrupt_gpio0 = 0, - enum_smsc9220_interrupt_gpio1 = 1, - enum_smsc9220_interrupt_gpio2 = 2, - enum_smsc9220_interrupt_rxstatus_fifo_level = 3, - enum_smsc9220_interrupt_rxstatus_fifo_full = 4, - /* 5 Reserved according to Datasheet */ - enum_smsc9220_interrupt_rx_dropped_frame = 6, - enum_smsc9220_interrupt_txstatus_fifo_level = 7, - enum_smsc9220_interrupt_txstatus_fifo_full = 8, - enum_smsc9220_interrupt_txdata_fifo_available = 9, - enum_smsc9220_interrupt_txdata_fifo_overrun = 10, - /* 11, 12 Reserved according to Datasheet */ - enum_smsc9220_interrupt_transmit_error = 13, - enum_smsc9220_interrupt_receive_error = 14, - enum_smsc9220_interrupt_receive_watchdog_timeout = 15, - enum_smsc9220_interrupt_txstatus_overflow = 16, - enum_smsc9220_interrupt_power_management = 17, - enum_smsc9220_interrupt_phy = 18, - enum_smsc9220_interrupt_gp_timer = 19, - enum_smsc9220_interrupt_rx_dma = 20, - enum_smsc9220_interrupt_tx_ioc = 21, - /* 22 Reserved according to Datasheet*/ - enum_smsc9220_interrupt_rx_dropped_frame_half = 23, - enum_smsc9220_interrupt_rx_stopped = 24, - enum_smsc9220_interrupt_tx_stopped = 25, - /* 26 - 30 Reserved according to Datasheet*/ - enum_smsc9220_interrupt_sw = 31 -}; - -/* Function declarations */ - -/** - * \brief Initialize SMS9220 Ethernet controller - * - * \return 0 if init is successful, 1 otherwise - */ -int smsc9220_init(void); - -/** - * \brief Enable the given interrupt source. - * - * \param[in] source Enum of the interrupt source. - */ -void smsc9220_enable_interrupt(enum smsc9220_interrupt_source source); - -/** - * \brief Disable the given interrupt source. - * - * \param[in] source Enum of the interrupt source. - */ -void smsc9220_disable_interrupt(enum smsc9220_interrupt_source source); - -/** - * \brief Clear the given interrupt source. - * - * \param[in] source Enum of the interrupt source. - */ -void smsc9220_clear_interrupt(enum smsc9220_interrupt_source source); - -/** - * \brief Get the status of the given interrupt source. - * - * \param[in] source Enum of the interrupt source. - * - * \return non-zero if the given interrupt source is triggered, zero otherwise - */ -int smsc9220_get_interrupt(enum smsc9220_interrupt_source source); - -/** - * \brief Establish link - */ -void smsc9220_establish_link(void); - -/** - * \brief Read MAC address from EEPROM. - * - * \param[in,out] mac array will include the read MAC address in - * 6 bytes hexadecimal format. - * It should be allocated by the caller to 6 bytes. - * - * \return 0 if read is successful, 1 otherwise - */ -int smsc9220_read_mac_address(char *mac); - -/** - * \brief Get the data size of the Tx buffer, aka Maximum Transition Unit - * - * \return Fifo data size in bytes - */ -unsigned int smsc9220_get_tx_data_fifo_size(void); - -/** - * \brief Send Ethernet packet from buffer chain. - * The full packet length should be known in the beginning - * of a new packet. - * - * \param[in] total_packet_length Length of the packet. Should be equal to - * the sum of passed buffers within a packet. - * \param[in] is_new_packet Should be set to non-zero if the passed buffer - * should be sent as the start of a new packet. - * If the current buffer should be sent as a full packet, - * it should be set to non-zero respectively. - * \param[in] data Pointer to the data should be sent. - * \param[in] current_size Size of the data in bytes. - * - * \return 0 if the send process is successful, standard C error code otherwise - */ -int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, - const char *data, unsigned int current_size); - -/** - * \brief Receive Ethernet packet from Rx FIFO to the passed buffer. - * Stops reading at packet border. - * If the passed buffer is larger than the current packet, - * the whole packet will be read into the buffer. - * If the current packet is larger than the passed buffer, - * the buffer will be filled with data and the next call - * will continue the read from that point. - * - * \param[in,out] data Pointer where the data will be read to. - * The caller is responsible to allocate it. - * \param[in] dlen Length of the allocated data in bytes. - * - * \return Remaining bytes left in the fifo of the current packet. - */ -unsigned int smsc9220_receive_by_chunks(char *data, unsigned int dlen); - -/** - * \brief Get the used space of Rx fifo in bytes. - * - * \return Data received and waiting for read in bytes - */ -unsigned int smsc9220_get_rxfifo_data_used_space(void); - -/** - * \brief Get the size of next unread packet in Rx buffer, using the peak - * register, which is not destructive so can be read asynchronously. - * Warning: In case of heavy receiving load, it's possible this register - * is not perfectly in sync. - * - * \return Size in bytes of the next packet can be read from Rx fifo, according - * to the peek register. - */ -unsigned int smsc9220_peek_next_packet_size(void); - -#endif diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.c new file mode 100644 index 00000000000..b9b6b57fcce --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.c @@ -0,0 +1,1074 @@ +/* + * Copyright (c) 2016-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" +#include "smsc9220_eth_drv.h" + +/** Setter bit manipulation macro */ +#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) +/** Clearing bit manipulation macro */ +#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) +/** Getter bit manipulation macro */ +#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX)))) + +/** Setter bit-field manipulation macro */ +#define SET_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET, VALUE) \ + (WORD |= ((VALUE & BIT_MASK) << BIT_OFFSET)) + +/** Clearing bit-field manipulation macro */ +#define CLR_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET, VALUE) \ + (WORD &= ~((VALUE & BIT_MASK) << BIT_OFFSET)) + +/** Getter bit-field manipulation macro */ +#define GET_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET) \ + ((WORD >> BIT_OFFSET) & BIT_MASK) + +/** Millisec timeout macros */ +#define RESET_TIME_OUT_MS 10U +#define REG_WRITE_TIME_OUT_MS 50U +#define PHY_RESET_TIME_OUT_MS 100U +#define INIT_FINISH_DELAY 2000U + +struct smsc9220_eth_reg_map_t { +__I uint32_t rx_data_port; /**< Receive FIFO Ports (offset 0x0) */ + uint32_t reserved1[0x7]; +__O uint32_t tx_data_port; /**< Transmit FIFO Ports (offset 0x20) */ + uint32_t reserved2[0x7]; + +__I uint32_t rx_status_port; /**< Receive FIFO status port (offset 0x40) */ +__I uint32_t rx_status_peek; /**< Receive FIFO status peek (offset 0x44) */ +__I uint32_t tx_status_port; /**< Transmit FIFO status port (offset 0x48) */ +__I uint32_t tx_status_peek; /**< Transmit FIFO status peek (offset 0x4C) */ + +__I uint32_t id_revision; /**< Chip ID and Revision (offset 0x50) */ +__IO uint32_t irq_cfg; /**< Main Interrupt Config (offset 0x54) */ +__IO uint32_t irq_status; /**< Interrupt Status (offset 0x58) */ +__IO uint32_t irq_enable; /**< Interrupt Enable Register (offset 0x5C) */ + uint32_t reserved3; /**< Reserved for future use (offset 0x60) */ +__I uint32_t byte_test; /**< Byte order test 87654321h (offset 0x64) */ +__IO uint32_t fifo_level_irq; /**< FIFO Level Interrupts (offset 0x68) */ +__IO uint32_t rx_cfg; /**< Receive Configuration (offset 0x6C) */ +__IO uint32_t tx_cfg; /**< Transmit Configuration (offset 0x70) */ +__IO uint32_t hw_cfg; /**< Hardware Configuration (offset 0x74) */ +__IO uint32_t rx_datapath_ctrl; /**< RX Datapath Control (offset 0x78) */ +__I uint32_t rx_fifo_inf; /**< Receive FIFO Information (offset 0x7C) */ +__I uint32_t tx_fifo_inf; /**< Transmit FIFO Information (offset 0x80) */ +__IO uint32_t pmt_ctrl; /**< Power Management Control (offset 0x84) */ +__IO uint32_t gpio_cfg; /**< GPIO Configuration (offset 0x88) */ +__IO uint32_t gptimer_cfg; /**< GP Timer Configuration (offset 0x8C) */ +__I uint32_t gptimer_count; /**< GP Timer Count (offset 0x90) */ + uint32_t reserved4; /**< Reserved for future use (offset 0x94) */ +__IO uint32_t word_swap; /**< WORD SWAP Register (offset 0x98) */ +__I uint32_t free_run_counter; /**< Free Run Counter (offset 0x9C) */ +__I uint32_t rx_dropped_frames;/**< RX Dropped Frames Counter (offset 0xA0) */ +__IO uint32_t mac_csr_cmd; /**< MAC CSR Synchronizer Cmd (offset 0xA4) */ +__IO uint32_t mac_csr_data; /**< MAC CSR Synchronizer Data (offset 0xA8) */ +__IO uint32_t afc_cfg; /**< AutomaticFlow Ctrl Config (offset 0xAC) */ +__IO uint32_t eeprom_cmd; /**< EEPROM Command (offset 0xB0) */ +__IO uint32_t eeprom_data; /**< EEPROM Data (offset 0xB4) */ +}; + +/** + * \brief TX FIFO Size definitions + * + */ +#define TX_STATUS_FIFO_SIZE_BYTES 512U /*< fixed allocation in bytes */ +#define TX_DATA_FIFO_SIZE_KBYTES_POS 16U +#define TX_DATA_FIFO_SIZE_KBYTES_MASK 0x0FU +#define KBYTES_TO_BYTES_MULTIPLIER 1024U + +/** + * \brief FIFO Info definitions + * + */ +#define FIFO_USED_SPACE_MASK 0xFFFFU +#define DATA_FIFO_USED_SPACE_POS 0U +#define STATUS_FIFO_USED_SPACE_POS 16U + +/** + * \brief MAC CSR Synchronizer Command bit definitions + * + */ +enum mac_csr_cmd_bits_t{ + MAC_CSR_CMD_RW_INDEX = 30U, + MAC_CSR_CMD_BUSY_INDEX = 31U, +}; + +#define MAC_CSR_CMD_ADDRESS_MASK 0x0FU + +/** + * \brief MAC Control register bit definitions + * + */ +enum mac_reg_cr_bits_t{ + MAC_REG_CR_RXEN_INDEX = 2U, + MAC_REG_CR_TXEN_INDEX = 3U +}; + +/** + * \brief MII Access register bit definitions + * + */ +enum mac_reg_mii_acc_bits_t{ + MAC_REG_MII_ACC_BUSY_INDEX = 0U, + MAC_REG_MII_ACC_WRITE_INDEX = 1U, + MAC_REG_MII_ACC_PHYADDR_INDEX = 11U +}; +#define MAC_REG_MII_ACC_MII_REG_MASK 0x1FU +#define MAC_REG_MII_ACC_MII_REG_OFFSET 6U + +/** + * \brief Hardware config register bit definitions + * + */ +enum hw_cfg_reg_bits_t{ + HW_CFG_REG_SRST_INDEX = 0U, + HW_CFG_REG_SRST_TIMEOUT_INDEX = 1U, + HW_CFG_REG_MUST_BE_ONE_INDEX = 20U, +}; +#define HW_CFG_REG_TX_FIFO_SIZE_POS 16U +#define HW_CFG_REG_TX_FIFO_SIZE_MIN 2U /*< Min Tx fifo size in KB */ +#define HW_CFG_REG_TX_FIFO_SIZE_MAX 14U /*< Max Tx fifo size in KB */ +#define HW_CFG_REG_TX_FIFO_SIZE 5U /*< Tx fifo size in KB */ + +/** + * \brief EEPROM command register bit definitions + * + */ +enum eeprom_cmd_reg_bits_t{ + EEPROM_CMD_REG_BUSY_INDEX = 31U, +}; + +/** + * \brief PHY Basic Control register bit definitions + * + */ +enum phy_reg_bctrl_reg_bits_t{ + PHY_REG_BCTRL_RST_AUTO_NEG_INDEX = 9U, + PHY_REG_BCTRL_AUTO_NEG_EN_INDEX = 12U, + PHY_REG_BCTRL_RESET_INDEX = 15U +}; + +/** + * \brief TX Command A bit definitions + * + */ + +#define TX_CMD_DATA_START_OFFSET_BYTES_POS 16U +#define TX_CMD_DATA_START_OFFSET_BYTES_MASK 0x1FU + + +enum tx_command_a_bits_t{ + TX_COMMAND_A_LAST_SEGMENT_INDEX = 12U, + TX_COMMAND_A_FIRST_SEGMENT_INDEX = 13U +}; + +#define TX_CMD_PKT_LEN_BYTES_MASK 0x7FFU +#define TX_CMD_PKT_TAG_MASK 0xFFFFU +#define TX_CMD_PKT_TAG_POS 16U + + +/** + * \brief RX Fifo Status bit definitions + * + */ +enum rx_fifo_status_bits_t{ + RX_FIFO_STATUS_ERROR_INDEX = 15U +}; +#define RX_FIFO_STATUS_PKT_LENGTH_POS 16U +#define RX_FIFO_STATUS_PKT_LENGTH_MASK 0x3FFFU + +/** + * \brief Interrupt Configuration register bit definitions + * + */ +enum irq_cfg_bits_t{ + IRQ_CFG_IRQ_EN_INDEX = 8U +}; + +#define IRQ_CFG_INT_DEAS_MASK 0xFFU +#define IRQ_CFG_INT_DEAS_POS 24U +#define IRQ_CFG_INT_DEAS_10US 0x22U + +/** + * \brief Automatic Flow Control register bit definitions + * + */ +enum afc_bits_t{ + AFC_ANY_INDEX = 0U, + AFC_ADDR_INDEX = 1U, + AFC_BROADCAST_INDEX = 2U, + AFC_MULTICAST_INDEX = 3U +}; + +#define AFC_BACK_DUR_MASK 0x0FU +#define AFC_BACK_DUR_POS 4U +#define AFC_BACK_DUR 4U /**< equal to 50us */ + +#define AFC_LOW_LEVEL_MASK 0xFFU +#define AFC_LOW_LEVEL_POS 8U +#define AFC_LOW_LEVEL 55U /**< specifies in multiple of 64 bytes */ + +#define AFC_HIGH_LEVEL_MASK 0xFFU +#define AFC_HIGH_LEVEL_POS 16U +#define AFC_HIGH_LEVEL 110U /**< specifies in multiple of 64 bytes */ + +/** + * \brief Auto-Negotiation Advertisement register bit definitions + * + */ +enum aneg_bits_t{ + ANEG_10_BASE_T_INDEX = 5U, /**< 10Mbps able */ + ANEG_10_BASE_T_FULL_DUPL_INDEX = 6U, /**< 10Mbps with full duplex */ + ANEG_100_BASE_TX_INDEX = 7U, /**< 100Mbps Tx able */ + ANEG_100_BASE_TX_FULL_DUPL_INDEX = 8U, /**< 100Mbps with full duplex */ + ANEG_SYMM_PAUSE_INDEX = 10U, /**< Symmetric Pause */ + ANEG_ASYMM_PAUSE_INDEX = 11U /**< Asymmetric Pause */ +}; + +/** + * \brief Transmit Configuration register bit definitions + * + */ +enum tx_cfg_bits_t{ + TX_CFG_STOP_INDEX = 0U, /*< stop */ + TX_CFG_ON_INDEX = 1U, /*< on */ + TX_CFG_AO_INDEX = 2U, /*< allow overrun */ + TX_CFG_TXD_DUMP_INDEX = 14U, /*< Data FIFO dump */ + TX_CFG_TXS_DUMP_INDEX = 15U /*< Status FIFO dump */ +}; + +/** + * \brief Chip ID definitions + * + */ +#define CHIP_ID 0x9220U +#define CHIP_ID_MASK 0xFFFFU +#define CHIP_ID_POS 16U + +/** + * \brief GPIO Configuration register bit definitions + * + */ +enum gpio_cfg_bits_t{ + GPIO_CFG_GPIO0_PUSHPULL_INDEX = 16U, /*< GPIO0 push/pull or open-drain */ + GPIO_CFG_GPIO1_PUSHPULL_INDEX = 17U, /*< GPIO1 push/pull or open-drain */ + GPIO_CFG_GPIO2_PUSHPULL_INDEX = 18U, /*< GPIO2 push/pull or open-drain */ + GPIO_CFG_GPIO0_LED_INDEX = 28U, /*< GPIO0 set to LED1 */ + GPIO_CFG_GPIO1_LED_INDEX = 29U, /*< GPIO1 set to LED2 */ + GPIO_CFG_GPIO2_LED_INDEX = 30U /*< GPIO2 set to LED3 */ +}; + + +static void fill_tx_fifo(const struct smsc9220_eth_dev_t* dev, + uint8_t *data, uint32_t size_bytes) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + uint32_t tx_data_port_tmp = 0; + uint8_t *tx_data_port_tmp_ptr = (uint8_t *)&tx_data_port_tmp; + + /*If the data length is not a multiple of 4, then the beginning of the first + * DWORD of the TX DATA FIFO gets filled up with zeros and a byte offset is + * set accordingly to guarantee proper transmission.*/ + uint32_t remainder_bytes = (size_bytes % 4); + uint32_t filler_bytes = (4 - remainder_bytes); + for(uint32_t i = 0; i < 4; i++){ + if(i < filler_bytes){ + tx_data_port_tmp_ptr[i] = 0; + } else { + tx_data_port_tmp_ptr[i] = data[i-filler_bytes]; + } + } + register_map->tx_data_port = tx_data_port_tmp; + size_bytes -= remainder_bytes; + data += remainder_bytes; + + while (size_bytes > 0) { + /* Keep the same endianness in data than in the temp variable */ + tx_data_port_tmp_ptr[0] = data[0]; + tx_data_port_tmp_ptr[1] = data[1]; + tx_data_port_tmp_ptr[2] = data[2]; + tx_data_port_tmp_ptr[3] = data[3]; + register_map->tx_data_port = tx_data_port_tmp; + data += 4; + size_bytes -= 4; + } +} + +static void empty_rx_fifo(const struct smsc9220_eth_dev_t* dev, + uint8_t *data, uint32_t size_bytes) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + uint32_t rx_data_port_tmp = 0; + uint8_t *rx_data_port_tmp_ptr = (uint8_t *)&rx_data_port_tmp; + + uint32_t remainder_bytes = (size_bytes % 4); + size_bytes -= remainder_bytes; + + while (size_bytes > 0) { + /* Keep the same endianness in data than in the temp variable */ + rx_data_port_tmp = register_map->rx_data_port; + data[0] = rx_data_port_tmp_ptr[0]; + data[1] = rx_data_port_tmp_ptr[1]; + data[2] = rx_data_port_tmp_ptr[2]; + data[3] = rx_data_port_tmp_ptr[3]; + data += 4; + size_bytes -= 4; + } + + rx_data_port_tmp = register_map->rx_data_port; + for(uint32_t i = 0; i < remainder_bytes; i++) { + data[i] = rx_data_port_tmp_ptr[i]; + } +} + +enum smsc9220_error_t smsc9220_mac_regread( + const struct smsc9220_eth_dev_t* dev, + enum smsc9220_mac_reg_offsets_t regoffset, + uint32_t *data) +{ + volatile uint32_t val; + uint32_t maccmd = GET_BIT_FIELD(regoffset, + MAC_CSR_CMD_ADDRESS_MASK, 0); + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + /* Make sure there's no pending operation */ + if(!(GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX))) { + SET_BIT(maccmd, MAC_CSR_CMD_RW_INDEX); + SET_BIT(maccmd, MAC_CSR_CMD_BUSY_INDEX); + register_map->mac_csr_cmd = maccmd; /* Start operation */ + + do { + val = register_map->byte_test; /* A no-op read. */ + (void)val; + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while(time_out && + GET_BIT(register_map->mac_csr_cmd,MAC_CSR_CMD_BUSY_INDEX)); + + if(!time_out) { + return SMSC9220_ERROR_TIMEOUT; + } + else { + *data = register_map->mac_csr_data; + } + } else { + return SMSC9220_ERROR_BUSY; + } + return SMSC9220_ERROR_NONE; +} + +enum smsc9220_error_t smsc9220_mac_regwrite( + const struct smsc9220_eth_dev_t* dev, + enum smsc9220_mac_reg_offsets_t regoffset, + uint32_t data) +{ + volatile uint32_t read = 0; + uint32_t maccmd = GET_BIT_FIELD(regoffset, + MAC_CSR_CMD_ADDRESS_MASK, 0); + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + /* Make sure there's no pending operation */ + if(!GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX)) { + register_map->mac_csr_data = data; /* Store data. */ + CLR_BIT(maccmd, MAC_CSR_CMD_RW_INDEX); + SET_BIT(maccmd, MAC_CSR_CMD_BUSY_INDEX); + register_map->mac_csr_cmd = maccmd; + + do { + read = register_map->byte_test; /* A no-op read. */ + (void)read; + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while(time_out && + (register_map->mac_csr_cmd & + GET_BIT(register_map->mac_csr_cmd, MAC_CSR_CMD_BUSY_INDEX))); + + if(!time_out) { + return SMSC9220_ERROR_TIMEOUT; + } + } else { + return SMSC9220_ERROR_BUSY; + } + return SMSC9220_ERROR_NONE; +} + +enum smsc9220_error_t smsc9220_phy_regread( + const struct smsc9220_eth_dev_t* dev, + enum phy_reg_offsets_t regoffset, + uint32_t *data) +{ + uint32_t val = 0; + uint32_t phycmd = 0; + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_MII_ACC, &val)) { + return SMSC9220_ERROR_INTERNAL; + } + + if(!GET_BIT(val, MAC_REG_MII_ACC_BUSY_INDEX)) { + phycmd = 0; + SET_BIT(phycmd, MAC_REG_MII_ACC_PHYADDR_INDEX); + SET_BIT_FIELD(phycmd, MAC_REG_MII_ACC_MII_REG_MASK, + MAC_REG_MII_ACC_MII_REG_OFFSET, regoffset); + CLR_BIT(phycmd, MAC_REG_MII_ACC_WRITE_INDEX); + SET_BIT(phycmd, MAC_REG_MII_ACC_BUSY_INDEX); + + if (smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_MII_ACC, + phycmd)) { + return SMSC9220_ERROR_INTERNAL; + } + + val = 0; + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_MII_ACC, + &val)) { + return SMSC9220_ERROR_INTERNAL; + } + } while(time_out && (GET_BIT(val, MAC_REG_MII_ACC_BUSY_INDEX))); + + if (!time_out) { + return SMSC9220_ERROR_TIMEOUT; + } else if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_MII_DATA, + data)) { + return SMSC9220_ERROR_INTERNAL; + } + } else { + return SMSC9220_ERROR_BUSY; + } + return SMSC9220_ERROR_NONE; +} + +enum smsc9220_error_t smsc9220_phy_regwrite( + const struct smsc9220_eth_dev_t* dev, + enum phy_reg_offsets_t regoffset, + uint32_t data) +{ + uint32_t val = 0; + uint32_t phycmd = 0; + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_MII_ACC, &val)) { + return SMSC9220_ERROR_INTERNAL; + } + + if(!GET_BIT(val, MAC_REG_MII_ACC_BUSY_INDEX)) { + /* Load the data */ + if (smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_MII_DATA, + (data & 0xFFFF))) { + return SMSC9220_ERROR_INTERNAL; + } + phycmd = 0; + SET_BIT(phycmd, MAC_REG_MII_ACC_PHYADDR_INDEX); + SET_BIT_FIELD(phycmd, MAC_REG_MII_ACC_MII_REG_MASK, + MAC_REG_MII_ACC_MII_REG_OFFSET, regoffset); + SET_BIT(phycmd, MAC_REG_MII_ACC_WRITE_INDEX); + SET_BIT(phycmd, MAC_REG_MII_ACC_BUSY_INDEX); + /* Start operation */ + if (smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_MII_ACC, + phycmd)) { + return SMSC9220_ERROR_INTERNAL; + } + + phycmd = 0; + + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_MII_ACC, + &phycmd)){ + return SMSC9220_ERROR_INTERNAL; + } + } while(time_out && GET_BIT(phycmd, 0)); + + if (!time_out) { + return SMSC9220_ERROR_TIMEOUT; + } + + } else { + return SMSC9220_ERROR_BUSY; + } + return SMSC9220_ERROR_NONE; +} + +uint32_t smsc9220_read_id(const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + return register_map->id_revision; +} + +enum smsc9220_error_t smsc9220_soft_reset( + const struct smsc9220_eth_dev_t* dev) +{ + uint32_t time_out = RESET_TIME_OUT_MS; + + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + /* Soft reset */ + SET_BIT(register_map->hw_cfg, HW_CFG_REG_SRST_INDEX); + + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while(time_out && + GET_BIT(register_map->hw_cfg, HW_CFG_REG_SRST_TIMEOUT_INDEX)); + + if (!time_out) { + return SMSC9220_ERROR_TIMEOUT; + } + + return SMSC9220_ERROR_NONE; +} + +void smsc9220_set_txfifo(const struct smsc9220_eth_dev_t* dev, + uint32_t val) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + if(val >= HW_CFG_REG_TX_FIFO_SIZE_MIN && + val <= HW_CFG_REG_TX_FIFO_SIZE_MAX) { + register_map->hw_cfg = val << HW_CFG_REG_TX_FIFO_SIZE_POS; + } +} + +enum smsc9220_error_t smsc9220_set_fifo_level_irq( + const struct smsc9220_eth_dev_t* dev, + enum smsc9220_fifo_level_irq_pos_t irq_level_pos, + uint32_t level) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + if (level < SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MIN || + level > SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MAX) { + return SMSC9220_ERROR_PARAM; + } + + CLR_BIT_FIELD(register_map->fifo_level_irq, SMSC9220_FIFO_LEVEL_IRQ_MASK, + irq_level_pos, SMSC9220_FIFO_LEVEL_IRQ_MASK); + SET_BIT_FIELD(register_map->fifo_level_irq, SMSC9220_FIFO_LEVEL_IRQ_MASK, + irq_level_pos, level); + return SMSC9220_ERROR_NONE; +} + +enum smsc9220_error_t smsc9220_wait_eeprom( + const struct smsc9220_eth_dev_t* dev) +{ + uint32_t time_out = REG_WRITE_TIME_OUT_MS; + + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + do { + if (dev->data->wait_ms) { + dev->data->wait_ms(1); + } + time_out--; + } while(time_out && + GET_BIT(register_map->eeprom_cmd, EEPROM_CMD_REG_BUSY_INDEX)); + + if (!time_out) { + return SMSC9220_ERROR_TIMEOUT; + } + + return SMSC9220_ERROR_NONE; +} + +void smsc9220_init_irqs(const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + smsc9220_disable_all_interrupts(dev); + smsc9220_clear_all_interrupts(dev); + + /* Set IRQ deassertion interval */ + SET_BIT_FIELD(register_map->irq_cfg, IRQ_CFG_INT_DEAS_MASK, + IRQ_CFG_INT_DEAS_POS, IRQ_CFG_INT_DEAS_10US); + + /* enable interrupts */ + SET_BIT(register_map->irq_cfg, IRQ_CFG_IRQ_EN_INDEX); +} + +enum smsc9220_error_t smsc9220_check_phy(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t phyid1 = 0; + uint32_t phyid2 = 0; + + if (smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_ID1,&phyid1)) { + return SMSC9220_ERROR_INTERNAL; + } + if (smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_ID2,&phyid2)) { + return SMSC9220_ERROR_INTERNAL; + } + if ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || + (phyid1 == 0x0 && phyid2 == 0x0)) { + return SMSC9220_ERROR_INTERNAL; + } + return SMSC9220_ERROR_NONE; +} + +enum smsc9220_error_t smsc9220_reset_phy(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t read = 0; + + if(smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_BCTRL, &read)) { + return SMSC9220_ERROR_INTERNAL; + } + + SET_BIT(read, PHY_REG_BCTRL_RESET_INDEX); + if(smsc9220_phy_regwrite(dev, SMSC9220_PHY_REG_OFFSET_BCTRL, read)) { + return SMSC9220_ERROR_INTERNAL; + } + return SMSC9220_ERROR_NONE; +} + +void smsc9220_advertise_cap(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t aneg_adv = 0; + smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_ANEG_ADV, &aneg_adv); + + SET_BIT(aneg_adv, ANEG_10_BASE_T_INDEX); + SET_BIT(aneg_adv, ANEG_10_BASE_T_FULL_DUPL_INDEX); + SET_BIT(aneg_adv, ANEG_100_BASE_TX_INDEX); + SET_BIT(aneg_adv, ANEG_100_BASE_TX_FULL_DUPL_INDEX); + SET_BIT(aneg_adv, ANEG_SYMM_PAUSE_INDEX); + SET_BIT(aneg_adv, ANEG_ASYMM_PAUSE_INDEX); + + smsc9220_phy_regwrite(dev, SMSC9220_PHY_REG_OFFSET_ANEG_ADV, aneg_adv); +} + +void smsc9220_enable_xmit(const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + SET_BIT(register_map->tx_cfg, TX_CFG_ON_INDEX); +} + +void smsc9220_disable_xmit(const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + CLR_BIT(register_map->tx_cfg, TX_CFG_ON_INDEX); +} + +void smsc9220_enable_mac_xmit(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t mac_cr = 0; + smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_CR, &mac_cr); + + SET_BIT(mac_cr, MAC_REG_CR_TXEN_INDEX); + + smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_CR, mac_cr); +} + +void smsc9220_disable_mac_xmit(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t mac_cr = 0; + smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_CR, &mac_cr); + + CLR_BIT(mac_cr, MAC_REG_CR_TXEN_INDEX); + + smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_CR, mac_cr); +} + +void smsc9220_enable_mac_recv(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t mac_cr = 0; + smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_CR, &mac_cr); + + SET_BIT(mac_cr, MAC_REG_CR_RXEN_INDEX); + + smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_CR, mac_cr); +} + +void smsc9220_disable_mac_recv(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t mac_cr = 0; + smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_CR, &mac_cr); + + CLR_BIT(mac_cr, MAC_REG_CR_RXEN_INDEX); + + smsc9220_mac_regwrite(dev, SMSC9220_MAC_REG_OFFSET_CR, mac_cr); +} + +int smsc9220_check_id(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t id = smsc9220_read_id(dev); + + return ((GET_BIT_FIELD(id, CHIP_ID_MASK, CHIP_ID_POS) == CHIP_ID) ? 0 : 1); +} + + +void smsc9220_enable_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + SET_BIT(register_map->irq_enable, source); +} + +void smsc9220_disable_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + CLR_BIT(register_map->irq_enable, source); +} + +void smsc9220_disable_all_interrupts(const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + register_map->irq_enable = 0; +} + +void smsc9220_clear_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + SET_BIT(register_map->irq_status, source); +} + +void smsc9220_clear_all_interrupts(const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + register_map->irq_status = UINT32_MAX; +} + +int smsc9220_get_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + return GET_BIT(register_map->irq_status, source); +} + +void smsc9220_establish_link(const struct smsc9220_eth_dev_t* dev) +{ + uint32_t bcr = 0; + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_BCTRL, &bcr); + SET_BIT(bcr, PHY_REG_BCTRL_AUTO_NEG_EN_INDEX); + SET_BIT(bcr, PHY_REG_BCTRL_RST_AUTO_NEG_INDEX); + smsc9220_phy_regwrite(dev, SMSC9220_PHY_REG_OFFSET_BCTRL, bcr); + + SET_BIT(register_map->hw_cfg, HW_CFG_REG_MUST_BE_ONE_INDEX); +} + +enum smsc9220_error_t smsc9220_read_mac_address( + const struct smsc9220_eth_dev_t* dev, char *mac) +{ + uint32_t mac_low = 0; + uint32_t mac_high = 0; + + if(!mac) { + return SMSC9220_ERROR_PARAM; + } + + /* Read current mac address. */ + if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_ADDRH, &mac_high)) { + return SMSC9220_ERROR_INTERNAL; + } + if (smsc9220_mac_regread(dev, SMSC9220_MAC_REG_OFFSET_ADDRL, &mac_low)) { + return SMSC9220_ERROR_INTERNAL; + } + mac[0] = mac_low & 0xFF; + mac[1] = (mac_low >> 8) & 0xFF; + mac[2] = (mac_low >> 16) & 0xFF; + mac[3] = (mac_low >> 24) & 0xFF; + mac[4] = mac_high & 0xFF; + mac[5] = (mac_high >> 8) & 0xFF; + + return SMSC9220_ERROR_NONE; +} + +uint32_t smsc9220_get_tx_data_fifo_size( + const struct smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + uint32_t tx_fifo_size = + GET_BIT_FIELD(register_map->hw_cfg, + TX_DATA_FIFO_SIZE_KBYTES_MASK, + TX_DATA_FIFO_SIZE_KBYTES_POS) * KBYTES_TO_BYTES_MULTIPLIER; + + return (tx_fifo_size - TX_STATUS_FIFO_SIZE_BYTES); +} + +enum smsc9220_error_t smsc9220_init( + const struct smsc9220_eth_dev_t* dev, + void(* wait_ms_function)(int)) +{ + uint32_t phyreset = 0; + enum smsc9220_error_t error = SMSC9220_ERROR_NONE; + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + if (!wait_ms_function) { + return SMSC9220_ERROR_PARAM; + } + dev->data->wait_ms = wait_ms_function; + + error = smsc9220_check_id(dev); + if(error != SMSC9220_ERROR_NONE) { + return error; + } + + error = smsc9220_soft_reset(dev); + if(error != SMSC9220_ERROR_NONE) { + return error; + } + + smsc9220_set_txfifo(dev, HW_CFG_REG_TX_FIFO_SIZE); + + SET_BIT_FIELD(register_map->afc_cfg, AFC_BACK_DUR_MASK, + AFC_BACK_DUR_POS, AFC_BACK_DUR); + SET_BIT_FIELD(register_map->afc_cfg, AFC_LOW_LEVEL_MASK, + AFC_LOW_LEVEL_POS, AFC_LOW_LEVEL); + SET_BIT_FIELD(register_map->afc_cfg, AFC_HIGH_LEVEL_MASK, + AFC_HIGH_LEVEL_POS, AFC_HIGH_LEVEL); + + error = smsc9220_wait_eeprom(dev); + if(error != SMSC9220_ERROR_NONE) { + return error; + } + + /* Configure GPIOs as LED outputs. */ + register_map->gpio_cfg = 0; + SET_BIT(register_map->gpio_cfg, GPIO_CFG_GPIO0_PUSHPULL_INDEX); + SET_BIT(register_map->gpio_cfg, GPIO_CFG_GPIO1_PUSHPULL_INDEX); + SET_BIT(register_map->gpio_cfg, GPIO_CFG_GPIO2_PUSHPULL_INDEX); + SET_BIT(register_map->gpio_cfg, GPIO_CFG_GPIO0_LED_INDEX); + SET_BIT(register_map->gpio_cfg, GPIO_CFG_GPIO1_LED_INDEX); + SET_BIT(register_map->gpio_cfg, GPIO_CFG_GPIO2_LED_INDEX); + + smsc9220_init_irqs(dev); + + /* Configure MAC addresses here if needed. */ + + error = smsc9220_check_phy(dev); + if(error != SMSC9220_ERROR_NONE) { + return error; + } + + error = smsc9220_reset_phy(dev); + if(error != SMSC9220_ERROR_NONE) { + return error; + } + + if (dev->data->wait_ms) { + dev->data->wait_ms(PHY_RESET_TIME_OUT_MS); + } + /* Checking whether phy reset completed successfully.*/ + error = smsc9220_phy_regread(dev, SMSC9220_PHY_REG_OFFSET_BCTRL, + &phyreset); + if(error != SMSC9220_ERROR_NONE) { + return error; + } + + if(GET_BIT(phyreset, PHY_REG_BCTRL_RESET_INDEX)) { + return SMSC9220_ERROR_INTERNAL; + } + + smsc9220_advertise_cap(dev); + smsc9220_establish_link(dev); + + smsc9220_enable_mac_xmit(dev); + smsc9220_enable_xmit(dev); + smsc9220_enable_mac_recv(dev); + + /* This sleep is compulsory otherwise txmit/receive will fail. */ + if (dev->data->wait_ms) { + dev->data->wait_ms(INIT_FINISH_DELAY); + } + dev->data->state = 1; + + return SMSC9220_ERROR_NONE; +} + +enum smsc9220_error_t smsc9220_send_by_chunks( + const struct smsc9220_eth_dev_t* dev, + uint32_t total_payload_length, + bool is_new_packet, + const char *data, uint32_t current_size) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + /* signing this is the first segment of the packet to be sent */ + bool is_first_segment = false; + /* signing this is the last segment of the packet to be sent */ + bool is_last_segment = false; + uint32_t txcmd_a, txcmd_b = 0; + uint32_t tx_buffer_free_space = 0; + volatile uint32_t xmit_stat = 0; + + if (!data) { + return SMSC9220_ERROR_PARAM; + } + + if (is_new_packet) { + is_first_segment = true; + dev->data->ongoing_packet_length = total_payload_length; + dev->data->ongoing_packet_length_sent = 0; + } else if (dev->data->ongoing_packet_length != total_payload_length || + dev->data->ongoing_packet_length_sent >= total_payload_length) { + return SMSC9220_ERROR_PARAM; + } + + /* Would next chunk fit into buffer? */ + tx_buffer_free_space = GET_BIT_FIELD(register_map->tx_fifo_inf, + FIFO_USED_SPACE_MASK, + DATA_FIFO_USED_SPACE_POS); + if (current_size > tx_buffer_free_space) { + return SMSC9220_ERROR_INTERNAL; /* Not enough space in FIFO */ + } + if ((dev->data->ongoing_packet_length_sent + current_size) == + total_payload_length) { + is_last_segment = true; + } + + txcmd_a = 0; + txcmd_b = 0; + + if (is_last_segment) { + SET_BIT(txcmd_a, TX_COMMAND_A_LAST_SEGMENT_INDEX); + } + if (is_first_segment) { + SET_BIT(txcmd_a, TX_COMMAND_A_FIRST_SEGMENT_INDEX); + } + + uint32_t data_start_offset_bytes = (4 - (current_size % 4)); + + SET_BIT_FIELD(txcmd_a, TX_CMD_PKT_LEN_BYTES_MASK, 0, current_size); + SET_BIT_FIELD(txcmd_a, TX_CMD_DATA_START_OFFSET_BYTES_MASK, + TX_CMD_DATA_START_OFFSET_BYTES_POS, + data_start_offset_bytes); + + SET_BIT_FIELD(txcmd_b, TX_CMD_PKT_LEN_BYTES_MASK, 0, current_size); + SET_BIT_FIELD(txcmd_b, TX_CMD_PKT_TAG_MASK, TX_CMD_PKT_TAG_POS, + current_size); + + register_map->tx_data_port = txcmd_a; + register_map->tx_data_port = txcmd_b; + + fill_tx_fifo(dev, (uint8_t *)data, current_size); + + if (is_last_segment) { + /* Pop status port for error check */ + xmit_stat = register_map->tx_status_port; + (void)xmit_stat; + } + dev->data->ongoing_packet_length_sent += current_size; + return SMSC9220_ERROR_NONE; +} + +uint32_t smsc9220_get_rxfifo_data_used_space(const struct + smsc9220_eth_dev_t* dev) +{ + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + return GET_BIT_FIELD(register_map->rx_fifo_inf, FIFO_USED_SPACE_MASK, + DATA_FIFO_USED_SPACE_POS); +} + +uint32_t smsc9220_receive_by_chunks(const struct smsc9220_eth_dev_t* dev, + char *data, uint32_t dlen) +{ + + uint32_t rxfifo_inf = 0; + uint32_t rxfifo_stat = 0; + uint32_t packet_length_byte = 0; + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + if (!data) { + return 0; /* Invalid input parameter, cannot read */ + } + rxfifo_inf = register_map->rx_fifo_inf; + + if(rxfifo_inf & 0xFFFF) { /* If there's data */ + rxfifo_stat = register_map->rx_status_port; + if(rxfifo_stat != 0) { /* Fetch status of this packet */ + /* Ethernet controller is padding to 32bit aligned data */ + packet_length_byte = GET_BIT_FIELD(rxfifo_stat, + RX_FIFO_STATUS_PKT_LENGTH_MASK, + RX_FIFO_STATUS_PKT_LENGTH_POS); + packet_length_byte -= 4; + dev->data->current_rx_size_words = packet_length_byte; + } + } + + empty_rx_fifo(dev, (uint8_t *)data, packet_length_byte); + dev->data->current_rx_size_words = 0; + return packet_length_byte; +} + +uint32_t smsc9220_peek_next_packet_size(const struct + smsc9220_eth_dev_t* dev) +{ + uint32_t packet_size = 0; + struct smsc9220_eth_reg_map_t* register_map = + (struct smsc9220_eth_reg_map_t*)dev->cfg->base; + + if(smsc9220_get_rxfifo_data_used_space(dev)) { + packet_size = GET_BIT_FIELD(register_map->rx_status_peek, + RX_FIFO_STATUS_PKT_LENGTH_MASK, + RX_FIFO_STATUS_PKT_LENGTH_POS); + } + return packet_size; +} diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h new file mode 100644 index 00000000000..aa60b4f95fb --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth_drv.h @@ -0,0 +1,548 @@ +/* + * Copyright (c) 2016-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file smsc9220_drv.h + * \brief Generic driver for SMSC9220 Ethernet controller + */ + +#ifndef __SMSC9220_ETH_H__ +#define __SMSC9220_ETH_H__ + +#include "stdbool.h" +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** SMSC9220 device configuration structure */ +struct smsc9220_eth_dev_cfg_t { + const uint32_t base; /*!< SMSC9220 base address */ +}; + +/** SMSC9220 device data structure */ +struct smsc9220_eth_dev_data_t { + uint32_t state; /*!< Indicates if the SMSC9220 driver + is initialized and enabled */ + void (*wait_ms) (int);/*!< function pointer to system's millisec delay + function, will be used for delays */ + uint32_t ongoing_packet_length;/*!< size in bytes of the packet + is being sent */ + uint32_t ongoing_packet_length_sent; /*!< size in bytes of the packet + has been sent */ + uint32_t current_rx_size_words; /*!< Data length in words, + currently is being read */ +}; + +/** SMSC9220 device structure */ +struct smsc9220_eth_dev_t { + const struct smsc9220_eth_dev_cfg_t* const cfg; /*!< configuration */ + struct smsc9220_eth_dev_data_t* const data; /*!< data */ +}; + +/** + * \brief Error code definitions + * + */ +enum smsc9220_error_t{ + SMSC9220_ERROR_NONE = 0U, /*!< no error */ + SMSC9220_ERROR_TIMEOUT = 1U, /*!< timeout */ + SMSC9220_ERROR_BUSY = 2U, /*!< no error */ + SMSC9220_ERROR_PARAM = 3U, /*!< invalid parameter */ + SMSC9220_ERROR_INTERNAL = 4U /*!< internal error */ +}; + +/** + * \brief Interrupt source definitions + * + */ +enum smsc9220_interrupt_source { + SMSC9220_INTERRUPT_GPIO0 = 0U, + SMSC9220_INTERRUPT_GPIO1 = 1U, + SMSC9220_INTERRUPT_GPIO2 = 2U, + SMSC9220_INTERRUPT_RX_STATUS_FIFO_LEVEL = 3U, + SMSC9220_INTERRUPT_RX_STATUS_FIFO_FULL = 4U, + /* 5 Reserved according to Datasheet */ + SMSC9220_INTERRUPT_RX_DROPPED_FRAME = 6U, + SMSC9220_INTERRUPT_TX_STATUS_FIFO_LEVEL = 7U, + SMSC9220_INTERRUPT_TX_STATUS_FIFO_FULL = 8U, + SMSC9220_INTERRUPT_TX_DATA_FIFO_AVAILABLE = 9U, + SMSC9220_INTERRUPT_TX_DATA_FIFO_OVERRUN = 10U, + /* 11, 12 Reserved according to Datasheet */ + SMSC9220_INTERRUPT_TX_ERROR = 13U, + SMSC9220_INTERRUPT_RX_ERROR = 14U, + SMSC9220_INTERRUPT_RX_WATCHDOG_TIMEOUT = 15U, + SMSC9220_INTERRUPT_TX_STATUS_OVERFLOW = 16U, + SMSC9220_INTERRUPT_TX_POWER_MANAGEMENT = 17U, + SMSC9220_INTERRUPT_PHY = 18U, + SMSC9220_INTERRUPT_GP_TIMER = 19U, + SMSC9220_INTERRUPT_RX_DMA = 20U, + SMSC9220_INTERRUPT_TX_IOC = 21U, + /* 22 Reserved according to Datasheet*/ + SMSC9220_INTERRUPT_RX_DROPPED_FRAME_HALF = 23U, + SMSC9220_INTERRUPT_RX_STOPPED = 24U, + SMSC9220_INTERRUPT_TX_STOPPED = 25U, + /* 26 - 30 Reserved according to Datasheet*/ + SMSC9220_INTERRUPT_SW = 31U +}; + +/** + * \brief MAC register offset definitions + * + */ +enum smsc9220_mac_reg_offsets_t{ + SMSC9220_MAC_REG_OFFSET_CR = 0x1U, + SMSC9220_MAC_REG_OFFSET_ADDRH = 0x2U, + SMSC9220_MAC_REG_OFFSET_ADDRL = 0x3U, + SMSC9220_MAC_REG_OFFSET_HASHH = 0x4U, + SMSC9220_MAC_REG_OFFSET_HASHL = 0x5U, + SMSC9220_MAC_REG_OFFSET_MII_ACC = 0x6U, + SMSC9220_MAC_REG_OFFSET_MII_DATA = 0x7U, + SMSC9220_MAC_REG_OFFSET_FLOW = 0x8U, + SMSC9220_MAC_REG_OFFSET_VLAN1 = 0x9U, + SMSC9220_MAC_REG_OFFSET_VLAN2 = 0xAU, + SMSC9220_MAC_REG_OFFSET_WUFF = 0xBU, + SMSC9220_MAC_REG_OFFSET_WUCSR = 0xCU, + SMSC9220_MAC_REG_OFFSET_COE_CR = 0xDU +}; + +/** + * \brief PHY register offset definitions + * + */ +enum phy_reg_offsets_t{ + SMSC9220_PHY_REG_OFFSET_BCTRL = 0x0U, + SMSC9220_PHY_REG_OFFSET_BSTATUS = 0x1U, + SMSC9220_PHY_REG_OFFSET_ID1 = 0x2U, + SMSC9220_PHY_REG_OFFSET_ID2 = 0x3U, + SMSC9220_PHY_REG_OFFSET_ANEG_ADV = 0x4U, + SMSC9220_PHY_REG_OFFSET_ANEG_LPA = 0x5U, + SMSC9220_PHY_REG_OFFSET_ANEG_EXP = 0x6U, + SMSC9220_PHY_REG_OFFSET_MCONTROL = 0x17U, + SMSC9220_PHY_REG_OFFSET_MSTATUS = 0x18U, + SMSC9220_PHY_REG_OFFSET_CSINDICATE = 0x27U, + SMSC9220_PHY_REG_OFFSET_INTSRC = 0x29U, + SMSC9220_PHY_REG_OFFSET_INTMASK = 0x30U, + SMSC9220_PHY_REG_OFFSET_CS = 0x31U +}; + +/* Bit definitions for PHY Basic Status Register */ +#define PHY_REG_BSTATUS_EXTENDED_CAPABILITIES_INDEX 0U +#define PHY_REG_BSTATUS_JABBER_DETECT_INDEX 1U +#define PHY_REG_BSTATUS_LINK_STATUS_INDEX 2U +#define PHY_REG_BSTATUS_AUTO_NEG_ABILITY_INDEX 3U +#define PHY_REG_BSTATUS_REMOTE_FAULT_INDEX 4U +#define PHY_REG_BSTATUS_AUTO_NEG_COMPLETE_INDEX 5U +#define PHY_REG_BSTATUS_10BASE_T_HALF_DUPLEX_INDEX 11U +#define PHY_REG_BSTATUS_10BASE_T_FULL_DUPLEX_INDEX 12U +#define PHY_REG_BSTATUS_100BASE_TX_HALF_DUPLEX_INDEX 13U +#define PHY_REG_BSTATUS_100BASE_TX_FULL_DUPLEX_INDEX 14U +#define PHY_REG_BSTATUS_100BASE_T4_INDEX 15U + +/** + * \brief FIFO Level Interrupt bit definitions + * + */ +enum smsc9220_fifo_level_irq_pos_t{ + SMSC9220_FIFO_LEVEL_IRQ_RX_STATUS_POS = 0U, + SMSC9220_FIFO_LEVEL_IRQ_TX_STATUS_POS = 16U, + SMSC9220_FIFO_LEVEL_IRQ_TX_DATA_POS = 24U +}; + +/** + * \brief FIFO Level Interrupt limits + * + */ +#define SMSC9220_FIFO_LEVEL_IRQ_MASK 0xFFU +#define SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MIN 0U +#define SMSC9220_FIFO_LEVEL_IRQ_LEVEL_MAX SMSC9220_FIFO_LEVEL_IRQ_MASK + +/** + * \brief Initializes SMSC9220 Ethernet controller to a known default state: + * - device ID is checked + * - global interrupt is enabled, but all irq sources are disabled + * - all capabilities are advertised + * - 10Mbps able + * - 10Mbps with full duplex + * - 100Mbps Tx able + * - 100Mbps with full duplex + * - Symmetric Pause + * - Asymmetric Pause + * - Establish link enabled + * - Rx enabled + * - Tx enabled + * Init should be called prior to any other process and + * it's the caller's responsibility to follow proper call order. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] wait_ms_function function pointer to a millisec delay function + * for proper timing of some processes + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_init(const struct smsc9220_eth_dev_t* dev, + void(* wait_ms_function)(int)); + +/** + * \brief Read MAC register. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] regoffset Register offset + * \param[in, out] data Pointer to register will be read + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_mac_regread( + const struct smsc9220_eth_dev_t* dev, + enum smsc9220_mac_reg_offsets_t regoffset, + uint32_t *data); + +/** + * \brief Write MAC register. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] regoffset Register offset + * \param[in] data Register value to write + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_mac_regwrite( + const struct smsc9220_eth_dev_t* dev, + enum smsc9220_mac_reg_offsets_t regoffset, + uint32_t data); + +/** + * \brief Read PHY register. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] regoffset Register offset + * \param[out] data Register value is read + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_phy_regread( + const struct smsc9220_eth_dev_t* dev, + enum phy_reg_offsets_t, + uint32_t *data); + +/** + * \brief Write PHY register. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] regoffset Register offset + * \param[in] data Register value to write + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_phy_regwrite( + const struct smsc9220_eth_dev_t* dev, + enum phy_reg_offsets_t, + uint32_t data); + +/** + * \brief Read SMSC9220 ID. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return ID number + */ +uint32_t smsc9220_read_id(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Initiates a soft reset, returns failure or success. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_soft_reset( + const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Set maximum transition unit by Tx fifo size. + * Note: The MTU will be smaller by 512 bytes, + * because the status uses this fixed space. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] val Size of the fifo in kbytes + * \ref HW_CFG_REG_TX_FIFO_SIZE_MIN + * \ref HW_CFG_REG_TX_FIFO_SIZE_MAX + */ +void smsc9220_set_txfifo(const struct smsc9220_eth_dev_t* dev, + uint32_t val); + +/** + * \brief Set FIFO level interrupt for a given source + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] irq_level_pos Bit position of the FIFO to set + * \ref smsc9220_fifo_level_irq_pos_t + * \param[in] level Level of the FIFO, when the FIFO used space is greater + * than this value, corresponding interrupt will be generated. + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_set_fifo_level_irq( + const struct smsc9220_eth_dev_t* dev, + enum smsc9220_fifo_level_irq_pos_t irq_level_pos, + uint32_t level); + +/** + * \brief Wait for EEPROM to be ready to use. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_wait_eeprom( + const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Initialise irqs by clearing and disabling all interrupt sources + * and enable interrupts. Since all interrupt sources are disabled, + * interrupt won't be triggered, until interrupt sources won't be + * enabled by \ref smsc9220_enable_interrupt + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_init_irqs(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Check PHY ID registers. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_check_phy(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Reset PHY + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_reset_phy(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Advertise all speeds and pause capabilities + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_advertise_cap(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Enable transmission + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_enable_xmit(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Disable transmission + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_disable_xmit(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Enable MAC transmitter + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_enable_mac_xmit(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Disable MAC transmitter + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_disable_mac_xmit(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Enable receive + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_enable_mac_recv(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Disable receive + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_disable_mac_recv(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Enable the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] source Enum of the interrupt source. + */ +void smsc9220_enable_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source); + +/** + * \brief Disable the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] source Enum of the interrupt source. + */ +void smsc9220_disable_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source); + +/** + * \brief Disable all of the interrupt sources. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_disable_all_interrupts(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Clear the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] source Enum of the interrupt source. + */ +void smsc9220_clear_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source); + +/** + * \brief Clear all of the interrupt sources. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_clear_all_interrupts(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Get the status of the given interrupt source. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] source Enum of the interrupt source. + * + * \return non-zero if the given interrupt source is triggered, zero otherwise + */ +int smsc9220_get_interrupt(const struct smsc9220_eth_dev_t* dev, + enum smsc9220_interrupt_source source); + +/** + * \brief Establish link + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + */ +void smsc9220_establish_link(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Read MAC address from EEPROM. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in,out] mac array will include the read MAC address in + * 6 bytes hexadecimal format. + * It should be allocated by the caller to 6 bytes. + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_read_mac_address( + const struct smsc9220_eth_dev_t* dev, char *mac); + +/** + * \brief Check device ID. + * + * \return error code /ref smsc9220_error_t + */ +int smsc9220_check_id(const struct smsc9220_eth_dev_t* dev); + +/** + * \brief Get the data size of the Tx buffer, aka Maximum Transition Unit + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return Fifo data size in bytes + */ +uint32_t smsc9220_get_tx_data_fifo_size(const struct + smsc9220_eth_dev_t* dev); + +/** + * \brief Send Ethernet packet from buffer chain. + * The full packet length should be known in the beginning + * of a new packet. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in] total_payload_length Length of the ethernet payload. + * Should be equal to the sum of passed buffers within a packet. + * \param[in] is_new_packet Should be set to true if the input buffer has to + * be sent as the start of a new packet or as a full packet. + * \param[in] data Pointer to the data should be sent. + * \param[in] current_size Size of the data in bytes. + * + * \return error code /ref smsc9220_error_t + */ +enum smsc9220_error_t smsc9220_send_by_chunks( + const struct smsc9220_eth_dev_t* dev, + uint32_t total_payload_length, + bool is_new_packet, + const char *data, uint32_t current_size); + +/** + * \brief Receive Ethernet packet from Rx FIFO to the passed buffer. + * Stops reading at packet border. + * If the passed buffer is larger than the current packet, + * the whole packet will be read into the buffer. + * If the current packet is larger than the passed buffer, + * the buffer will be filled with data and the next call + * will continue the read from that point. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * \param[in,out] data Pointer where the data will be read to. + * The caller is responsible to allocate it. + * \param[in] dlen Length of the allocated data in bytes. + * + * \return Remaining bytes left in the fifo of the current packet. + */ +uint32_t smsc9220_receive_by_chunks(const struct smsc9220_eth_dev_t* dev, + char *data, uint32_t dlen); + +/** + * \brief Get the used space of Rx fifo in bytes. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return Data received and waiting for read in bytes + */ +uint32_t smsc9220_get_rxfifo_data_used_space(const struct + smsc9220_eth_dev_t* dev); + +/** + * \brief Get the size of next unread packet in Rx buffer, using the peak + * register, which is not destructive so can be read asynchronously. + * Warning: In case of heavy receiving load, it's possible this register + * is not perfectly in sync. + * + * \param[in] dev Ethernet device structure \ref smsc9220_eth_dev_t + * + * \return Size in bytes of the next packet can be read from Rx fifo, according + * to the peek register. + */ +uint32_t smsc9220_peek_next_packet_size(const struct + smsc9220_eth_dev_t* dev); + +#ifdef __cplusplus +} +#endif + +#endif /* __SMSC9220_ETH_H__ */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c index 53524a35943..ccfab4b4ac8 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c @@ -270,3 +270,13 @@ static struct arm_uart_dev_data_t ARM_UART4_DEV_DATA = { struct arm_uart_dev_t ARM_UART4_DEV = {&(ARM_UART4_DEV_CFG), &(ARM_UART4_DEV_DATA)}; #endif /* ARM_UART4 */ + +/* SMSC9220 Ethernet driver structures */ +#ifdef SMSC9220_ETH +static const struct smsc9220_eth_dev_cfg_t SMSC9220_ETH_DEV_CFG = { + .base = SMSC9220_BASE}; +static struct smsc9220_eth_dev_data_t SMSC9220_ETH_DEV_DATA = { + .state = 0}; +struct smsc9220_eth_dev_t SMSC9220_ETH_DEV = {&(SMSC9220_ETH_DEV_CFG), + &(SMSC9220_ETH_DEV_DATA)}; +#endif \ No newline at end of file diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h index c33f07e25b0..14fdc45bc2d 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h @@ -26,6 +26,7 @@ #include "arm_mps2_io_drv.h" #include "spi_pl022_drv.h" #include "arm_uart_drv.h" +#include "smsc9220_eth_drv.h" /* ======= Defines peripheral configuration structures ======= */ @@ -96,4 +97,8 @@ extern struct arm_uart_dev_t ARM_UART3_DEV; extern struct arm_uart_dev_t ARM_UART4_DEV; #endif +#ifdef SMSC9220_ETH +extern struct smsc9220_eth_dev_t SMSC9220_ETH_DEV; +#endif + #endif /* __ARM_LTD_PLATFORM_DEVICES_H__ */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c deleted file mode 100644 index d9755dfb33f..00000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c +++ /dev/null @@ -1,85 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "mbed_wait_api.h" -#include "smsc9220_eth.h" - -/*---------------------------------------------------------------------------- - Ethernet Device initialize - *----------------------------------------------------------------------------*/ -int ethernet_init() -{ - return smsc9220_init(); -} - -/*---------------------------------------------------------------------------- - Ethernet Device Uninitialize - *----------------------------------------------------------------------------*/ -void ethernet_free() -{ - /* Uninitialize function is not implemented in Ethernet driver. */ -} - -int ethernet_write(const char *data, int size) -{ - /* smsc9220 cannot provide the functionality of writing into the tx buffer */ - /* by chunks, without knowing the full size of the packet in the beginning */ - return 0; -} - -int ethernet_send() -{ - /* smsc9220 cannot provide the functionality of writing into the tx buffer */ - /* by chunks, without knowing the full size of the packet in the beginning */ - return 0; -} - -int ethernet_receive() -{ - return smsc9220_peek_next_packet_size(); -} - -/* Read from an recevied ethernet packet.*/ -/* After receive returnd a number bigger than 0 it is*/ -/* possible to read bytes from this packet.*/ -/* Read will write up to size bytes into data.*/ -/* It is possible to use read multible times.*/ -/* Each time read will start reading after the last read byte before. */ -int ethernet_read(char *data, int dlen) -{ - return smsc9220_receive_by_chunks(data, dlen); -} - -void ethernet_address(char *mac) -{ - smsc9220_read_mac_address(mac); -} - -int ethernet_link(void) -{ - return 0; -} - -void ethernet_set_link(int speed, int duplex) -{ - smsc9220_establish_link(); -} diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/mbed_overrides.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/mbed_overrides.c index 1531692bce6..2fdfa0d75ee 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/mbed_overrides.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/mbed_overrides.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited + * Copyright (c) 2006-2018 Arm Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -15,10 +15,12 @@ * limitations under the License. */ -#include "smsc9220_eth.h" +#include "platform_devices.h" +#include "smsc9220_eth_drv.h" /* Provide ethernet devices with a semi-unique MAC address from the UUID */ void mbed_mac_address(char *mac) { - smsc9220_read_mac_address(mac); + smsc9220_read_mac_address(&SMSC9220_ETH_DEV, mac); } + diff --git a/targets/targets.json b/targets/targets.json index ce6dbed00b1..15e90c6cd6f 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -2880,13 +2880,17 @@ "inherits": ["ARM_IOTSS_Target"], "core": "Cortex-M3", "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "components": ["SMSC9220"], "extra_labels": ["ARM_SSG", "CM3DS_MPS2"], "OUTPUT_EXT": "elf", "macros": ["CMSDK_CM3DS"], - "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "TRNG", "FLASH"], + "device_has": ["ANALOGIN", "EMAC", "FLASH", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "TRNG"], "release_versions": ["2", "5"], "copy_method": "mps2", - "reset_method": "reboot.txt" + "reset_method": "reboot.txt", + "overrides": { + "target.network-default-interface-type": "ETHERNET" + } }, "ARM_BEETLE_SOC": { "inherits": ["ARM_IOTSS_Target"], From f366c257e5f8e0e9829d3e1a80861c447dc5bd35 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 30 Oct 2018 09:38:22 -0500 Subject: [PATCH 02/10] Export: Remove DS-5 ### Description The DS-5 exporter does not work. It exports projects which I'm 100% sure don't build. I have been looking over supporting it for about 6 months now and I have convinced myself that I don't think it's worth the trouble. Shout now if you need this exporter. ### Pull request type [ ] Fix [ ] Refactor [ ] Target update [x] Functionality change [ ] Docs update [ ] Test update [ ] Breaking change --- tools/export/__init__.py | 3 +- tools/export/ds5_5/__init__.py | 72 ------------ tools/export/ds5_5/arch_pro.cproject.tmpl | 115 -------------------- tools/export/ds5_5/arch_pro.launch.tmpl | 111 ------------------- tools/export/ds5_5/arch_pro.project.tmpl | 83 -------------- tools/export/ds5_5/gr_lychee.cproject.tmpl | 115 -------------------- tools/export/ds5_5/gr_lychee.launch.tmpl | 111 ------------------- tools/export/ds5_5/gr_lychee.project.tmpl | 83 -------------- tools/export/ds5_5/lpc11u24.cproject.tmpl | 103 ------------------ tools/export/ds5_5/lpc11u24.launch.tmpl | 111 ------------------- tools/export/ds5_5/lpc11u24.project.tmpl | 83 -------------- tools/export/ds5_5/lpc1768.cproject.tmpl | 115 -------------------- tools/export/ds5_5/lpc1768.launch.tmpl | 111 ------------------- tools/export/ds5_5/lpc1768.project.tmpl | 83 -------------- tools/export/ds5_5/lpc812.cproject.tmpl | 103 ------------------ tools/export/ds5_5/lpc812.launch.tmpl | 111 ------------------- tools/export/ds5_5/lpc812.project.tmpl | 83 -------------- tools/export/ds5_5/rz_a1h.cproject.tmpl | 115 -------------------- tools/export/ds5_5/rz_a1h.launch.tmpl | 111 ------------------- tools/export/ds5_5/rz_a1h.project.tmpl | 83 -------------- tools/export/ds5_5/ublox_c027.cproject.tmpl | 115 -------------------- tools/export/ds5_5/ublox_c027.launch.tmpl | 111 ------------------- tools/export/ds5_5/ublox_c027.project.tmpl | 83 -------------- tools/export/ds5_5/vk_rz_a1h.cproject.tmpl | 115 -------------------- tools/export/ds5_5/vk_rz_a1h.launch.tmpl | 111 ------------------- tools/export/ds5_5/vk_rz_a1h.project.tmpl | 83 -------------- 26 files changed, 1 insertion(+), 2522 deletions(-) delete mode 100644 tools/export/ds5_5/__init__.py delete mode 100644 tools/export/ds5_5/arch_pro.cproject.tmpl delete mode 100644 tools/export/ds5_5/arch_pro.launch.tmpl delete mode 100644 tools/export/ds5_5/arch_pro.project.tmpl delete mode 100644 tools/export/ds5_5/gr_lychee.cproject.tmpl delete mode 100644 tools/export/ds5_5/gr_lychee.launch.tmpl delete mode 100644 tools/export/ds5_5/gr_lychee.project.tmpl delete mode 100644 tools/export/ds5_5/lpc11u24.cproject.tmpl delete mode 100644 tools/export/ds5_5/lpc11u24.launch.tmpl delete mode 100644 tools/export/ds5_5/lpc11u24.project.tmpl delete mode 100644 tools/export/ds5_5/lpc1768.cproject.tmpl delete mode 100644 tools/export/ds5_5/lpc1768.launch.tmpl delete mode 100644 tools/export/ds5_5/lpc1768.project.tmpl delete mode 100644 tools/export/ds5_5/lpc812.cproject.tmpl delete mode 100644 tools/export/ds5_5/lpc812.launch.tmpl delete mode 100644 tools/export/ds5_5/lpc812.project.tmpl delete mode 100644 tools/export/ds5_5/rz_a1h.cproject.tmpl delete mode 100644 tools/export/ds5_5/rz_a1h.launch.tmpl delete mode 100644 tools/export/ds5_5/rz_a1h.project.tmpl delete mode 100644 tools/export/ds5_5/ublox_c027.cproject.tmpl delete mode 100644 tools/export/ds5_5/ublox_c027.launch.tmpl delete mode 100644 tools/export/ds5_5/ublox_c027.project.tmpl delete mode 100644 tools/export/ds5_5/vk_rz_a1h.cproject.tmpl delete mode 100644 tools/export/ds5_5/vk_rz_a1h.launch.tmpl delete mode 100644 tools/export/ds5_5/vk_rz_a1h.project.tmpl diff --git a/tools/export/__init__.py b/tools/export/__init__.py index 26654c16f43..70f0a33b8e9 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -29,7 +29,7 @@ from ..config import ALLOWED_FEATURES from ..build_api import prepare_toolchain from ..targets import TARGET_NAMES -from . import (lpcxpresso, ds5_5, iar, makefile, embitz, coide, kds, simplicity, +from . import (lpcxpresso, iar, makefile, embitz, coide, kds, simplicity, atmelstudio, mcuxpresso, sw4stm32, e2studio, zip, cmsis, uvision, cdt, vscode, gnuarmeclipse, qtcreator, cmake, nb, cces, codeblocks) @@ -40,7 +40,6 @@ u'make_armc5': makefile.Armc5, u'make_armc6': makefile.Armc6, u'make_iar': makefile.IAR, - u'ds5_5': ds5_5.DS5_5, u'iar': iar.IAR, u'embitz' : embitz.EmBitz, u'sw4stm32' : sw4stm32.Sw4STM32, diff --git a/tools/export/ds5_5/__init__.py b/tools/export/ds5_5/__init__.py deleted file mode 100644 index 9b2649269fb..00000000000 --- a/tools/export/ds5_5/__init__.py +++ /dev/null @@ -1,72 +0,0 @@ -""" -mbed SDK -Copyright (c) 2011-2016 ARM Limited - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -""" -from os.path import basename - -from tools.export.exporters import Exporter - - -class DS5_5(Exporter): - NAME = 'DS5' - - TARGETS = [ - 'LPC1768', - 'LPC11U24', - 'LPC812', - 'UBLOX_C027', - 'ARCH_PRO', - 'RZ_A1H', - 'VK_RZ_A1H', - 'GR_LYCHEE', - ] - - USING_MICROLIB = [ - 'LPC812', - ] - - FILE_TYPES = { - 'c_sources':'1', - 'cpp_sources':'8', - 's_sources':'2' - } - - TOOLCHAIN = "ARM" - - def get_toolchain(self): - return 'uARM' if (self.target in self.USING_MICROLIB) else 'ARM' - - def generate(self): - source_files = [] - for r_type, n in DS5_5.FILE_TYPES.items(): - for file in getattr(self.resources, r_type): - source_files.append({ - 'name': basename(file), 'type': n, 'path': file - }) - - ctx = { - 'name': self.project_name, - 'include_paths': self.resources.inc_dirs, - 'scatter_file': self.resources.linker_script, - 'object_files': self.resources.objects + self.libraries, - 'source_files': source_files, - 'symbols': self.toolchain.get_symbols() - } - target = self.target.lower() - - # Project file - self.gen_file('ds5_5/%s.project.tmpl' % target, ctx, '.project') - self.gen_file('ds5_5/%s.cproject.tmpl' % target, ctx, '.cproject') - self.gen_file('ds5_5/%s.launch.tmpl' % target, ctx, 'ds5_%s.launch' % target) diff --git a/tools/export/ds5_5/arch_pro.cproject.tmpl b/tools/export/ds5_5/arch_pro.cproject.tmpl deleted file mode 100644 index 5a5fff4d49c..00000000000 --- a/tools/export/ds5_5/arch_pro.cproject.tmpl +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/arch_pro.launch.tmpl b/tools/export/ds5_5/arch_pro.launch.tmpl deleted file mode 100644 index 74bc9649e79..00000000000 --- a/tools/export/ds5_5/arch_pro.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/arch_pro.project.tmpl b/tools/export/ds5_5/arch_pro.project.tmpl deleted file mode 100644 index 4f892f370b7..00000000000 --- a/tools/export/ds5_5/arch_pro.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_lpc1768 - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_lpc1768/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/gr_lychee.cproject.tmpl b/tools/export/ds5_5/gr_lychee.cproject.tmpl deleted file mode 100644 index bfd81f7f960..00000000000 --- a/tools/export/ds5_5/gr_lychee.cproject.tmpl +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/gr_lychee.launch.tmpl b/tools/export/ds5_5/gr_lychee.launch.tmpl deleted file mode 100644 index 3c5d272bdd2..00000000000 --- a/tools/export/ds5_5/gr_lychee.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/gr_lychee.project.tmpl b/tools/export/ds5_5/gr_lychee.project.tmpl deleted file mode 100644 index 613167cd00e..00000000000 --- a/tools/export/ds5_5/gr_lychee.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_gr_lychee - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_gr_lychee/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/lpc11u24.cproject.tmpl b/tools/export/ds5_5/lpc11u24.cproject.tmpl deleted file mode 100644 index 32adc51b8dd..00000000000 --- a/tools/export/ds5_5/lpc11u24.cproject.tmpl +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/lpc11u24.launch.tmpl b/tools/export/ds5_5/lpc11u24.launch.tmpl deleted file mode 100644 index 868cba3d2ca..00000000000 --- a/tools/export/ds5_5/lpc11u24.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/lpc11u24.project.tmpl b/tools/export/ds5_5/lpc11u24.project.tmpl deleted file mode 100644 index 8ad8f0a24df..00000000000 --- a/tools/export/ds5_5/lpc11u24.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_lpc11u24 - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_lpc11u24/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/lpc1768.cproject.tmpl b/tools/export/ds5_5/lpc1768.cproject.tmpl deleted file mode 100644 index 5a5fff4d49c..00000000000 --- a/tools/export/ds5_5/lpc1768.cproject.tmpl +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/lpc1768.launch.tmpl b/tools/export/ds5_5/lpc1768.launch.tmpl deleted file mode 100644 index 74bc9649e79..00000000000 --- a/tools/export/ds5_5/lpc1768.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/lpc1768.project.tmpl b/tools/export/ds5_5/lpc1768.project.tmpl deleted file mode 100644 index 4f892f370b7..00000000000 --- a/tools/export/ds5_5/lpc1768.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_lpc1768 - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_lpc1768/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/lpc812.cproject.tmpl b/tools/export/ds5_5/lpc812.cproject.tmpl deleted file mode 100644 index 96f0dc958e1..00000000000 --- a/tools/export/ds5_5/lpc812.cproject.tmpl +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/lpc812.launch.tmpl b/tools/export/ds5_5/lpc812.launch.tmpl deleted file mode 100644 index 57ab0bac89c..00000000000 --- a/tools/export/ds5_5/lpc812.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/lpc812.project.tmpl b/tools/export/ds5_5/lpc812.project.tmpl deleted file mode 100644 index 2e9c358ff93..00000000000 --- a/tools/export/ds5_5/lpc812.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_lpc812 - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_lpc812/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/rz_a1h.cproject.tmpl b/tools/export/ds5_5/rz_a1h.cproject.tmpl deleted file mode 100644 index 44e66cad211..00000000000 --- a/tools/export/ds5_5/rz_a1h.cproject.tmpl +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/rz_a1h.launch.tmpl b/tools/export/ds5_5/rz_a1h.launch.tmpl deleted file mode 100644 index a4bee75246c..00000000000 --- a/tools/export/ds5_5/rz_a1h.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/rz_a1h.project.tmpl b/tools/export/ds5_5/rz_a1h.project.tmpl deleted file mode 100644 index eee5209b751..00000000000 --- a/tools/export/ds5_5/rz_a1h.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_rz_a1h - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_rz_a1h/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/ublox_c027.cproject.tmpl b/tools/export/ds5_5/ublox_c027.cproject.tmpl deleted file mode 100644 index 5a5fff4d49c..00000000000 --- a/tools/export/ds5_5/ublox_c027.cproject.tmpl +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/ublox_c027.launch.tmpl b/tools/export/ds5_5/ublox_c027.launch.tmpl deleted file mode 100644 index 74bc9649e79..00000000000 --- a/tools/export/ds5_5/ublox_c027.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/ublox_c027.project.tmpl b/tools/export/ds5_5/ublox_c027.project.tmpl deleted file mode 100644 index 4f892f370b7..00000000000 --- a/tools/export/ds5_5/ublox_c027.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_lpc1768 - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_lpc1768/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/tools/export/ds5_5/vk_rz_a1h.cproject.tmpl b/tools/export/ds5_5/vk_rz_a1h.cproject.tmpl deleted file mode 100644 index 04a6254c2a0..00000000000 --- a/tools/export/ds5_5/vk_rz_a1h.cproject.tmpl +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/vk_rz_a1h.launch.tmpl b/tools/export/ds5_5/vk_rz_a1h.launch.tmpl deleted file mode 100644 index 4978e953f70..00000000000 --- a/tools/export/ds5_5/vk_rz_a1h.launch.tmpl +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tools/export/ds5_5/vk_rz_a1h.project.tmpl b/tools/export/ds5_5/vk_rz_a1h.project.tmpl deleted file mode 100644 index ad5694893b7..00000000000 --- a/tools/export/ds5_5/vk_rz_a1h.project.tmpl +++ /dev/null @@ -1,83 +0,0 @@ - - - {{name}}_ds5_vk_rz_a1h - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/ds5_vk_rz_a1h/Build} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - From a215d9d85666ccf970c5b9f986f5190f990c6e27 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Wed, 31 Oct 2018 16:01:16 +0200 Subject: [PATCH 03/10] Sync with Atmel RF driver v3.0.5 --- .../atmel-rf-driver/NanostackRfPhyAtmel.h | 4 +- .../source/NanostackRfPhyAtmel.cpp | 864 ++++++++---------- .../atmel-rf-driver/source/at24mac.cpp | 35 +- 3 files changed, 413 insertions(+), 490 deletions(-) diff --git a/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h b/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h index cf852952f40..0adcb7c3084 100644 --- a/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h +++ b/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h @@ -58,8 +58,8 @@ class RFBits; class NanostackRfPhyAtmel : public NanostackRfPhy { public: NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso, - PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq, - PinName i2c_sda, PinName i2c_scl); + PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq, + PinName i2c_sda, PinName i2c_scl); virtual ~NanostackRfPhyAtmel(); virtual int8_t rf_register(); virtual void rf_unregister(); diff --git a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp index 856230d1d8d..7fec78f6e73 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp +++ b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp @@ -50,25 +50,22 @@ #define RFF_TX 0x04 #define RFF_CCA 0x08 -typedef enum -{ +typedef enum { RF_MODE_NORMAL = 0, RF_MODE_SNIFFER = 1, RF_MODE_ED = 2 -}rf_mode_t; +} rf_mode_t; /*Atmel RF Part Type*/ -typedef enum -{ +typedef enum { ATMEL_UNKNOW_DEV = 0, ATMEL_AT86RF212, ATMEL_AT86RF231, // No longer supported (doesn't give ED+status on frame read) ATMEL_AT86RF233 -}rf_trx_part_e; +} rf_trx_part_e; /*Atmel RF states*/ -typedef enum -{ +typedef enum { NOP = 0x00, BUSY_RX = 0x01, BUSY_TX = 0x02, @@ -83,7 +80,7 @@ typedef enum RX_AACK_ON = 0x16, TX_ARET_ON = 0x19, STATE_TRANSITION_IN_PROGRESS = 0x1F -}rf_trx_states_t; +} rf_trx_states_t; static const uint8_t *rf_tx_data; // Points to Nanostack's buffer static uint8_t rf_tx_length; @@ -109,9 +106,9 @@ static const phy_rf_channel_configuration_s phy_24ghz = {2405000000U, 5000000U, static const phy_rf_channel_configuration_s phy_subghz = {868300000U, 2000000U, 250000U, 11U, M_OQPSK}; static const phy_device_channel_page_s phy_channel_pages[] = { - { CHANNEL_PAGE_0, &phy_24ghz}, - { CHANNEL_PAGE_2, &phy_subghz}, - { CHANNEL_PAGE_0, NULL} + { CHANNEL_PAGE_0, &phy_24ghz}, + { CHANNEL_PAGE_2, &phy_subghz}, + { CHANNEL_PAGE_0, NULL} }; /** @@ -156,7 +153,7 @@ static rf_trx_states_t rf_poll_trx_state_change(rf_trx_states_t trx_state); static void rf_init(void); static int8_t rf_device_register(const uint8_t *mac_addr); static void rf_device_unregister(void); -static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol ); +static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol); static void rf_cca_abort(void); static void rf_calibration_cb(void); static void rf_init_phy_mode(void); @@ -168,8 +165,8 @@ static void rf_cca_timer_start(uint32_t slots); static uint8_t rf_scale_lqi(int8_t rssi); static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel); -static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr); -static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr); +static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr); +static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr); static void rf_if_cca_timer_start(uint32_t slots); static void rf_if_enable_promiscuous_mode(void); @@ -214,7 +211,7 @@ static void rf_if_spi_exchange_n(const void *tx, size_t tx_len, void *rx, size_t static inline rf_trx_states_t rf_if_trx_status_from_full(uint8_t full_trx_status) { - return (rf_trx_states_t) (full_trx_status & 0x1F); + return (rf_trx_states_t)(full_trx_status & 0x1F); } #ifdef MBED_CONF_RTOS_PRESENT @@ -273,7 +270,7 @@ RFBits::RFBits(PinName spi_mosi, PinName spi_miso, SLP_TR(spi_slp), IRQ(spi_irq) #ifdef MBED_CONF_RTOS_PRESENT -,irq_thread(osPriorityRealtime, 1024) + , irq_thread(osPriorityRealtime, 1024) #endif { #ifdef MBED_CONF_RTOS_PRESENT @@ -313,7 +310,7 @@ static void rf_if_ack_timer_signal(void) } #endif - +// *INDENT-OFF* /* Delay functions for RF Chip SPI access */ #ifdef __CC_ARM __asm static void delay_loop(uint32_t count) @@ -359,27 +356,28 @@ static void delay_loop(uint32_t count) ); } #endif +// *INDENT-ON* static void delay_ns(uint32_t ns) { - uint32_t cycles_per_us = SystemCoreClock / 1000000; - // Cortex-M0 takes 4 cycles per loop (SUB=1, BCS=3) - // Cortex-M3 and M4 takes 3 cycles per loop (SUB=1, BCS=2) - // Cortex-M7 - who knows? - // Cortex M3-M7 have "CYCCNT" - would be better than a software loop, but M0 doesn't - // Assume 3 cycles per loop for now - will be 33% slow on M0. No biggie, - // as original version of code was 300% slow on M4. - // [Note that this very calculation, plus call overhead, will take multiple - // cycles. Could well be 100ns on its own... So round down here, startup is - // worth at least one loop iteration.] - uint32_t count = (cycles_per_us * ns) / 3000; + uint32_t cycles_per_us = SystemCoreClock / 1000000; + // Cortex-M0 takes 4 cycles per loop (SUB=1, BCS=3) + // Cortex-M3 and M4 takes 3 cycles per loop (SUB=1, BCS=2) + // Cortex-M7 - who knows? + // Cortex M3-M7 have "CYCCNT" - would be better than a software loop, but M0 doesn't + // Assume 3 cycles per loop for now - will be 33% slow on M0. No biggie, + // as original version of code was 300% slow on M4. + // [Note that this very calculation, plus call overhead, will take multiple + // cycles. Could well be 100ns on its own... So round down here, startup is + // worth at least one loop iteration.] + uint32_t count = (cycles_per_us * ns) / 3000; - delay_loop(count); + delay_loop(count); } // t1 = 180ns, SEL falling edge to MISO active [SPI setup assumed slow enough to not need manual delay] #define CS_SELECT() {rf->CS = 0; /* delay_ns(180); */} - // t9 = 250ns, last clock to SEL rising edge, t8 = 250ns, SPI idle time between consecutive access +// t9 = 250ns, last clock to SEL rising edge, t8 = 250ns, SPI idle time between consecutive access #define CS_RELEASE() {delay_ns(250); rf->CS = 1; delay_ns(250);} /* @@ -391,21 +389,20 @@ static void delay_ns(uint32_t ns) */ static rf_trx_part_e rf_radio_type_read(void) { - rf_trx_part_e ret_val = ATMEL_UNKNOW_DEV; + rf_trx_part_e ret_val = ATMEL_UNKNOW_DEV; - switch (rf_part_num) - { - case PART_AT86RF212: - ret_val = ATMEL_AT86RF212; - break; - case PART_AT86RF233: - ret_val = ATMEL_AT86RF233; - break; - default: - break; - } + switch (rf_part_num) { + case PART_AT86RF212: + ret_val = ATMEL_AT86RF212; + break; + case PART_AT86RF233: + ret_val = ATMEL_AT86RF233; + break; + default: + break; + } - return ret_val; + return ret_val; } @@ -419,9 +416,9 @@ static rf_trx_part_e rf_radio_type_read(void) static void rf_if_ack_wait_timer_start(uint16_t slots) { #ifdef MBED_CONF_RTOS_PRESENT - rf->ack_timer.attach_us(rf_if_ack_timer_signal, slots*50); + rf->ack_timer.attach_us(rf_if_ack_timer_signal, slots * 50); #else - rf->ack_timer.attach_us(rf_ack_wait_timer_interrupt, slots*50); + rf->ack_timer.attach_us(rf_ack_wait_timer_interrupt, slots * 50); #endif } @@ -435,9 +432,9 @@ static void rf_if_ack_wait_timer_start(uint16_t slots) static void rf_if_calibration_timer_start(uint32_t slots) { #ifdef MBED_CONF_RTOS_PRESENT - rf->cal_timer.attach_us(rf_if_cal_timer_signal, slots*50); + rf->cal_timer.attach_us(rf_if_cal_timer_signal, slots * 50); #else - rf->cal_timer.attach_us(rf_calibration_timer_interrupt, slots*50); + rf->cal_timer.attach_us(rf_calibration_timer_interrupt, slots * 50); #endif } @@ -451,9 +448,9 @@ static void rf_if_calibration_timer_start(uint32_t slots) static void rf_if_cca_timer_start(uint32_t slots) { #ifdef MBED_CONF_RTOS_PRESENT - rf->cca_timer.attach_us(rf_if_cca_timer_signal, slots*50); + rf->cca_timer.attach_us(rf_if_cca_timer_signal, slots * 50); #else - rf->cca_timer.attach_us(rf_cca_timer_interrupt, slots*50); + rf->cca_timer.attach_us(rf_cca_timer_interrupt, slots * 50); #endif } @@ -464,7 +461,7 @@ static void rf_if_cca_timer_start(uint32_t slots) */ static void rf_if_cca_timer_stop(void) { - rf->cca_timer.detach(); + rf->cca_timer.detach(); } /* @@ -476,7 +473,7 @@ static void rf_if_cca_timer_stop(void) */ static void rf_if_ack_wait_timer_stop(void) { - rf->ack_timer.detach(); + rf->ack_timer.detach(); } /* @@ -490,10 +487,10 @@ static void rf_if_ack_wait_timer_stop(void) */ static void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask) { - uint8_t reg = rf_if_read_register(addr); - reg &= ~bit_mask; - reg |= bit; - rf_if_write_register(addr, reg); + uint8_t reg = rf_if_read_register(addr); + reg &= ~bit_mask; + reg |= bit; + rf_if_write_register(addr, reg); } /* @@ -506,7 +503,7 @@ static void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask) */ static void rf_if_clear_bit(uint8_t addr, uint8_t bit) { - rf_if_set_bit(addr, 0, bit); + rf_if_set_bit(addr, 0, bit); } /* @@ -519,11 +516,11 @@ static void rf_if_clear_bit(uint8_t addr, uint8_t bit) */ static void rf_if_write_register(uint8_t addr, uint8_t data) { - const uint8_t tx[2] = { static_cast(0xC0 | addr), data }; - uint8_t rx[2]; - CS_SELECT(); - rf_if_spi_exchange_n(tx, 2, rx, 2); - CS_RELEASE(); + const uint8_t tx[2] = { static_cast(0xC0 | addr), data }; + uint8_t rx[2]; + CS_SELECT(); + rf_if_spi_exchange_n(tx, 2, rx, 2); + CS_RELEASE(); } /* @@ -536,15 +533,15 @@ static void rf_if_write_register(uint8_t addr, uint8_t data) */ static uint8_t rf_if_read_register_with_status(uint8_t addr, uint8_t *status_out) { - const uint8_t tx[1] = { static_cast(0x80 | addr) }; - uint8_t rx[2]; - CS_SELECT(); - rf_if_spi_exchange_n(tx, 1, rx, 2); - CS_RELEASE(); - if (status_out) { - *status_out = rx[0]; - } - return rx[1]; + const uint8_t tx[1] = { static_cast(0x80 | addr) }; + uint8_t rx[2]; + CS_SELECT(); + rf_if_spi_exchange_n(tx, 1, rx, 2); + CS_RELEASE(); + if (status_out) { + *status_out = rx[0]; + } + return rx[1]; } /* @@ -556,7 +553,7 @@ static uint8_t rf_if_read_register_with_status(uint8_t addr, uint8_t *status_out */ static uint8_t rf_if_read_register(uint8_t addr) { - return rf_if_read_register_with_status(addr, NULL); + return rf_if_read_register_with_status(addr, NULL); } /* @@ -569,29 +566,29 @@ static uint8_t rf_if_read_register(uint8_t addr) static void rf_if_reset_radio(void) { #if MBED_CONF_ATMEL_RF_USE_SPI_SPACING_API - rf->spi.frequency(MBED_CONF_ATMEL_RF_FULL_SPI_SPEED); - int spacing = rf->spi.write_spacing(MBED_CONF_ATMEL_RF_FULL_SPI_SPEED_BYTE_SPACING); - if (spacing < MBED_CONF_ATMEL_RF_FULL_SPI_SPEED_BYTE_SPACING) { - rf->spi.frequency(MBED_CONF_ATMEL_RF_LOW_SPI_SPEED); - rf->spi.write_spacing(0); - } + rf->spi.frequency(MBED_CONF_ATMEL_RF_FULL_SPI_SPEED); + int spacing = rf->spi.write_spacing(MBED_CONF_ATMEL_RF_FULL_SPI_SPEED_BYTE_SPACING); + if (spacing < MBED_CONF_ATMEL_RF_FULL_SPI_SPEED_BYTE_SPACING) { + rf->spi.frequency(MBED_CONF_ATMEL_RF_LOW_SPI_SPEED); + rf->spi.write_spacing(0); + } #elif MBED_CONF_ATMEL_RF_ASSUME_SPACED_SPI - rf->spi.frequency(MBED_CONF_ATMEL_RF_FULL_SPI_SPEED); + rf->spi.frequency(MBED_CONF_ATMEL_RF_FULL_SPI_SPEED); #else - rf->spi.frequency(MBED_CONF_ATMEL_RF_LOW_SPI_SPEED); + rf->spi.frequency(MBED_CONF_ATMEL_RF_LOW_SPI_SPEED); #endif - rf->IRQ.rise(0); - rf->RST = 1; - wait_ms(1); - rf->RST = 0; - wait_ms(10); - CS_RELEASE(); - rf->SLP_TR = 0; - wait_ms(10); - rf->RST = 1; - wait_ms(10); + rf->IRQ.rise(0); + rf->RST = 1; + wait_ms(1); + rf->RST = 0; + wait_ms(10); + CS_RELEASE(); + rf->SLP_TR = 0; + wait_ms(10); + rf->RST = 1; + wait_ms(10); - rf->IRQ.rise(&rf_if_interrupt_handler); + rf->IRQ.rise(&rf_if_interrupt_handler); } /* @@ -603,10 +600,10 @@ static void rf_if_reset_radio(void) */ static void rf_if_enable_promiscuous_mode(void) { - if (!(xah_ctrl_1 & AACK_PROM_MODE)) { - /*Set AACK_PROM_MODE to enable the promiscuous mode*/ - rf_if_write_register(XAH_CTRL_1, xah_ctrl_1 |= AACK_PROM_MODE); - } + if (!(xah_ctrl_1 & AACK_PROM_MODE)) { + /*Set AACK_PROM_MODE to enable the promiscuous mode*/ + rf_if_write_register(XAH_CTRL_1, xah_ctrl_1 |= AACK_PROM_MODE); + } } /* @@ -618,10 +615,10 @@ static void rf_if_enable_promiscuous_mode(void) */ static void rf_if_disable_promiscuous_mode(void) { - if (xah_ctrl_1 & AACK_PROM_MODE) { - /*Clear AACK_PROM_MODE to disable the promiscuous mode*/ - rf_if_write_register(XAH_CTRL_1, xah_ctrl_1 &= ~AACK_PROM_MODE); - } + if (xah_ctrl_1 & AACK_PROM_MODE) { + /*Clear AACK_PROM_MODE to disable the promiscuous mode*/ + rf_if_write_register(XAH_CTRL_1, xah_ctrl_1 &= ~AACK_PROM_MODE); + } } /* @@ -633,8 +630,8 @@ static void rf_if_disable_promiscuous_mode(void) */ static void rf_if_enable_ant_div(void) { - /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/ - rf_if_set_bit(ANT_DIV, ANT_EXT_SW_EN, ANT_EXT_SW_EN); + /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/ + rf_if_set_bit(ANT_DIV, ANT_EXT_SW_EN, ANT_EXT_SW_EN); } /* @@ -646,7 +643,7 @@ static void rf_if_enable_ant_div(void) */ static void rf_if_disable_ant_div(void) { - rf_if_clear_bit(ANT_DIV, ANT_EXT_SW_EN); + rf_if_clear_bit(ANT_DIV, ANT_EXT_SW_EN); } /* @@ -658,7 +655,7 @@ static void rf_if_disable_ant_div(void) */ static void rf_if_enable_slptr(void) { - rf->SLP_TR = 1; + rf->SLP_TR = 1; } /* @@ -670,7 +667,7 @@ static void rf_if_enable_slptr(void) */ static void rf_if_disable_slptr(void) { - rf->SLP_TR = 0; + rf->SLP_TR = 0; } /* @@ -682,9 +679,9 @@ static void rf_if_disable_slptr(void) */ static void rf_if_write_antenna_diversity_settings(void) { - /*Recommended setting of PDT_THRES is 3 when antenna diversity is used*/ - rf_if_set_bit(RX_CTRL, 0x03, 0x0f); - rf_if_write_register(ANT_DIV, ANT_DIV_EN | ANT_EXT_SW_EN | ANT_CTRL_DEFAULT); + /*Recommended setting of PDT_THRES is 3 when antenna diversity is used*/ + rf_if_set_bit(RX_CTRL, 0x03, 0x0f); + rf_if_write_register(ANT_DIV, ANT_DIV_EN | ANT_EXT_SW_EN | ANT_CTRL_DEFAULT); } /* @@ -696,7 +693,7 @@ static void rf_if_write_antenna_diversity_settings(void) */ static void rf_if_write_set_tx_power_register(uint8_t value) { - rf_if_write_register(PHY_TX_PWR, value); + rf_if_write_register(PHY_TX_PWR, value); } /* @@ -708,7 +705,7 @@ static void rf_if_write_set_tx_power_register(uint8_t value) */ static uint8_t rf_if_read_part_num(void) { - return rf_if_read_register(PART_NUM); + return rf_if_read_register(PART_NUM); } /* @@ -720,58 +717,53 @@ static uint8_t rf_if_read_part_num(void) */ static void rf_if_write_rf_settings(void) { - /*Reset RF module*/ - rf_if_reset_radio(); + /*Reset RF module*/ + rf_if_reset_radio(); - rf_part_num = rf_if_read_part_num(); + rf_part_num = rf_if_read_part_num(); - rf_if_write_register(XAH_CTRL_0,0); + rf_if_write_register(XAH_CTRL_0, 0); - /* Auto CRC on, IRQ status shows unmasked only, TRX_STATUS output on all accesses */ - rf_if_write_register(TRX_CTRL_1, TX_AUTO_CRC_ON | SPI_CMD_MODE_TRX_STATUS); + /* Auto CRC on, IRQ status shows unmasked only, TRX_STATUS output on all accesses */ + rf_if_write_register(TRX_CTRL_1, TX_AUTO_CRC_ON | SPI_CMD_MODE_TRX_STATUS); - rf_if_write_register(IRQ_MASK, CCA_ED_DONE | TRX_END | TRX_UR); + rf_if_write_register(IRQ_MASK, CCA_ED_DONE | TRX_END | TRX_UR); - xah_ctrl_1 = rf_if_read_register(XAH_CTRL_1); + xah_ctrl_1 = rf_if_read_register(XAH_CTRL_1); - /*Read transceiver PART_NUM*/ - rf_part_num = rf_if_read_register(PART_NUM); + /*Read transceiver PART_NUM*/ + rf_part_num = rf_if_read_register(PART_NUM); - /*Sub-GHz RF settings*/ - if(rf_part_num == PART_AT86RF212) - { - /*GC_TX_OFFS mode-dependent setting - OQPSK*/ - rf_if_write_register(RF_CTRL_0, 0x32); + /*Sub-GHz RF settings*/ + if (rf_part_num == PART_AT86RF212) { + /*GC_TX_OFFS mode-dependent setting - OQPSK*/ + rf_if_write_register(RF_CTRL_0, 0x32); - if(rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B) - { - /*TX Output Power setting - 0 dBm North American Band*/ - rf_if_write_register(PHY_TX_PWR, 0x03); - } - else - { - /*TX Output Power setting - 0 dBm North American Band*/ - rf_if_write_register(PHY_TX_PWR, 0x24); - } + if (rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B) { + /*TX Output Power setting - 0 dBm North American Band*/ + rf_if_write_register(PHY_TX_PWR, 0x03); + } else { + /*TX Output Power setting - 0 dBm North American Band*/ + rf_if_write_register(PHY_TX_PWR, 0x24); + } - /*PHY Mode: IEEE 802.15.4-2006/2011 - OQPSK-SIN-250*/ - rf_if_write_register(TRX_CTRL_2, RX_SAFE_MODE | RF_PHY_MODE); - /*Based on receiver Characteristics. See AT86RF212B Datasheet where RSSI BASE VALUE in range -97 - -100 dBm*/ - rf_rssi_base_val = -98; - } - /*2.4GHz RF settings*/ - else - { + /*PHY Mode: IEEE 802.15.4-2006/2011 - OQPSK-SIN-250*/ + rf_if_write_register(TRX_CTRL_2, RX_SAFE_MODE | RF_PHY_MODE); + /*Based on receiver Characteristics. See AT86RF212B Datasheet where RSSI BASE VALUE in range -97 - -100 dBm*/ + rf_rssi_base_val = -98; + } + /*2.4GHz RF settings*/ + else { #if 0 - /* Disable power saving functions for now - can only impact reliability, - * and don't have any users demanding it. */ - /*Set RPC register*/ - rf_if_write_register(TRX_RPC, RX_RPC_CTRL|RX_RPC_EN|PLL_RPC_EN|XAH_TX_RPC_EN|IPAN_RPC_EN|TRX_RPC_RSVD_1); + /* Disable power saving functions for now - can only impact reliability, + * and don't have any users demanding it. */ + /*Set RPC register*/ + rf_if_write_register(TRX_RPC, RX_RPC_CTRL | RX_RPC_EN | PLL_RPC_EN | XAH_TX_RPC_EN | IPAN_RPC_EN | TRX_RPC_RSVD_1); #endif - /*PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s*/ - rf_if_write_register(TRX_CTRL_2, RX_SAFE_MODE); - rf_rssi_base_val = -91; - } + /*PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s*/ + rf_if_write_register(TRX_CTRL_2, RX_SAFE_MODE); + rf_rssi_base_val = -91; + } } /* @@ -783,7 +775,7 @@ static void rf_if_write_rf_settings(void) */ static rf_trx_states_t rf_if_read_trx_state(void) { - return rf_if_trx_status_from_full(rf_if_read_register(TRX_STATUS)); + return rf_if_trx_status_from_full(rf_if_read_register(TRX_STATUS)); } /* @@ -798,19 +790,19 @@ static rf_trx_states_t rf_if_read_trx_state(void) */ static uint16_t rf_if_read_packet(uint8_t data_out[RF_MTU], uint8_t *lqi_out, uint8_t *ed_out, bool *crc_good) { - CS_SELECT(); - const uint8_t tx[1] = { 0x20 }; - uint8_t rx[3]; - rf_if_spi_exchange_n(tx, 1, rx, 2); - uint8_t len = rx[1] & 0x7F; - rf_if_spi_exchange_n(NULL, 0, data_out, len); - rf_if_spi_exchange_n(NULL, 0, rx, 3); - *lqi_out = rx[0]; - *ed_out = rx[1]; - *crc_good = rx[2] & 0x80; - CS_RELEASE(); + CS_SELECT(); + const uint8_t tx[1] = { 0x20 }; + uint8_t rx[3]; + rf_if_spi_exchange_n(tx, 1, rx, 2); + uint8_t len = rx[1] & 0x7F; + rf_if_spi_exchange_n(NULL, 0, data_out, len); + rf_if_spi_exchange_n(NULL, 0, rx, 3); + *lqi_out = rx[0]; + *ed_out = rx[1]; + *crc_good = rx[2] & 0x80; + CS_RELEASE(); - return len; + return len; } /* @@ -822,8 +814,8 @@ static uint16_t rf_if_read_packet(uint8_t data_out[RF_MTU], uint8_t *lqi_out, ui */ static void rf_if_write_short_addr_registers(uint8_t *short_address) { - rf_if_write_register(SHORT_ADDR_1, *short_address++); - rf_if_write_register(SHORT_ADDR_0, *short_address); + rf_if_write_register(SHORT_ADDR_1, *short_address++); + rf_if_write_register(SHORT_ADDR_0, *short_address); } /* @@ -835,16 +827,13 @@ static void rf_if_write_short_addr_registers(uint8_t *short_address) */ static void rf_if_ack_pending_ctrl(uint8_t state) { - rf_if_lock(); - if(state) - { - rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD)); - } - else - { - rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD)); - } - rf_if_unlock(); + rf_if_lock(); + if (state) { + rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD)); + } else { + rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD)); + } + rf_if_unlock(); } /* @@ -856,16 +845,17 @@ static void rf_if_ack_pending_ctrl(uint8_t state) */ static uint8_t rf_if_last_acked_pending(void) { - uint8_t last_acked_data_pending; + uint8_t last_acked_data_pending; - rf_if_lock(); - if(rf_if_read_register(CSMA_SEED_1) & (1 << AACK_SET_PD)) - last_acked_data_pending = 1; - else - last_acked_data_pending = 0; - rf_if_unlock(); + rf_if_lock(); + if (rf_if_read_register(CSMA_SEED_1) & (1 << AACK_SET_PD)) { + last_acked_data_pending = 1; + } else { + last_acked_data_pending = 0; + } + rf_if_unlock(); - return last_acked_data_pending; + return last_acked_data_pending; } /* @@ -877,9 +867,9 @@ static uint8_t rf_if_last_acked_pending(void) */ static void rf_if_calibration(void) { - rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START); - /*Wait while calibration is running*/ - while(rf_if_read_register(FTN_CTRL) & FTN_START); + rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START); + /*Wait while calibration is running*/ + while (rf_if_read_register(FTN_CTRL) & FTN_START); } /* @@ -891,8 +881,8 @@ static void rf_if_calibration(void) */ static void rf_if_write_pan_id_registers(uint8_t *pan_id) { - rf_if_write_register(PAN_ID_1, *pan_id++); - rf_if_write_register(PAN_ID_0, *pan_id); + rf_if_write_register(PAN_ID_1, *pan_id++); + rf_if_write_register(PAN_ID_0, *pan_id); } /* @@ -904,11 +894,12 @@ static void rf_if_write_pan_id_registers(uint8_t *pan_id) */ static void rf_if_write_ieee_addr_registers(uint8_t *address) { - uint8_t i; - uint8_t temp = IEEE_ADDR_0; + uint8_t i; + uint8_t temp = IEEE_ADDR_0; - for(i=0; i<8; i++) - rf_if_write_register(temp++, address[7-i]); + for (i = 0; i < 8; i++) { + rf_if_write_register(temp++, address[7 - i]); + } } /* @@ -921,12 +912,12 @@ static void rf_if_write_ieee_addr_registers(uint8_t *address) */ static void rf_if_write_frame_buffer(const uint8_t *ptr, uint8_t length) { - const uint8_t cmd[2] = { 0x60, static_cast(length + 2) }; + const uint8_t cmd[2] = { 0x60, static_cast(length + 2) }; - CS_SELECT(); - rf_if_spi_exchange_n(cmd, 2, NULL, 0); - rf_if_spi_exchange_n(ptr, length, NULL, 0); - CS_RELEASE(); + CS_SELECT(); + rf_if_spi_exchange_n(cmd, 2, NULL, 0); + rf_if_spi_exchange_n(ptr, length, NULL, 0); + CS_RELEASE(); } /* @@ -938,27 +929,27 @@ static void rf_if_write_frame_buffer(const uint8_t *ptr, uint8_t length) */ static uint8_t rf_if_read_rnd(void) { - uint8_t temp; - uint8_t tmp_rpc_val = 0; - /*RPC must be disabled while reading the random number*/ - if(rf_part_num == PART_AT86RF233) - { - tmp_rpc_val = rf_if_read_register(TRX_RPC); - rf_if_write_register(TRX_RPC, RX_RPC_CTRL|TRX_RPC_RSVD_1); - } - - wait_ms(1); - temp = ((rf_if_read_register(PHY_RSSI)>>5) << 6); - wait_ms(1); - temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 4); - wait_ms(1); - temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 2); - wait_ms(1); - temp |= ((rf_if_read_register(PHY_RSSI)>>5)); - wait_ms(1); - if(rf_part_num == PART_AT86RF233) - rf_if_write_register(TRX_RPC, tmp_rpc_val); - return temp; + uint8_t temp; + uint8_t tmp_rpc_val = 0; + /*RPC must be disabled while reading the random number*/ + if (rf_part_num == PART_AT86RF233) { + tmp_rpc_val = rf_if_read_register(TRX_RPC); + rf_if_write_register(TRX_RPC, RX_RPC_CTRL | TRX_RPC_RSVD_1); + } + + wait_ms(1); + temp = ((rf_if_read_register(PHY_RSSI) >> 5) << 6); + wait_ms(1); + temp |= ((rf_if_read_register(PHY_RSSI) >> 5) << 4); + wait_ms(1); + temp |= ((rf_if_read_register(PHY_RSSI) >> 5) << 2); + wait_ms(1); + temp |= ((rf_if_read_register(PHY_RSSI) >> 5)); + wait_ms(1); + if (rf_part_num == PART_AT86RF233) { + rf_if_write_register(TRX_RPC, tmp_rpc_val); + } + return temp; } /* @@ -970,9 +961,9 @@ static uint8_t rf_if_read_rnd(void) */ static rf_trx_states_t rf_if_change_trx_state(rf_trx_states_t trx_state) { - rf_if_write_register(TRX_STATE, trx_state); - /*Wait while not in desired state*/ - return rf_poll_trx_state_change(trx_state); + rf_if_write_register(TRX_STATE, trx_state); + /*Wait while not in desired state*/ + return rf_poll_trx_state_change(trx_state); } /* @@ -984,7 +975,7 @@ static rf_trx_states_t rf_if_change_trx_state(rf_trx_states_t trx_state) */ static void rf_if_start_cca_process(void) { - rf_if_write_register(PHY_CC_CCA, CCA_REQUEST | CCA_MODE_3A | rf_phy_channel); + rf_if_write_register(PHY_CC_CCA, CCA_REQUEST | CCA_MODE_3A | rf_phy_channel); } /* @@ -996,11 +987,11 @@ static void rf_if_start_cca_process(void) */ static int8_t rf_if_scale_rssi(uint8_t ed_level) { - if (rf_part_num == PART_AT86RF212) { - /* Data sheet says to multiply by 1.03 - this is 1.03125, rounding down */ - ed_level += ed_level >> 5; - } - return rf_rssi_base_val + ed_level; + if (rf_part_num == PART_AT86RF212) { + /* Data sheet says to multiply by 1.03 - this is 1.03125, rounding down */ + ed_level += ed_level >> 5; + } + return rf_rssi_base_val + ed_level; } /* @@ -1012,7 +1003,7 @@ static int8_t rf_if_scale_rssi(uint8_t ed_level) */ static void rf_if_set_channel_register(uint8_t channel) { - rf_if_set_bit(PHY_CC_CCA, channel, CCA_CHANNEL_MASK); + rf_if_set_bit(PHY_CC_CCA, channel, CCA_CHANNEL_MASK); } /* @@ -1024,7 +1015,7 @@ static void rf_if_set_channel_register(uint8_t channel) */ static void rf_if_enable_irq(void) { - rf->IRQ.enable_irq(); + rf->IRQ.enable_irq(); } /* @@ -1036,7 +1027,7 @@ static void rf_if_enable_irq(void) */ static void rf_if_disable_irq(void) { - rf->IRQ.disable_irq(); + rf->IRQ.disable_irq(); } #ifdef MBED_CONF_RTOS_PRESENT @@ -1080,39 +1071,35 @@ static void rf_if_irq_task_process_irq(void) static void rf_if_interrupt_handler(void) #endif { - static uint8_t last_is, last_ts; - uint8_t irq_status, full_trx_status; - uint8_t orig_xah_ctrl_1 = xah_ctrl_1; + static uint8_t last_is, last_ts; + uint8_t irq_status, full_trx_status; + uint8_t orig_xah_ctrl_1 = xah_ctrl_1; - /*Read and clear interrupt flag, and pick up trx_status*/ - irq_status = rf_if_read_register_with_status(IRQ_STATUS, &full_trx_status); - uint8_t orig_flags = rf_flags; + /*Read and clear interrupt flag, and pick up trx_status*/ + irq_status = rf_if_read_register_with_status(IRQ_STATUS, &full_trx_status); + uint8_t orig_flags = rf_flags; - /*Frame end interrupt (RX and TX)*/ - if(irq_status & TRX_END) - { - /*TX done interrupt*/ - rf_trx_states_t trx_status = rf_if_trx_status_from_full(full_trx_status); - if(trx_status == PLL_ON || trx_status == TX_ARET_ON) - { - rf_handle_tx_end(trx_status); + /*Frame end interrupt (RX and TX)*/ + if (irq_status & TRX_END) { + /*TX done interrupt*/ + rf_trx_states_t trx_status = rf_if_trx_status_from_full(full_trx_status); + if (trx_status == PLL_ON || trx_status == TX_ARET_ON) { + rf_handle_tx_end(trx_status); + } + /*Frame received interrupt*/ + else { + rf_handle_rx_end(trx_status); + } } - /*Frame received interrupt*/ - else - { - rf_handle_rx_end(trx_status); + if (irq_status & CCA_ED_DONE) { + rf_handle_cca_ed_done(full_trx_status); } - } - if(irq_status & CCA_ED_DONE) - { - rf_handle_cca_ed_done(full_trx_status); - } - if (irq_status & TRX_UR) - { - tr_error("Radio underrun is %x->%x ts %x->%x fl %x->%x x1 %x", last_is, irq_status, last_ts, full_trx_status, orig_flags, rf_flags, orig_xah_ctrl_1); - } - last_is = irq_status; - last_ts = full_trx_status; + if (irq_status & TRX_UR) { + // Here some counter could be used to monitor the underrun occurancy count. + // Do not print anything here! + } + last_is = irq_status; + last_ts = full_trx_status; } /* @@ -1121,25 +1108,25 @@ static void rf_if_interrupt_handler(void) static void rf_if_spi_exchange_n(const void *tx, size_t tx_len, void *rx, size_t rx_len) { #if 1 - rf->spi.write(static_cast(tx), tx_len, - static_cast(rx), rx_len); + rf->spi.write(static_cast(tx), tx_len, + static_cast(rx), rx_len); #else - const uint8_t *txb = static_cast(tx); - uint8_t *rxb = static_cast(rx); - while (tx_len > 0 || rx_len > 0) { - uint8_t b; - if (tx_len) { - tx_len--; - b = *txb++; - } else { - b = 0xFF; - } - b = rf->spi.write(b); - if (rx_len) { - rx_len--; - *rxb++ = b; - } - } + const uint8_t *txb = static_cast(tx); + uint8_t *rxb = static_cast(rx); + while (tx_len > 0 || rx_len > 0) { + uint8_t b; + if (tx_len) { + tx_len--; + b = *txb++; + } else { + b = 0xFF; + } + b = rf->spi.write(b); + if (rx_len) { + rx_len--; + *rxb++ = b; + } + } #endif } @@ -1205,18 +1192,14 @@ static int8_t rf_device_register(const uint8_t *mac_addr) rf_init(); radio_type = rf_radio_type_read(); - if(radio_type != ATMEL_UNKNOW_DEV) - { + if (radio_type != ATMEL_UNKNOW_DEV) { /*Set pointer to MAC address*/ device_driver.PHY_MAC = (uint8_t *)mac_addr; - device_driver.driver_description = (char*)"ATMEL_MAC"; + device_driver.driver_description = (char *)"ATMEL_MAC"; //Create setup Used Radio chips - if(radio_type == ATMEL_AT86RF212) - { + if (radio_type == ATMEL_AT86RF212) { device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE; - } - else - { + } else { device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE; } device_driver.phy_channel_pages = phy_channel_pages; @@ -1364,8 +1347,9 @@ static void rf_write_settings(void) /*Set output power*/ rf_if_write_set_tx_power_register(radio_tx_power); /*Initialise Antenna Diversity*/ - if(rf_use_antenna_diversity) + if (rf_use_antenna_diversity) { rf_if_write_antenna_diversity_settings(); + } rf_if_unlock(); } @@ -1376,20 +1360,18 @@ static void rf_write_settings(void) * * \return none */ -static void rf_set_short_adr(uint8_t * short_address) +static void rf_set_short_adr(uint8_t *short_address) { rf_if_lock(); /*Wake up RF if sleeping*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_disable_slptr(); rf_poll_trx_state_change(TRX_OFF); } /*Write address filter registers*/ rf_if_write_short_addr_registers(short_address); /*RF back to sleep*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_enable_slptr(); } rf_if_unlock(); @@ -1406,16 +1388,14 @@ static void rf_set_pan_id(uint8_t *pan_id) { rf_if_lock(); /*Wake up RF if sleeping*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_disable_slptr(); rf_poll_trx_state_change(TRX_OFF); } /*Write address filter registers*/ rf_if_write_pan_id_registers(pan_id); /*RF back to sleep*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_enable_slptr(); } rf_if_unlock(); @@ -1432,16 +1412,14 @@ static void rf_set_address(uint8_t *address) { rf_if_lock(); /*Wake up RF if sleeping*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_disable_slptr(); rf_poll_trx_state_change(TRX_OFF); } /*Write address filter registers*/ rf_if_write_ieee_addr_registers(address); /*RF back to sleep*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_enable_slptr(); } rf_if_unlock(); @@ -1458,8 +1436,9 @@ static void rf_channel_set(uint8_t ch) { rf_if_lock(); rf_phy_channel = ch; - if(ch < 0x1f) + if (ch < 0x1f) { rf_if_set_channel_register(ch); + } rf_if_unlock(); } @@ -1504,29 +1483,28 @@ static void rf_init(void) */ static void rf_off(void) { - if(rf_flags_check(RFF_ON)) - { + if (rf_flags_check(RFF_ON)) { rf_if_lock(); rf_cca_abort(); uint16_t while_counter = 0; /*Wait while receiving*/ - while(rf_if_read_trx_state() == BUSY_RX_AACK) - { + while (rf_if_read_trx_state() == BUSY_RX_AACK) { while_counter++; - if(while_counter == 0xffff) + if (while_counter == 0xffff) { break; + } } /*RF state change: RX_AACK_ON->PLL_ON->TRX_OFF->SLEEP*/ - if(rf_if_read_trx_state() == RX_AACK_ON) - { + if (rf_if_read_trx_state() == RX_AACK_ON) { rf_if_change_trx_state(PLL_ON); } rf_if_change_trx_state(TRX_OFF); rf_if_enable_slptr(); /*Disable Antenna Diversity*/ - if(rf_use_antenna_diversity) + if (rf_use_antenna_diversity) { rf_if_disable_ant_div(); + } rf_if_unlock(); } @@ -1545,17 +1523,18 @@ static rf_trx_states_t rf_poll_trx_state_change(rf_trx_states_t trx_state) { uint16_t while_counter = 0; - if(trx_state == FORCE_PLL_ON) + if (trx_state == FORCE_PLL_ON) { trx_state = PLL_ON; - else if(trx_state == FORCE_TRX_OFF) + } else if (trx_state == FORCE_TRX_OFF) { trx_state = TRX_OFF; + } rf_trx_states_t state_out; - while((state_out = rf_if_read_trx_state()) != trx_state) - { + while ((state_out = rf_if_read_trx_state()) != trx_state) { while_counter++; - if(while_counter == 0x1ff) + if (while_counter == 0x1ff) { break; + } } return state_out; @@ -1571,8 +1550,7 @@ static rf_trx_states_t rf_poll_trx_state_change(rf_trx_states_t trx_state) static rf_trx_states_t rf_poll_for_state(void) { rf_trx_states_t state_out; - while((state_out = rf_if_read_trx_state()) == STATE_TRANSITION_IN_PROGRESS) - { + while ((state_out = rf_if_read_trx_state()) == STATE_TRANSITION_IN_PROGRESS) { } return state_out; @@ -1587,20 +1565,17 @@ static rf_trx_states_t rf_poll_for_state(void) * \return 0 Success * \return -1 Busy */ -static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol ) +static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol) { (void)data_protocol; rf_if_lock(); /*Check if transmitter is busy*/ rf_trx_states_t trx_state = rf_if_read_trx_state(); - if(trx_state == BUSY_RX || trx_state == BUSY_RX_AACK || data_length > RF_MTU - 2) - { + if (trx_state == BUSY_RX || trx_state == BUSY_RX_AACK || data_length > RF_MTU - 2) { rf_if_unlock(); /*Return busy*/ return -1; - } - else - { + } else { rf_give_up_on_ack(); /*Nanostack has a static TX buffer, which will remain valid until we*/ @@ -1686,42 +1661,32 @@ static bool rf_start_tx() static void rf_receive(rf_trx_states_t trx_status) { uint16_t while_counter = 0; - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_on(); rf_channel_set(rf_phy_channel); trx_status = TRX_OFF; } /*If not yet in RX state set it*/ - if(rf_flags_check(RFF_RX) == 0) - { + if (rf_flags_check(RFF_RX) == 0) { /*Wait while receiving data. Just making sure, usually this shouldn't happen. */ - while(trx_status == BUSY_RX || trx_status == BUSY_RX_AACK || trx_status == STATE_TRANSITION_IN_PROGRESS) - { + while (trx_status == BUSY_RX || trx_status == BUSY_RX_AACK || trx_status == STATE_TRANSITION_IN_PROGRESS) { while_counter++; - if(while_counter == 0xffff) - { + if (while_counter == 0xffff) { break; } trx_status = rf_if_read_trx_state(); } - if((rf_mode == RF_MODE_SNIFFER) || (rf_mode == RF_MODE_ED)) - { + if ((rf_mode == RF_MODE_SNIFFER) || (rf_mode == RF_MODE_ED)) { if (trx_status != RX_ON) { trx_status = rf_if_change_trx_state(RX_ON); } - } - else - { + } else { /*ACK is always received in promiscuous mode to bypass address filters*/ - if(rf_rx_mode) - { + if (rf_rx_mode) { rf_rx_mode = 0; rf_if_enable_promiscuous_mode(); - } - else - { + } else { rf_if_disable_promiscuous_mode(); } if (trx_status != RX_AACK_ON) { @@ -1729,8 +1694,7 @@ static void rf_receive(rf_trx_states_t trx_status) } } /*If calibration timer was unable to calibrate the RF, run calibration now*/ - if(!rf_tuned) - { + if (!rf_tuned) { /*Start calibration. This can be done in states TRX_OFF, PLL_ON or in any receive state*/ rf_if_calibration(); /*RF is tuned now*/ @@ -1753,8 +1717,7 @@ static void rf_calibration_cb(void) /*clear tuned flag to start tuning in rf_receive*/ rf_tuned = 0; /*If RF is in default receive state, start calibration*/ - if(rf_if_read_trx_state() == RX_AACK_ON) - { + if (rf_if_read_trx_state() == RX_AACK_ON) { rf_if_lock(); /*Set RF in PLL_ON state*/ rf_if_change_trx_state(PLL_ON); @@ -1783,14 +1746,15 @@ static void rf_calibration_cb(void) static void rf_on(void) { /*Set RFF_ON flag*/ - if(rf_flags_check(RFF_ON) == 0) - { + if (rf_flags_check(RFF_ON) == 0) { rf_if_lock(); rf_flags_set(RFF_ON); /*Enable Antenna diversity*/ - if(rf_use_antenna_diversity) + if (rf_use_antenna_diversity) /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/ + { rf_if_enable_ant_div(); + } /*Wake up from sleep state*/ rf_if_disable_slptr(); @@ -1814,7 +1778,7 @@ static void rf_give_up_on_ack(void) rf_if_ack_wait_timer_stop(); expected_ack_sequence = -1; - if(device_driver.phy_tx_done_cb){ + if (device_driver.phy_tx_done_cb) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_FAIL, 0, 0); } } @@ -1831,20 +1795,20 @@ static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending) { phy_link_tx_status_e phy_status; /*Received ACK sequence must be equal with transmitted packet sequence*/ - if(expected_ack_sequence == seq_number) - { + if (expected_ack_sequence == seq_number) { rf_if_disable_promiscuous_mode(); rf_if_ack_wait_timer_stop(); expected_ack_sequence = -1; /*When data pending bit in ACK frame is set, inform NET library*/ - if(data_pending) + if (data_pending) { phy_status = PHY_LINK_TX_DONE_PENDING; - else + } else { phy_status = PHY_LINK_TX_DONE; + } /*Call PHY TX Done API*/ - if(device_driver.phy_tx_done_cb){ - device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle,phy_status, 0, 0); + if (device_driver.phy_tx_done_cb) { + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, phy_status, 0, 0); } } else { rf_give_up_on_ack(); @@ -1861,7 +1825,7 @@ static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending) static void rf_handle_rx_end(rf_trx_states_t trx_status) { /*Frame received interrupt*/ - if(!rf_flags_check(RFF_RX)) { + if (!rf_flags_check(RFF_RX)) { return; } @@ -1886,8 +1850,7 @@ static void rf_handle_rx_end(rf_trx_states_t trx_status) rf_lqi = rf_scale_lqi(rf_rssi); /*Handle received ACK*/ - if((rf_buffer[0] & 0x07) == 0x02 && rf_mode != RF_MODE_SNIFFER) - { + if ((rf_buffer[0] & 0x07) == 0x02 && rf_mode != RF_MODE_SNIFFER) { /*Check if data is pending*/ bool pending = (rf_buffer[0] & 0x10); @@ -1895,7 +1858,7 @@ static void rf_handle_rx_end(rf_trx_states_t trx_status) rf_handle_ack(rf_buffer[2], pending); } else { rf_give_up_on_ack(); - if( device_driver.phy_rx_cb ){ + if (device_driver.phy_rx_cb) { device_driver.phy_rx_cb(rf_buffer, len - 2, rf_lqi, rf_rssi, rf_radio_driver_id); } } @@ -1925,8 +1888,7 @@ static void rf_handle_tx_end(rf_trx_states_t trx_status) { rf_rx_mode = 0; /*If ACK is needed for this transmission*/ - if((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX)) - { + if ((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX)) { expected_ack_sequence = rf_tx_data[2]; rf_ack_wait_timer_start(rf_ack_wait_duration); rf_rx_mode = 1; @@ -1936,7 +1898,7 @@ static void rf_handle_tx_end(rf_trx_states_t trx_status) rf_receive(trx_status); /*Call PHY TX Done API*/ - if(device_driver.phy_tx_done_cb){ + if (device_driver.phy_tx_done_cb) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0); } } @@ -1958,15 +1920,13 @@ static void rf_handle_cca_ed_done(uint8_t full_trx_status) bool success = false; /*Check the result of CCA process*/ - if((full_trx_status & CCA_STATUS) && rf_if_trx_status_from_full(full_trx_status) == RX_AACK_ON) - { + if ((full_trx_status & CCA_STATUS) && rf_if_trx_status_from_full(full_trx_status) == RX_AACK_ON) { success = rf_start_tx(); } - if (!success) - { + if (!success) { /*Send CCA fail notification*/ - if(device_driver.phy_tx_done_cb){ + if (device_driver.phy_tx_done_cb) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0); } } @@ -1983,8 +1943,7 @@ static void rf_handle_cca_ed_done(uint8_t full_trx_status) static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel) { int8_t ret_val = 0; - switch (new_state) - { + switch (new_state) { /*Reset PHY driver and set to idle*/ case PHY_INTERFACE_RESET: break; @@ -2033,16 +1992,12 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_ */ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr) { - switch (extension_type) - { + switch (extension_type) { /*Control MAC pending bit for Indirect data transmission*/ case PHY_EXTENSION_CTRL_PENDING_BIT: - if(*data_ptr) - { + if (*data_ptr) { rf_if_ack_pending_ctrl(1); - } - else - { + } else { rf_if_ack_pending_ctrl(0); } break; @@ -2084,12 +2039,11 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr) { int8_t ret_val = 0; - switch (address_type) - { + switch (address_type) { /*Set 48-bit address*/ case PHY_MAC_48BIT: break; - /*Set 64-bit address*/ + /*Set 64-bit address*/ case PHY_MAC_64BIT: rf_set_address(address_ptr); break; @@ -2119,137 +2073,93 @@ static void rf_init_phy_mode(void) /*Read used PHY Mode*/ tmp = rf_if_read_register(TRX_CTRL_2); /*Set ACK wait time for used data rate*/ - if(part == PART_AT86RF212) - { - if((tmp & 0x1f) == 0x00) - { + if (part == PART_AT86RF212) { + if ((tmp & 0x1f) == 0x00) { rf_sensitivity = -110; rf_ack_wait_duration = 938; tmp = BPSK_20; - } - else if((tmp & 0x1f) == 0x04) - { + } else if ((tmp & 0x1f) == 0x04) { rf_sensitivity = -108; rf_ack_wait_duration = 469; tmp = BPSK_40; - } - else if((tmp & 0x1f) == 0x14) - { + } else if ((tmp & 0x1f) == 0x14) { rf_sensitivity = -108; rf_ack_wait_duration = 469; tmp = BPSK_40_ALT; - } - else if((tmp & 0x1f) == 0x08) - { + } else if ((tmp & 0x1f) == 0x08) { rf_sensitivity = -101; rf_ack_wait_duration = 50; tmp = OQPSK_SIN_RC_100; - } - else if((tmp & 0x1f) == 0x09) - { + } else if ((tmp & 0x1f) == 0x09) { rf_sensitivity = -99; rf_ack_wait_duration = 30; tmp = OQPSK_SIN_RC_200; - } - else if((tmp & 0x1f) == 0x18) - { + } else if ((tmp & 0x1f) == 0x18) { rf_sensitivity = -102; rf_ack_wait_duration = 50; tmp = OQPSK_RC_100; - } - else if((tmp & 0x1f) == 0x19) - { + } else if ((tmp & 0x1f) == 0x19) { rf_sensitivity = -100; rf_ack_wait_duration = 30; tmp = OQPSK_RC_200; - } - else if((tmp & 0x1f) == 0x0c) - { + } else if ((tmp & 0x1f) == 0x0c) { rf_sensitivity = -100; rf_ack_wait_duration = 20; tmp = OQPSK_SIN_250; - } - else if((tmp & 0x1f) == 0x0d) - { + } else if ((tmp & 0x1f) == 0x0d) { rf_sensitivity = -98; rf_ack_wait_duration = 25; tmp = OQPSK_SIN_500; - } - else if((tmp & 0x1f) == 0x0f) - { + } else if ((tmp & 0x1f) == 0x0f) { rf_sensitivity = -98; rf_ack_wait_duration = 25; tmp = OQPSK_SIN_500_ALT; - } - else if((tmp & 0x1f) == 0x1c) - { + } else if ((tmp & 0x1f) == 0x1c) { rf_sensitivity = -101; rf_ack_wait_duration = 20; tmp = OQPSK_RC_250; - } - else if((tmp & 0x1f) == 0x1d) - { + } else if ((tmp & 0x1f) == 0x1d) { rf_sensitivity = -99; rf_ack_wait_duration = 25; tmp = OQPSK_RC_500; - } - else if((tmp & 0x1f) == 0x1f) - { + } else if ((tmp & 0x1f) == 0x1f) { rf_sensitivity = -99; rf_ack_wait_duration = 25; tmp = OQPSK_RC_500_ALT; - } - else if((tmp & 0x3f) == 0x2A) - { + } else if ((tmp & 0x3f) == 0x2A) { rf_sensitivity = -91; rf_ack_wait_duration = 25; tmp = OQPSK_SIN_RC_400_SCR_ON; - } - else if((tmp & 0x3f) == 0x0A) - { + } else if ((tmp & 0x3f) == 0x0A) { rf_sensitivity = -91; rf_ack_wait_duration = 25; tmp = OQPSK_SIN_RC_400_SCR_OFF; - } - else if((tmp & 0x3f) == 0x3A) - { + } else if ((tmp & 0x3f) == 0x3A) { rf_sensitivity = -97; rf_ack_wait_duration = 25; tmp = OQPSK_RC_400_SCR_ON; - } - else if((tmp & 0x3f) == 0x1A) - { + } else if ((tmp & 0x3f) == 0x1A) { rf_sensitivity = -97; rf_ack_wait_duration = 25; tmp = OQPSK_RC_400_SCR_OFF; - } - else if((tmp & 0x3f) == 0x2E) - { + } else if ((tmp & 0x3f) == 0x2E) { rf_sensitivity = -93; rf_ack_wait_duration = 13; tmp = OQPSK_SIN_1000_SCR_ON; - } - else if((tmp & 0x3f) == 0x0E) - { + } else if ((tmp & 0x3f) == 0x0E) { rf_sensitivity = -93; rf_ack_wait_duration = 13; tmp = OQPSK_SIN_1000_SCR_OFF; - } - else if((tmp & 0x3f) == 0x3E) - { + } else if ((tmp & 0x3f) == 0x3E) { rf_sensitivity = -95; rf_ack_wait_duration = 13; tmp = OQPSK_RC_1000_SCR_ON; - } - else if((tmp & 0x3f) == 0x1E) - { + } else if ((tmp & 0x3f) == 0x1E) { rf_sensitivity = -95; rf_ack_wait_duration = 13; tmp = OQPSK_RC_1000_SCR_OFF; } - } - else - { + } else { rf_sensitivity = -101; rf_ack_wait_duration = 20; } @@ -2263,50 +2173,60 @@ static uint8_t rf_scale_lqi(int8_t rssi) uint8_t scaled_lqi; /*rssi < RF sensitivity*/ - if(rssi < rf_sensitivity) - scaled_lqi=0; + if (rssi < rf_sensitivity) { + scaled_lqi = 0; + } /*-91 dBm < rssi < -81 dBm (AT86RF233 XPro)*/ /*-90 dBm < rssi < -80 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 10)) - scaled_lqi=31; + else if (rssi < (rf_sensitivity + 10)) { + scaled_lqi = 31; + } /*-81 dBm < rssi < -71 dBm (AT86RF233 XPro)*/ /*-80 dBm < rssi < -70 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 20)) - scaled_lqi=207; + else if (rssi < (rf_sensitivity + 20)) { + scaled_lqi = 207; + } /*-71 dBm < rssi < -61 dBm (AT86RF233 XPro)*/ /*-70 dBm < rssi < -60 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 30)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 30)) { + scaled_lqi = 255; + } /*-61 dBm < rssi < -51 dBm (AT86RF233 XPro)*/ /*-60 dBm < rssi < -50 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 40)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 40)) { + scaled_lqi = 255; + } /*-51 dBm < rssi < -41 dBm (AT86RF233 XPro)*/ /*-50 dBm < rssi < -40 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 50)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 50)) { + scaled_lqi = 255; + } /*-41 dBm < rssi < -31 dBm (AT86RF233 XPro)*/ /*-40 dBm < rssi < -30 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 60)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 60)) { + scaled_lqi = 255; + } /*-31 dBm < rssi < -21 dBm (AT86RF233 XPro)*/ /*-30 dBm < rssi < -20 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 70)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 70)) { + scaled_lqi = 255; + } /*rssi > RF saturation*/ - else if(rssi > (rf_sensitivity + 80)) - scaled_lqi=111; + else if (rssi > (rf_sensitivity + 80)) { + scaled_lqi = 111; + } /*-21 dBm < rssi < -11 dBm (AT86RF233 XPro)*/ /*-20 dBm < rssi < -10 dBm (AT86RF212B XPro)*/ - else - scaled_lqi=255; + else { + scaled_lqi = 255; + } return scaled_lqi; } NanostackRfPhyAtmel::NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso, - PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq, - PinName i2c_sda, PinName i2c_scl) + PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq, + PinName i2c_sda, PinName i2c_scl) : _mac(i2c_sda, i2c_scl), _mac_addr(), _rf(NULL), _mac_set(false), _spi_mosi(spi_mosi), _spi_miso(spi_miso), _spi_sclk(spi_sclk), _spi_cs(spi_cs), _spi_rst(spi_rst), _spi_slp(spi_slp), _spi_irq(spi_irq) @@ -2336,7 +2256,7 @@ int8_t NanostackRfPhyAtmel::rf_register() // Read the mac address if it hasn't been set by a user rf = _rf; if (!_mac_set) { - int ret = _mac.read_eui64((void*)_mac_addr); + int ret = _mac.read_eui64((void *)_mac_addr); if (ret < 0) { rf = NULL; rf_if_unlock(); @@ -2377,7 +2297,7 @@ void NanostackRfPhyAtmel::get_mac_address(uint8_t *mac) rf_if_unlock(); return; } - memcpy((void*)mac, (void*)_mac_addr, sizeof(_mac_addr)); + memcpy((void *)mac, (void *)_mac_addr, sizeof(_mac_addr)); rf_if_unlock(); } @@ -2391,7 +2311,7 @@ void NanostackRfPhyAtmel::set_mac_address(uint8_t *mac) rf_if_unlock(); return; } - memcpy((void*)_mac_addr, (void*)mac, sizeof(_mac_addr)); + memcpy((void *)_mac_addr, (void *)mac, sizeof(_mac_addr)); _mac_set = true; rf_if_unlock(); @@ -2401,9 +2321,9 @@ void NanostackRfPhyAtmel::set_mac_address(uint8_t *mac) NanostackRfPhy &NanostackRfPhy::get_default_instance() { - static NanostackRfPhyAtmel rf_phy(ATMEL_SPI_MOSI, ATMEL_SPI_MISO, ATMEL_SPI_SCLK, ATMEL_SPI_CS, - ATMEL_SPI_RST, ATMEL_SPI_SLP, ATMEL_SPI_IRQ, ATMEL_I2C_SDA, ATMEL_I2C_SCL); - return rf_phy; + static NanostackRfPhyAtmel rf_phy(ATMEL_SPI_MOSI, ATMEL_SPI_MISO, ATMEL_SPI_SCLK, ATMEL_SPI_CS, + ATMEL_SPI_RST, ATMEL_SPI_SLP, ATMEL_SPI_IRQ, ATMEL_I2C_SDA, ATMEL_I2C_SCL); + return rf_phy; } #endif // MBED_CONF_ATMEL_RF_PROVIDE_DEFAULT diff --git a/components/802.15.4_RF/atmel-rf-driver/source/at24mac.cpp b/components/802.15.4_RF/atmel-rf-driver/source/at24mac.cpp index 7f06976849f..cdb18a0cb7c 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/at24mac.cpp +++ b/components/802.15.4_RF/atmel-rf-driver/source/at24mac.cpp @@ -18,14 +18,14 @@ #if DEVICE_I2C /* Device addressing */ -#define AT24MAC_EEPROM_ADDRESS (0x0A<<4) -#define AT24MAC_RW_PROTECT_ADDRESS (0x06<<4) -#define AT24MAC_SERIAL_ADDRESS (0x0B<<4) +#define AT24MAC_EEPROM_ADDRESS (0x0A<<4) +#define AT24MAC_RW_PROTECT_ADDRESS (0x06<<4) +#define AT24MAC_SERIAL_ADDRESS (0x0B<<4) /* Known memory blocks */ -#define AT24MAC_SERIAL_OFFSET (0x80) -#define AT24MAC_EUI64_OFFSET (0x98) -#define AT24MAC_EUI48_OFFSET (0x9A) +#define AT24MAC_SERIAL_OFFSET (0x80) +#define AT24MAC_EUI64_OFFSET (0x98) +#define AT24MAC_EUI48_OFFSET (0x9A) #define SERIAL_LEN 16 #define EUI64_LEN 8 @@ -33,7 +33,7 @@ using namespace mbed; -AT24Mac::AT24Mac(PinName sda, PinName scl) : _i2c(sda , scl) +AT24Mac::AT24Mac(PinName sda, PinName scl) : _i2c(sda, scl) { // Do nothing } @@ -41,25 +41,28 @@ AT24Mac::AT24Mac(PinName sda, PinName scl) : _i2c(sda , scl) int AT24Mac::read_serial(void *buf) { char offset = AT24MAC_SERIAL_OFFSET; - if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) - return -1; //No ACK - return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, SERIAL_LEN); + if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) { + return -1; //No ACK + } + return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, SERIAL_LEN); } int AT24Mac::read_eui64(void *buf) { char offset = AT24MAC_EUI64_OFFSET; - if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) - return -1; //No ACK - return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, EUI64_LEN); + if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) { + return -1; //No ACK + } + return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, EUI64_LEN); } int AT24Mac::read_eui48(void *buf) { char offset = AT24MAC_EUI48_OFFSET; - if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) - return -1; //No ACK - return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, EUI48_LEN); + if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true)) { + return -1; //No ACK + } + return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char *)buf, EUI48_LEN); } #endif /* DEVICE_I2C */ From 135a894b079caf91f998d6bf6ea8b6d035edc801 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Wed, 31 Oct 2018 16:11:34 +0200 Subject: [PATCH 04/10] Sync with MCR20a RF driver v1.0.2 --- .../mcr20a-rf-driver/source/MCR20Drv.c | 140 +++--- .../mcr20a-rf-driver/source/MCR20Drv.h | 84 ++-- .../mcr20a-rf-driver/source/MCR20Overwrites.h | 192 ++++----- .../mcr20a-rf-driver/source/MCR20Reg.h | 208 ++++----- .../source/NanostackRfPhyMcr20a.cpp | 403 ++++++++---------- .../mcr20a-rf-driver/source/XcvrSpi.h | 10 +- 6 files changed, 490 insertions(+), 547 deletions(-) diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c index 23088cb4ea4..f561c0d412a 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c @@ -106,16 +106,16 @@ uint32_t mPhyIrqDisableCnt = 1; *---------------------------------------------------------------------------*/ void MCR20Drv_Init ( -void + void ) { xcvr_spi_init(gXcvrSpiInstance_c); xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000); gXcvrDeassertCS_d(); - #if !defined(TARGET_KW24D) - MCR20Drv_RST_B_Deassert(); - #endif +#if !defined(TARGET_KW24D) + MCR20Drv_RST_B_Deassert(); +#endif RF_IRQ_Init(); RF_IRQ_Disable(); mPhyIrqDisableCnt = 1; @@ -129,8 +129,8 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_DirectAccessSPIWrite ( -uint8_t address, -uint8_t value + uint8_t address, + uint8_t value ) { uint16_t txData; @@ -158,15 +158,14 @@ uint8_t value *---------------------------------------------------------------------------*/ void MCR20Drv_DirectAccessSPIMultiByteWrite ( -uint8_t startAddress, -uint8_t * byteArray, -uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ) { uint8_t txData; - if( (numOfBytes == 0) || (byteArray == 0) ) - { + if ((numOfBytes == 0) || (byteArray == 0)) { return; } @@ -193,8 +192,8 @@ uint8_t numOfBytes *---------------------------------------------------------------------------*/ void MCR20Drv_PB_SPIByteWrite ( -uint8_t address, -uint8_t value + uint8_t address, + uint8_t value ) { uint32_t txData; @@ -206,12 +205,12 @@ uint8_t value gXcvrAssertCS_d(); txData = TransceiverSPI_WriteSelect | - TransceiverSPI_PacketBuffAccessSelect | - TransceiverSPI_PacketBuffByteModeSelect; + TransceiverSPI_PacketBuffAccessSelect | + TransceiverSPI_PacketBuffByteModeSelect; txData |= (address) << 8; txData |= (value) << 16; - xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3); + xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, 3); gXcvrDeassertCS_d(); UnprotectFromMCR20Interrupt(); @@ -225,14 +224,13 @@ uint8_t value *---------------------------------------------------------------------------*/ void MCR20Drv_PB_SPIBurstWrite ( -uint8_t * byteArray, -uint8_t numOfBytes + uint8_t *byteArray, + uint8_t numOfBytes ) { uint8_t txData; - if( (numOfBytes == 0) || (byteArray == 0) ) - { + if ((numOfBytes == 0) || (byteArray == 0)) { return; } @@ -243,8 +241,8 @@ uint8_t numOfBytes gXcvrAssertCS_d(); txData = TransceiverSPI_WriteSelect | - TransceiverSPI_PacketBuffAccessSelect | - TransceiverSPI_PacketBuffBurstModeSelect; + TransceiverSPI_PacketBuffAccessSelect | + TransceiverSPI_PacketBuffBurstModeSelect; xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, 1); xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes); @@ -262,7 +260,7 @@ uint8_t numOfBytes uint8_t MCR20Drv_DirectAccessSPIRead ( -uint8_t address + uint8_t address ) { uint8_t txData; @@ -275,7 +273,7 @@ uint8_t address gXcvrAssertCS_d(); txData = (address & TransceiverSPI_DirectRegisterAddressMask) | - TransceiverSPI_ReadSelect; + TransceiverSPI_ReadSelect; xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData)); xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData)); @@ -295,16 +293,15 @@ uint8_t address *---------------------------------------------------------------------------*/ uint8_t MCR20Drv_DirectAccessSPIMultiByteRead ( -uint8_t startAddress, -uint8_t * byteArray, -uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ) { uint8_t txData; uint8_t phyIRQSTS1; - if( (numOfBytes == 0) || (byteArray == 0) ) - { + if ((numOfBytes == 0) || (byteArray == 0)) { return 0; } @@ -315,7 +312,7 @@ uint8_t numOfBytes gXcvrAssertCS_d(); txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) | - TransceiverSPI_ReadSelect; + TransceiverSPI_ReadSelect; xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData)); xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes); @@ -334,15 +331,14 @@ uint8_t numOfBytes *---------------------------------------------------------------------------*/ uint8_t MCR20Drv_PB_SPIBurstRead ( -uint8_t * byteArray, -uint8_t numOfBytes + uint8_t *byteArray, + uint8_t numOfBytes ) { uint8_t txData; uint8_t phyIRQSTS1; - if( (numOfBytes == 0) || (byteArray == 0) ) - { + if ((numOfBytes == 0) || (byteArray == 0)) { return 0; } @@ -353,8 +349,8 @@ uint8_t numOfBytes gXcvrAssertCS_d(); txData = TransceiverSPI_ReadSelect | - TransceiverSPI_PacketBuffAccessSelect | - TransceiverSPI_PacketBuffBurstModeSelect; + TransceiverSPI_PacketBuffAccessSelect | + TransceiverSPI_PacketBuffBurstModeSelect; xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData)); xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes); @@ -373,8 +369,8 @@ uint8_t numOfBytes *---------------------------------------------------------------------------*/ void MCR20Drv_IndirectAccessSPIWrite ( -uint8_t address, -uint8_t value + uint8_t address, + uint8_t value ) { uint32_t txData; @@ -389,7 +385,7 @@ uint8_t value txData |= (address) << 8; txData |= (value) << 16; - xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3); + xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, 3); gXcvrDeassertCS_d(); UnprotectFromMCR20Interrupt(); @@ -403,15 +399,14 @@ uint8_t value *---------------------------------------------------------------------------*/ void MCR20Drv_IndirectAccessSPIMultiByteWrite ( -uint8_t startAddress, -uint8_t * byteArray, -uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ) { uint16_t txData; - if( (numOfBytes == 0) || (byteArray == 0) ) - { + if ((numOfBytes == 0) || (byteArray == 0)) { return; } @@ -424,8 +419,8 @@ uint8_t numOfBytes txData = TransceiverSPI_IARIndexReg; txData |= (startAddress) << 8; - xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData)); - xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes); + xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData)); + xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)byteArray, 0, numOfBytes); gXcvrDeassertCS_d(); UnprotectFromMCR20Interrupt(); @@ -439,7 +434,7 @@ uint8_t numOfBytes *---------------------------------------------------------------------------*/ uint8_t MCR20Drv_IndirectAccessSPIRead ( -uint8_t address + uint8_t address ) { uint16_t txData; @@ -454,7 +449,7 @@ uint8_t address txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect; txData |= (address) << 8; - xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData)); + xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData)); xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData)); gXcvrDeassertCS_d(); @@ -471,15 +466,14 @@ uint8_t address *---------------------------------------------------------------------------*/ void MCR20Drv_IndirectAccessSPIMultiByteRead ( -uint8_t startAddress, -uint8_t * byteArray, -uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ) { uint16_t txData; - if( (numOfBytes == 0) || (byteArray == 0) ) - { + if ((numOfBytes == 0) || (byteArray == 0)) { return; } @@ -492,7 +486,7 @@ uint8_t numOfBytes txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect); txData |= (startAddress) << 8; - xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData)); + xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData)); xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes); gXcvrDeassertCS_d(); @@ -507,7 +501,7 @@ uint8_t numOfBytes *---------------------------------------------------------------------------*/ uint32_t MCR20Drv_IsIrqPending ( -void + void ) { return RF_isIRQ_Pending(); @@ -521,13 +515,12 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_IRQ_Disable ( -void + void ) { core_util_critical_section_enter(); - if( mPhyIrqDisableCnt == 0 ) - { + if (mPhyIrqDisableCnt == 0) { RF_IRQ_Disable(); } @@ -544,17 +537,15 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_IRQ_Enable ( -void + void ) { core_util_critical_section_enter(); - if( mPhyIrqDisableCnt ) - { + if (mPhyIrqDisableCnt) { mPhyIrqDisableCnt--; - if( mPhyIrqDisableCnt == 0 ) - { + if (mPhyIrqDisableCnt == 0) { RF_IRQ_Enable(); } } @@ -570,7 +561,7 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_RST_B_Assert ( -void + void ) { RF_RST_Set(0); @@ -584,7 +575,7 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_RST_B_Deassert ( -void + void ) { RF_RST_Set(1); @@ -598,7 +589,7 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_SoftRST_Assert ( -void + void ) { MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80)); @@ -612,7 +603,7 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_SoftRST_Deassert ( -void + void ) { MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00)); @@ -626,7 +617,7 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_Soft_RESET ( -void + void ) { //assert SOG_RST @@ -644,19 +635,19 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_RESET ( -void + void ) { - #if !defined(TARGET_KW24D) +#if !defined(TARGET_KW24D) volatile uint32_t delay = 1000; //assert RST_B MCR20Drv_RST_B_Assert(); - while(delay--); + while (delay--); //deassert RST_B MCR20Drv_RST_B_Deassert(); - #endif +#endif } /*--------------------------------------------------------------------------- @@ -667,13 +658,12 @@ void *---------------------------------------------------------------------------*/ void MCR20Drv_Set_CLK_OUT_Freq ( -uint8_t freqDiv + uint8_t freqDiv ) { uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND; - if(freqDiv == gCLK_OUT_FREQ_DISABLE) - { + if (freqDiv == gCLK_OUT_FREQ_DISABLE) { clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled } diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h index 332de94a5d3..c2d013eb522 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h @@ -53,7 +53,7 @@ *****************************************************************************/ /* Disable XCVR clock output by default, to reduce power consumption */ -#ifndef gMCR20_ClkOutFreq_d +#ifndef gMCR20_ClkOutFreq_d #define gMCR20_ClkOutFreq_d gCLK_OUT_FREQ_DISABLE #endif @@ -73,7 +73,7 @@ *---------------------------------------------------------------------------*/ extern void MCR20Drv_Init ( - void + void ); /*--------------------------------------------------------------------------- @@ -84,7 +84,7 @@ extern void MCR20Drv_Init *---------------------------------------------------------------------------*/ void MCR20Drv_SPI_DMA_Init ( - void + void ); /*--------------------------------------------------------------------------- @@ -95,8 +95,8 @@ void MCR20Drv_SPI_DMA_Init *---------------------------------------------------------------------------*/ void MCR20Drv_Start_PB_DMA_SPI_Write ( - uint8_t * srcAddress, - uint8_t numOfBytes + uint8_t *srcAddress, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -107,8 +107,8 @@ void MCR20Drv_Start_PB_DMA_SPI_Write *---------------------------------------------------------------------------*/ void MCR20Drv_Start_PB_DMA_SPI_Read ( - uint8_t * dstAddress, - uint8_t numOfBytes + uint8_t *dstAddress, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -119,8 +119,8 @@ void MCR20Drv_Start_PB_DMA_SPI_Read *---------------------------------------------------------------------------*/ void MCR20Drv_DirectAccessSPIWrite ( - uint8_t address, - uint8_t value + uint8_t address, + uint8_t value ); /*--------------------------------------------------------------------------- @@ -131,9 +131,9 @@ void MCR20Drv_DirectAccessSPIWrite *---------------------------------------------------------------------------*/ void MCR20Drv_DirectAccessSPIMultiByteWrite ( - uint8_t startAddress, - uint8_t * byteArray, - uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -144,8 +144,8 @@ void MCR20Drv_DirectAccessSPIMultiByteWrite *---------------------------------------------------------------------------*/ void MCR20Drv_PB_SPIBurstWrite ( - uint8_t * byteArray, - uint8_t numOfBytes + uint8_t *byteArray, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -156,7 +156,7 @@ void MCR20Drv_PB_SPIBurstWrite *---------------------------------------------------------------------------*/ uint8_t MCR20Drv_DirectAccessSPIRead ( - uint8_t address + uint8_t address ); /*--------------------------------------------------------------------------- @@ -168,9 +168,9 @@ uint8_t MCR20Drv_DirectAccessSPIRead uint8_t MCR20Drv_DirectAccessSPIMultiByteRead ( - uint8_t startAddress, - uint8_t * byteArray, - uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -181,8 +181,8 @@ uint8_t MCR20Drv_DirectAccessSPIMultiByteRead *---------------------------------------------------------------------------*/ void MCR20Drv_PB_SPIByteWrite ( - uint8_t address, - uint8_t value + uint8_t address, + uint8_t value ); /*--------------------------------------------------------------------------- @@ -193,8 +193,8 @@ void MCR20Drv_PB_SPIByteWrite *---------------------------------------------------------------------------*/ uint8_t MCR20Drv_PB_SPIBurstRead ( - uint8_t * byteArray, - uint8_t numOfBytes + uint8_t *byteArray, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -205,8 +205,8 @@ uint8_t MCR20Drv_PB_SPIBurstRead *---------------------------------------------------------------------------*/ void MCR20Drv_IndirectAccessSPIWrite ( - uint8_t address, - uint8_t value + uint8_t address, + uint8_t value ); /*--------------------------------------------------------------------------- @@ -217,9 +217,9 @@ void MCR20Drv_IndirectAccessSPIWrite *---------------------------------------------------------------------------*/ void MCR20Drv_IndirectAccessSPIMultiByteWrite ( - uint8_t startAddress, - uint8_t * byteArray, - uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -230,7 +230,7 @@ void MCR20Drv_IndirectAccessSPIMultiByteWrite *---------------------------------------------------------------------------*/ uint8_t MCR20Drv_IndirectAccessSPIRead ( - uint8_t address + uint8_t address ); /*--------------------------------------------------------------------------- * Name: MCR20Drv_IndirectAccessSPIMultiByteRead @@ -240,9 +240,9 @@ uint8_t MCR20Drv_IndirectAccessSPIRead *---------------------------------------------------------------------------*/ void MCR20Drv_IndirectAccessSPIMultiByteRead ( - uint8_t startAddress, - uint8_t * byteArray, - uint8_t numOfBytes + uint8_t startAddress, + uint8_t *byteArray, + uint8_t numOfBytes ); /*--------------------------------------------------------------------------- @@ -253,7 +253,7 @@ void MCR20Drv_IndirectAccessSPIMultiByteRead *---------------------------------------------------------------------------*/ uint32_t MCR20Drv_IsIrqPending ( - void + void ); /*--------------------------------------------------------------------------- @@ -264,7 +264,7 @@ uint32_t MCR20Drv_IsIrqPending *---------------------------------------------------------------------------*/ void MCR20Drv_IRQ_Disable ( - void + void ); /*--------------------------------------------------------------------------- @@ -275,7 +275,7 @@ void MCR20Drv_IRQ_Disable *---------------------------------------------------------------------------*/ void MCR20Drv_IRQ_Enable ( - void + void ); /*--------------------------------------------------------------------------- @@ -286,7 +286,7 @@ void MCR20Drv_IRQ_Enable *---------------------------------------------------------------------------*/ void MCR20Drv_RST_B_PortConfig ( - void + void ); /*--------------------------------------------------------------------------- @@ -297,7 +297,7 @@ void MCR20Drv_RST_B_PortConfig *---------------------------------------------------------------------------*/ void MCR20Drv_RST_B_Assert ( - void + void ); /*--------------------------------------------------------------------------- @@ -308,7 +308,7 @@ void MCR20Drv_RST_B_Assert *---------------------------------------------------------------------------*/ void MCR20Drv_RST_B_Deassert ( - void + void ); /*--------------------------------------------------------------------------- @@ -319,7 +319,7 @@ void MCR20Drv_RST_B_Deassert *---------------------------------------------------------------------------*/ void MCR20Drv_SoftRST_Assert ( - void + void ); /*--------------------------------------------------------------------------- @@ -330,7 +330,7 @@ void MCR20Drv_SoftRST_Assert *---------------------------------------------------------------------------*/ void MCR20Drv_SoftRST_Deassert ( - void + void ); @@ -342,7 +342,7 @@ void MCR20Drv_SoftRST_Deassert *---------------------------------------------------------------------------*/ void MCR20Drv_RESET ( - void + void ); /*--------------------------------------------------------------------------- @@ -353,7 +353,7 @@ void MCR20Drv_RESET *---------------------------------------------------------------------------*/ void MCR20Drv_Soft_RESET ( - void + void ); /*--------------------------------------------------------------------------- @@ -364,7 +364,7 @@ void MCR20Drv_Soft_RESET *---------------------------------------------------------------------------*/ void MCR20Drv_Set_CLK_OUT_Freq ( - uint8_t freqDiv + uint8_t freqDiv ); #define ProtectFromMCR20Interrupt() MCR20Drv_IRQ_Disable() diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h index 4b0221132ba..3b2c063f3f2 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h @@ -35,9 +35,9 @@ #define OVERWRITES_H_ typedef struct overwrites_tag { - char address; - char data; -}overwrites_t; + char address; + char data; +} overwrites_t; /*****************************************************************************************************************/ @@ -66,37 +66,37 @@ typedef struct overwrites_tag { // // Write access to direct space requires only a single address, data pair. -overwrites_t const overwrites_direct[] ={ -{0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak) -{0x23, 0x17} //PA_PWR new default Power Step is "23" +overwrites_t const overwrites_direct[] = { + {0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak) + {0x23, 0x17} //PA_PWR new default Power Step is "23" }; -overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 -{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) -{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) -{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) -{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration -{0x52, 0x55}, //AGC_THR1 RSSI tune up -{0x53, 0x2D}, //AGC_THR2 RSSI tune up -{0x66, 0x5F}, //ATT_RSSI1 tune up -{0x67, 0x8F}, //ATT_RSSI2 tune up -{0x68, 0x61}, //RSSI_OFFSET -{0x78, 0x03}, //CHF_PMAGAIN -{0x22, 0x50}, //CCA1_THRESH -{0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity -{0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak) +overwrites_t const overwrites_indirect[] = { + {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) + {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 + {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 + {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) + {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) + {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) + {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) + {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration + {0x52, 0x55}, //AGC_THR1 RSSI tune up + {0x53, 0x2D}, //AGC_THR2 RSSI tune up + {0x66, 0x5F}, //ATT_RSSI1 tune up + {0x67, 0x8F}, //ATT_RSSI2 tune up + {0x68, 0x61}, //RSSI_OFFSET + {0x78, 0x03}, //CHF_PMAGAIN + {0x22, 0x50}, //CCA1_THRESH + {0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity + {0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak) }; @@ -107,25 +107,25 @@ overwrites_t const overwrites_indirect[] ={ ==VERSION 2== overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) }; ==VERSION 3== overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3 -{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 }; ==VERSION 4== overwrites_t const overwrites_direct[] ={ -{0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default +{0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3 -{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) }; @@ -135,9 +135,9 @@ overwrites_t const overwrites_direct[] ={ }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) @@ -154,13 +154,13 @@ overwrites_t const overwrites_indirect[] ={ ==VERSION 6== overwrites_t const overwrites_direct[] ={ -{0x3B, 0x06} //version 06: disable PA calibration +{0x3B, 0x06} //version 06: disable PA calibration }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) @@ -173,18 +173,18 @@ overwrites_t const overwrites_indirect[] ={ {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration +{0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration }; ==VERSION 7== overwrites_t const overwrites_direct[] ={ -{0x3B, 0x07} //version 07: updated registers for ED/RSSI +{0x3B, 0x07} //version 07: updated registers for ED/RSSI }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) @@ -197,25 +197,25 @@ overwrites_t const overwrites_indirect[] ={ {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration -{0x52, 0x73}, //AGC_THR1 RSSI tune up -{0x53, 0x2D}, //AGC_THR2 RSSI tune up -{0x66, 0x5F}, //ATT_RSSI1 tune up -{0x67, 0x8F}, //ATT_RSSI2 tune up -{0x68, 0x60}, //RSSI_OFFSET -{0x69, 0x65} //RSSI_SLOPE +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x73}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x60}, //RSSI_OFFSET +{0x69, 0x65} //RSSI_SLOPE }; ==VERSION 8== overwrites_t const overwrites_direct[] ={ -{0x3B, 0x08} //version 08: updated registers for ED/RSSI +{0x3B, 0x08} //version 08: updated registers for ED/RSSI }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) @@ -228,27 +228,27 @@ overwrites_t const overwrites_indirect[] ={ {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration -{0x52, 0x73}, //AGC_THR1 RSSI tune up -{0x53, 0x2D}, //AGC_THR2 RSSI tune up -{0x66, 0x5F}, //ATT_RSSI1 tune up -{0x67, 0x8F}, //ATT_RSSI2 tune up -{0x69, 0x65} //RSSI_SLOPE -{0x68, 0x61}, //RSSI_OFFSET -{0x78, 0x03} //CHF_PMAGAIN +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x73}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x69, 0x65} //RSSI_SLOPE +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03} //CHF_PMAGAIN }; ==VERSION 9== overwrites_t const overwrites_direct[] ={ -{0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep -{0x23, 0x17} //PA_PWR new default value +{0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep +{0x23, 0x17} //PA_PWR new default value }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) @@ -261,25 +261,25 @@ overwrites_t const overwrites_indirect[] ={ {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration -{0x52, 0x55}, //AGC_THR1 RSSI tune up -{0x53, 0x2D}, //AGC_THR2 RSSI tune up -{0x66, 0x5F}, //ATT_RSSI1 tune up -{0x67, 0x8F}, //ATT_RSSI2 tune up -{0x68, 0x61}, //RSSI_OFFSET -{0x78, 0x03} //CHF_PMAGAIN +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x55}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03} //CHF_PMAGAIN }; ==VERSION A== overwrites_t const overwrites_direct[] ={ -{0x3B, 0x0A} //version 0A: updated registers for CCA -{0x23, 0x17} //PA_PWR new default Power Step is "23" +{0x3B, 0x0A} //version 0A: updated registers for CCA +{0x23, 0x17} //PA_PWR new default Power Step is "23" }; overwrites_t const overwrites_indirect[] ={ -{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) -{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 -{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) @@ -292,14 +292,14 @@ overwrites_t const overwrites_indirect[] ={ {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) -{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration -{0x52, 0x55}, //AGC_THR1 RSSI tune up -{0x53, 0x2D}, //AGC_THR2 RSSI tune up -{0x66, 0x5F}, //ATT_RSSI1 tune up -{0x67, 0x8F}, //ATT_RSSI2 tune up -{0x68, 0x61}, //RSSI_OFFSET -{0x78, 0x03} //CHF_PMAGAIN -{0x22, 0x50} //CCA1_THRESH +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x55}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03} //CHF_PMAGAIN +{0x22, 0x50} //CCA1_THRESH }; end of deprecated versions */ diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h index a77686f2a04..96410c9a9c6 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h @@ -312,18 +312,18 @@ #define cIRQSTS1_TXIRQ (1<<1) #define cIRQSTS1_SEQIRQ (1<<0) -typedef union regIRQSTS1_tag{ - uint8_t byte; - struct{ - uint8_t SEQIRQ:1; - uint8_t TXIRQ:1; - uint8_t RXIRQ:1; - uint8_t CCAIRQ:1; - uint8_t RXWTRMRKIRQ:1; - uint8_t FILTERFAIL_IRQ:1; - uint8_t PLL_UNLOCK_IRQ:1; - uint8_t RX_FRM_PEND:1; - }bit; +typedef union regIRQSTS1_tag { + uint8_t byte; + struct { + uint8_t SEQIRQ: 1; + uint8_t TXIRQ: 1; + uint8_t RXIRQ: 1; + uint8_t CCAIRQ: 1; + uint8_t RXWTRMRKIRQ: 1; + uint8_t FILTERFAIL_IRQ: 1; + uint8_t PLL_UNLOCK_IRQ: 1; + uint8_t RX_FRM_PEND: 1; + } bit; } regIRQSTS1_t; // IRQSTS2 bits @@ -336,18 +336,18 @@ typedef union regIRQSTS1_tag{ #define cIRQSTS2_PB_ERR_IRQ (1<<1) #define cIRQSTS2_WAKE_IRQ (1<<0) -typedef union regIRQSTS2_tag{ - uint8_t byte; - struct{ - uint8_t WAKE_IRQ:1; - uint8_t PB_ERR_IRQ:1; - uint8_t ASM_IRQ:1; - uint8_t TMRSTATUS:1; - uint8_t PI_:1; - uint8_t SRCADDR:1; - uint8_t CCA:1; - uint8_t CRCVALID:1; - }bit; +typedef union regIRQSTS2_tag { + uint8_t byte; + struct { + uint8_t WAKE_IRQ: 1; + uint8_t PB_ERR_IRQ: 1; + uint8_t ASM_IRQ: 1; + uint8_t TMRSTATUS: 1; + uint8_t PI_: 1; + uint8_t SRCADDR: 1; + uint8_t CCA: 1; + uint8_t CRCVALID: 1; + } bit; } regIRQSTS2_t; // IRQSTS3 bits @@ -360,18 +360,18 @@ typedef union regIRQSTS2_tag{ #define cIRQSTS3_TMR2IRQ (1<<1) #define cIRQSTS3_TMR1IRQ (1<<0) -typedef union regIRQSTS3_tag{ - uint8_t byte; - struct{ - uint8_t TMR1IRQ:1; - uint8_t TMR2IRQ:1; - uint8_t TMR3IRQ:1; - uint8_t TMR4IRQ:1; - uint8_t TMR1MSK:1; - uint8_t TMR2MSK:1; - uint8_t TMR3MSK:1; - uint8_t TMR4MSK:1; - }bit; +typedef union regIRQSTS3_tag { + uint8_t byte; + struct { + uint8_t TMR1IRQ: 1; + uint8_t TMR2IRQ: 1; + uint8_t TMR3IRQ: 1; + uint8_t TMR4IRQ: 1; + uint8_t TMR1MSK: 1; + uint8_t TMR2MSK: 1; + uint8_t TMR3MSK: 1; + uint8_t TMR4MSK: 1; + } bit; } regIRQSTS3_t; // PHY_CTRL1 bits @@ -382,17 +382,17 @@ typedef union regIRQSTS3_tag{ #define cPHY_CTRL1_AUTOACK (1<<3) #define cPHY_CTRL1_XCVSEQ (7<<0) -typedef union regPHY_CTRL1_tag{ - uint8_t byte; - struct{ - uint8_t XCVSEQ:3; - uint8_t AUTOACK:1; - uint8_t RXACKRQD:1; - uint8_t CCABFRTX:1; - uint8_t SLOTTED:1; - uint8_t TMRTRIGEN:1; - }bit; -} regPHY_CTRL1_t; +typedef union regPHY_CTRL1_tag { + uint8_t byte; + struct { + uint8_t XCVSEQ: 3; + uint8_t AUTOACK: 1; + uint8_t RXACKRQD: 1; + uint8_t CCABFRTX: 1; + uint8_t SLOTTED: 1; + uint8_t TMRTRIGEN: 1; + } bit; +} regPHY_CTRL1_t; // PHY_CTRL2 bits #define cPHY_CTRL2_CRC_MSK (1<<7) @@ -404,19 +404,19 @@ typedef union regPHY_CTRL1_tag{ #define cPHY_CTRL2_TXMSK (1<<1) #define cPHY_CTRL2_SEQMSK (1<<0) -typedef union regPHY_CTRL2_tag{ - uint8_t byte; - struct{ - uint8_t SEQMSK:1; - uint8_t TXMSK:1; - uint8_t RXMSK:1; - uint8_t CCAMSK:1; - uint8_t RX_WMRK_MSK:1; - uint8_t FILTERFAIL_MSK:1; - uint8_t PLL_UNLOCK_MSK:1; - uint8_t CRC_MSK:1; - }bit; -} regPHY_CTRL2_t; +typedef union regPHY_CTRL2_tag { + uint8_t byte; + struct { + uint8_t SEQMSK: 1; + uint8_t TXMSK: 1; + uint8_t RXMSK: 1; + uint8_t CCAMSK: 1; + uint8_t RX_WMRK_MSK: 1; + uint8_t FILTERFAIL_MSK: 1; + uint8_t PLL_UNLOCK_MSK: 1; + uint8_t CRC_MSK: 1; + } bit; +} regPHY_CTRL2_t; // PHY_CTRL3 bits #define cPHY_CTRL3_TMR4CMP_EN (1<<7) @@ -427,18 +427,18 @@ typedef union regPHY_CTRL2_tag{ #define cPHY_CTRL3_PB_ERR_MSK (1<<1) #define cPHY_CTRL3_WAKE_MSK (1<<0) -typedef union regPHY_CTRL3_tag{ - uint8_t byte; - struct{ - uint8_t WAKE_MSK:1; - uint8_t PB_ERR_MSK:1; - uint8_t ASM_MSK:1; - uint8_t RESERVED:1; - uint8_t TMR1CMP_EN:1; - uint8_t TMR2CMP_EN:1; - uint8_t TMR3CMP_EN:1; - uint8_t TMR4CMP_EN:1; - }bit; +typedef union regPHY_CTRL3_tag { + uint8_t byte; + struct { + uint8_t WAKE_MSK: 1; + uint8_t PB_ERR_MSK: 1; + uint8_t ASM_MSK: 1; + uint8_t RESERVED: 1; + uint8_t TMR1CMP_EN: 1; + uint8_t TMR2CMP_EN: 1; + uint8_t TMR3CMP_EN: 1; + uint8_t TMR4CMP_EN: 1; + } bit; } regPHY_CTRL3_t; // RX_FRM_LEN bits @@ -454,17 +454,17 @@ typedef union regPHY_CTRL3_tag{ #define cPHY_CTRL4_PROMISCUOUS (1<<1) #define cPHY_CTRL4_TC2PRIME_EN (1<<0) -typedef union regPHY_CTRL4_tag{ - uint8_t byte; - struct{ - uint8_t TC2PRIME_EN:1; - uint8_t PROMISCUOUS:1; - uint8_t TMRLOAD:1; - uint8_t CCATYPE:2; - uint8_t PANCORDNTR0:1; - uint8_t TC3TMOUT:1; - uint8_t TRCV_MSK:1; - }bit; +typedef union regPHY_CTRL4_tag { + uint8_t byte; + struct { + uint8_t TC2PRIME_EN: 1; + uint8_t PROMISCUOUS: 1; + uint8_t TMRLOAD: 1; + uint8_t CCATYPE: 2; + uint8_t PANCORDNTR0: 1; + uint8_t TC3TMOUT: 1; + uint8_t TRCV_MSK: 1; + } bit; } regPHY_CTRL4_t; // SRC_CTRL bits @@ -475,15 +475,15 @@ typedef union regPHY_CTRL4_tag{ #define cSRC_CTRL_INDEX_EN (1<<1) #define cSRC_CTRL_INDEX_DISABLE (1<<0) -typedef union regSRC_CTRL_tag{ - uint8_t byte; - struct{ - uint8_t INDEX_DISABLE:1; - uint8_t INDEX_EN:1; - uint8_t SRCADDR_EN:1; - uint8_t ACK_FRM_PND:1; - uint8_t INDEX:4; - }bit; +typedef union regSRC_CTRL_tag { + uint8_t byte; + struct { + uint8_t INDEX_DISABLE: 1; + uint8_t INDEX_EN: 1; + uint8_t SRCADDR_EN: 1; + uint8_t ACK_FRM_PND: 1; + uint8_t INDEX: 4; + } bit; } regSRC_CTRL_t; // ASM_CTRL1 bits @@ -525,18 +525,18 @@ typedef union regSRC_CTRL_tag{ #define cRX_FRAME_FLT_DATA_FT (1<<1) #define cRX_FRAME_FLT_BEACON_FT (1<<0) -typedef union regRX_FRAME_FILTER_tag{ - uint8_t byte; - struct{ - uint8_t FRAME_FLT_BEACON_FT:1; - uint8_t FRAME_FLT_DATA_FT:1; - uint8_t FRAME_FLT_ACK_FT:1; - uint8_t FRAME_FLT_CMD_FT:1; - uint8_t FRAME_FLT_NS_FT:1; - uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1; - uint8_t FRAME_FLT_FRM_VER:2; - }bit; -} regRX_FRAME_FILTER_t; +typedef union regRX_FRAME_FILTER_tag { + uint8_t byte; + struct { + uint8_t FRAME_FLT_BEACON_FT: 1; + uint8_t FRAME_FLT_DATA_FT: 1; + uint8_t FRAME_FLT_ACK_FT: 1; + uint8_t FRAME_FLT_CMD_FT: 1; + uint8_t FRAME_FLT_NS_FT: 1; + uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS: 1; + uint8_t FRAME_FLT_FRM_VER: 2; + } bit; +} regRX_FRAME_FILTER_t; // DUAL_PAN_CTRL bits #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0) diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp index b882d7a3f80..544808845d4 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp @@ -60,40 +60,38 @@ extern "C" { #define gXcvrRunState_d gXcvrPwrAutodoze_c #if !defined(TARGET_KW24D) - #define gXcvrLowPowerState_d gXcvrPwrHibernate_c +#define gXcvrLowPowerState_d gXcvrPwrHibernate_c #else - #define gXcvrLowPowerState_d gXcvrPwrAutodoze_c +#define gXcvrLowPowerState_d gXcvrPwrAutodoze_c #endif /* MCR20A XCVR states */ -typedef enum xcvrState_tag{ - gIdle_c, - gRX_c, - gTX_c, - gCCA_c, - gTR_c, - gCCCA_c, -}xcvrState_t; +typedef enum xcvrState_tag { + gIdle_c, + gRX_c, + gTX_c, + gCCA_c, + gTR_c, + gCCCA_c, +} xcvrState_t; /* MCR20A XCVR low power states */ -typedef enum xcvrPwrMode_tag{ +typedef enum xcvrPwrMode_tag { gXcvrPwrIdle_c, gXcvrPwrAutodoze_c, gXcvrPwrDoze_c, gXcvrPwrHibernate_c -}xcvrPwrMode_t; +} xcvrPwrMode_t; /*RF Part Type*/ -typedef enum -{ +typedef enum { FREESCALE_UNKNOW_DEV = 0, FREESCALE_MCR20A -}rf_trx_part_e; +} rf_trx_part_e; /*Atmel RF states*/ -typedef enum -{ +typedef enum { NOP = 0x00, BUSY_RX = 0x01, RF_TX_START = 0x02, @@ -106,7 +104,7 @@ typedef enum SLEEP = 0x0F, RX_AACK_ON = 0x16, TX_ARET_ON = 0x19 -}rf_trx_states_t; +} rf_trx_states_t; /*RF receive buffer*/ static uint8_t rf_buffer[RF_BUFFER_SIZE]; @@ -143,8 +141,8 @@ static const uint16_t pll_frac[16] = {0x2800, 0x5000, 0x7800, 0xA000, 0xC800, 0x static const phy_rf_channel_configuration_s phy_24ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK}; static const phy_device_channel_page_s phy_channel_pages[] = { - { CHANNEL_PAGE_0, &phy_24ghz}, - { CHANNEL_PAGE_0, NULL} + { CHANNEL_PAGE_0, &phy_24ghz}, + { CHANNEL_PAGE_0, NULL} }; @@ -162,7 +160,7 @@ MBED_UNUSED static void rf_init(void); MBED_UNUSED static void rf_set_mac_address(const uint8_t *ptr); MBED_UNUSED static int8_t rf_device_register(void); MBED_UNUSED static void rf_device_unregister(void); -MBED_UNUSED static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol ); +MBED_UNUSED static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol); MBED_UNUSED static void rf_cca_abort(void); MBED_UNUSED static void rf_read_mac_address(uint8_t *ptr); MBED_UNUSED static int8_t rf_read_random(void); @@ -203,8 +201,8 @@ MBED_UNUSED static uint8_t rf_get_channel_energy(void); MBED_UNUSED static uint8_t rf_convert_energy_level(uint8_t energyLevel); MBED_UNUSED static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi); MBED_UNUSED static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel); -MBED_UNUSED static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr); -MBED_UNUSED static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr); +MBED_UNUSED static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr); +MBED_UNUSED static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr); static void PHY_InterruptThread(void); static void handle_interrupt(void); @@ -237,11 +235,10 @@ static int8_t rf_device_register(void) radio_type = rf_radio_type_read(); - if(radio_type == FREESCALE_MCR20A) - { + if (radio_type == FREESCALE_MCR20A) { /*Set pointer to MAC address*/ device_driver.PHY_MAC = MAC_address; - device_driver.driver_description = (char*)"FREESCALE_MAC"; + device_driver.driver_description = (char *)"FREESCALE_MAC"; //Create setup Used Radio chips /*Type of RF PHY is SubGHz*/ @@ -427,7 +424,7 @@ static uint16_t rf_get_phy_mtu_size(void) * * \return none */ -static void rf_set_short_adr(uint8_t * short_address) +static void rf_set_short_adr(uint8_t *short_address) { /* Write one register at a time to be accessible from hibernate mode */ MCR20Drv_IndirectAccessSPIWrite(MACSHORTADDRS0_MSB, short_address[0]); @@ -501,9 +498,9 @@ static void rf_init(void) /* Disable Tristate on MISO for SPI reads */ MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02); /* Set XCVR clock output settings */ - #if !defined(TARGET_KW24D) - MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d); - #endif +#if !defined(TARGET_KW24D) + MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d); +#endif /* Set default XCVR power state */ rf_set_power_state(gXcvrRunState_d); @@ -547,13 +544,15 @@ static void rf_init(void) MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, (cRX_FRAME_FLT_FRM_VER | \ cRX_FRAME_FLT_BEACON_FT | \ cRX_FRAME_FLT_DATA_FT | \ - cRX_FRAME_FLT_CMD_FT )); + cRX_FRAME_FLT_CMD_FT)); /* Direct register overwrites */ - for (index = 0; index < sizeof(overwrites_direct)/sizeof(overwrites_t); index++) + for (index = 0; index < sizeof(overwrites_direct) / sizeof(overwrites_t); index++) { MCR20Drv_DirectAccessSPIWrite(overwrites_direct[index].address, overwrites_direct[index].data); + } /* Indirect register overwrites */ - for (index = 0; index < sizeof(overwrites_indirect)/sizeof(overwrites_t); index++) + for (index = 0; index < sizeof(overwrites_indirect) / sizeof(overwrites_t); index++) { MCR20Drv_IndirectAccessSPIWrite(overwrites_indirect[index].address, overwrites_indirect[index].data); + } /* Set the CCA energy threshold value */ MCR20Drv_IndirectAccessSPIWrite(CCA1_THRESH, RF_CCA_THRESHOLD); @@ -608,22 +607,19 @@ static void rf_poll_trx_state_change(rf_trx_states_t trx_state) * \return 0 Success * \return -1 Busy */ -static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol ) +static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol) { uint8_t ccaMode; /* Parameter validation */ - if( !data_ptr || (data_length > 125) || (PHY_LAYER_PAYLOAD != data_protocol) ) - { + if (!data_ptr || (data_length > 125) || (PHY_LAYER_PAYLOAD != data_protocol)) { return -1; } - if( mPhySeqState == gRX_c ) - { + if (mPhySeqState == gRX_c) { uint8_t phyReg = MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F; /* Check for an Rx in progress. */ - if((phyReg <= 0x06) || (phyReg == 0x15) || (phyReg == 0x16)) - { + if ((phyReg <= 0x06) || (phyReg == 0x15) || (phyReg == 0x16)) { if (device_driver.phy_tx_done_cb) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1); } @@ -633,8 +629,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h } /*Check if transmitter is busy*/ - if( mPhySeqState != gIdle_c ) - { + if (mPhySeqState != gIdle_c) { /*Return busy*/ return -1; } @@ -649,12 +644,11 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h /* Load data into XCVR */ tx_len = data_length + 2; MCR20Drv_PB_SPIBurstWrite(data_ptr - 1, data_length + 1); - MCR20Drv_PB_SPIByteWrite(0,tx_len); + MCR20Drv_PB_SPIByteWrite(0, tx_len); /* Set CCA mode 1 */ ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE; - if( ccaMode != gCcaCCA_MODE1_c ) - { + if (ccaMode != gCcaCCA_MODE1_c) { mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c); mStatusAndControlRegs[PHY_CTRL4] |= gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c; MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]); @@ -704,13 +698,10 @@ static void rf_cca_abort(void) static void rf_start_tx(void) { /* Perform TxRxAck sequence if required by phyTxMode */ - if( need_ack ) - { + if (need_ack) { mStatusAndControlRegs[PHY_CTRL1] |= cPHY_CTRL1_RXACKRQD; mPhySeqState = gTR_c; - } - else - { + } else { mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_RXACKRQD); mPhySeqState = gTX_c; } @@ -724,8 +715,7 @@ static void rf_start_tx(void) /* Start the sequence immediately */ MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, &mStatusAndControlRegs[PHY_CTRL1], 2); - if( need_ack ) - { + if (need_ack) { rf_ack_wait_timer_start(gPhyWarmUpTime_c + gPhySHRDuration_c + tx_len * gPhySymbolsPerOctet_c + gPhyAckWaitDuration_c); } } @@ -742,8 +732,7 @@ static void rf_receive(void) uint8_t phyRegs[5]; /* RX can start only from Idle state */ - if( mPhySeqState != gIdle_c ) - { + if (mPhySeqState != gIdle_c) { return; } @@ -804,8 +793,7 @@ static void rf_handle_rx_end(void) rf_receive(); /*Check the length is valid*/ - if(len > 1 && len < RF_BUFFER_SIZE) - { + if (len > 1 && len < RF_BUFFER_SIZE) { rf_lqi = rf_convert_LQI(rf_lqi); rf_rssi = rf_convert_LQI_to_RSSI(rf_lqi); /*gcararu: Scale LQI using received RSSI, to match the LQI reported by the ATMEL radio */ @@ -851,20 +839,14 @@ static void rf_handle_tx_end(void) } /*Call PHY TX Done API*/ - if( need_ack ) - { - if( rx_frame_pending ) - { + if (need_ack) { + if (rx_frame_pending) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE_PENDING, 1, 1); - } - else - { + } else { // arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1); device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE, 1, 1); } - } - else - { + } else { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1); } } @@ -879,12 +861,9 @@ static void rf_handle_tx_end(void) static void rf_handle_cca_ed_done(void) { /*Check the result of CCA process*/ - if( !(mStatusAndControlRegs[IRQSTS2] & cIRQSTS2_CCA) ) - { + if (!(mStatusAndControlRegs[IRQSTS2] & cIRQSTS2_CCA)) { rf_start_tx(); - } - else if (device_driver.phy_tx_done_cb) - { + } else if (device_driver.phy_tx_done_cb) { /*Send CCA fail notification*/ device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1); } @@ -901,10 +880,9 @@ static void rf_handle_cca_ed_done(void) static int8_t rf_tx_power_set(uint8_t power) { /* gcapraru: Map MCR20A Tx power levels over ATMEL values */ - static uint8_t pwrLevelMapping[16] = {25,25,25,24,24,24,23,23,22,22,21,20,19,18,17,14}; + static uint8_t pwrLevelMapping[16] = {25, 25, 25, 24, 24, 24, 23, 23, 22, 22, 21, 20, 19, 18, 17, 14}; - if( power > 15 ) - { + if (power > 15) { return -1; } @@ -958,8 +936,7 @@ static int8_t rf_enable_antenna_diversity(void) static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel) { int8_t ret_val = 0; - switch (new_state) - { + switch (new_state) { /*Reset PHY driver and set to idle*/ case PHY_INTERFACE_RESET: break; @@ -996,19 +973,14 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_ */ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr) { - switch (extension_type) - { + switch (extension_type) { /*Control MAC pending bit for Indirect data transmission*/ - case PHY_EXTENSION_CTRL_PENDING_BIT: - { + case PHY_EXTENSION_CTRL_PENDING_BIT: { uint8_t reg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL); - if(*data_ptr) - { + if (*data_ptr) { reg |= cSRC_CTRL_ACK_FRM_PND; - } - else - { + } else { reg &= ~cSRC_CTRL_ACK_FRM_PND; } @@ -1055,12 +1027,11 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr) { int8_t ret_val = 0; - switch (address_type) - { + switch (address_type) { /*Set 48-bit address*/ case PHY_MAC_48BIT: break; - /*Set 64-bit address*/ + /*Set 64-bit address*/ case PHY_MAC_64BIT: rf_set_address(address_ptr); break; @@ -1120,11 +1091,9 @@ static void handle_interrupt(void) xcvseqCopy = mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ; /* Flter Fail IRQ */ - if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_FILTERFAIL_IRQ) && - !(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_FILTERFAIL_MSK) ) - { - if( xcvseqCopy == gRX_c ) - { + if ((mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_FILTERFAIL_IRQ) && + !(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_FILTERFAIL_MSK)) { + if (xcvseqCopy == gRX_c) { /* Abort current SEQ */ mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ); MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]); @@ -1139,17 +1108,15 @@ static void handle_interrupt(void) } /* TMR3 IRQ: ACK wait time-out */ - if( (mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3IRQ) && - !(mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3MSK) ) - { + if ((mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3IRQ) && + !(mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3MSK)) { /* Disable TMR3 IRQ */ mStatusAndControlRegs[IRQSTS3] |= cIRQSTS3_TMR3MSK; - if( xcvseqCopy == gTR_c ) - { + if (xcvseqCopy == gTR_c) { /* Set XCVR to Idle */ mPhySeqState = gIdle_c; - mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ ); + mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ); /* Mask interrupts */ mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_CCAMSK | cPHY_CTRL2_RXMSK | cPHY_CTRL2_TXMSK | cPHY_CTRL2_SEQMSK; /* Sync settings with XCVR */ @@ -1161,44 +1128,40 @@ static void handle_interrupt(void) } /* Sequencer interrupt, the autosequence has completed */ - if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_SEQIRQ) && - !(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_SEQMSK) ) - { + if ((mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_SEQIRQ) && + !(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_SEQMSK)) { /* Set XCVR to Idle */ mPhySeqState = gIdle_c; - mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ ); + mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ); /* Mask interrupts */ mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_CCAMSK | cPHY_CTRL2_RXMSK | cPHY_CTRL2_TXMSK | cPHY_CTRL2_SEQMSK; /* Sync settings with XCVR */ MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5); /* PLL unlock, the autosequence has been aborted due to PLL unlock */ - if( mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_PLL_UNLOCK_IRQ ) - { - if(xcvseqCopy == gRX_c) - { + if (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_PLL_UNLOCK_IRQ) { + if (xcvseqCopy == gRX_c) { rf_receive(); } return; } - switch(xcvseqCopy) - { - case gTX_c: - case gTR_c: - rf_handle_tx_end(); - break; + switch (xcvseqCopy) { + case gTX_c: + case gTR_c: + rf_handle_tx_end(); + break; - case gRX_c: - rf_handle_rx_end(); - break; + case gRX_c: + rf_handle_rx_end(); + break; - case gCCA_c: - rf_handle_cca_ed_done(); - break; + case gCCA_c: + rf_handle_cca_ed_done(); + break; - default: - break; + default: + break; } return; @@ -1227,8 +1190,7 @@ static void rf_abort(void) mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_SEQMSK; MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, mStatusAndControlRegs[PHY_CTRL2]); - if( (mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c ) - { + if ((mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c) { /* Abort current SEQ */ mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ); MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]); @@ -1258,8 +1220,7 @@ static void rf_abort(void) */ static void rf_get_timestamp(uint32_t *pRetClk) { - if(NULL == pRetClk) - { + if (NULL == pRetClk) { return; } @@ -1282,8 +1243,7 @@ static void rf_set_timeout(uint32_t *pEndTime) { uint8_t phyReg; - if(NULL == pEndTime) - { + if (NULL == pEndTime) { return; } @@ -1318,12 +1278,11 @@ static uint8_t rf_if_read_rnd(void) /* Check if XCVR is idle */ phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1); - if( (phyReg & cPHY_CTRL1_XCVSEQ) == gIdle_c ) - { + if ((phyReg & cPHY_CTRL1_XCVSEQ) == gIdle_c) { /* Program a new sequence */ MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyReg | gCCA_c); /* Wait for sequence to finish */ - while( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ) ); + while (!(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ)); /* Clear interrupt flag */ MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_SEQIRQ); } @@ -1342,7 +1301,7 @@ static uint8_t rf_if_read_rnd(void) */ static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi) { - int32_t rssi = (50*lqi - 16820) / 163; + int32_t rssi = (50 * lqi - 16820) / 163; return (int8_t)rssi; } @@ -1358,20 +1317,15 @@ static uint8_t rf_convert_LQI(uint8_t hwLqi) uint32_t tmpLQI; /* LQI Saturation Level */ - if (hwLqi >= 230) - { + if (hwLqi >= 230) { return 0xFF; - } - else if (hwLqi <= 9) - { + } else if (hwLqi <= 9) { return 0; - } - else - { + } else { /* Rescale the LQI values from min to saturation to the 0x00 - 0xFF range */ /* The LQI value mst be multiplied by ~1.1087 */ /* tmpLQI = hwLqi * 7123 ~= hwLqi * 65536 * 0.1087 = hwLqi * 2^16 * 0.1087*/ - tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123 ); + tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123); /* tmpLQI = (tmpLQI / 2^16) + hwLqi */ tmpLQI = (uint32_t)(tmpLQI >> 16) + (uint32_t)hwLqi; @@ -1393,16 +1347,13 @@ static void rf_promiscuous(uint8_t state) rxFrameFltReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER); phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4); - if( state ) - { + if (state) { /* FRM_VER[1:0] = b00. 00: Any FrameVersion accepted (0,1,2 & 3) */ /* All frame types accepted*/ phyCtrl4Reg |= cPHY_CTRL4_PROMISCUOUS; rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER); - rxFrameFltReg |= (cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT); - } - else - { + rxFrameFltReg |= (cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT); + } else { phyCtrl4Reg &= ~cPHY_CTRL4_PROMISCUOUS; /* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others */ /* Beacon, Data and MAC command frame types accepted */ @@ -1427,8 +1378,7 @@ static void rf_set_power_state(xcvrPwrMode_t newState) uint8_t pwrMode; uint8_t xtalState; - if( mPwrState == newState ) - { + if (mPwrState == newState) { return; } @@ -1436,35 +1386,33 @@ static void rf_set_power_state(xcvrPwrMode_t newState) pwrMode = MCR20Drv_DirectAccessSPIRead(PWR_MODES); xtalState = pwrMode & cPWR_MODES_XTALEN; - switch( newState ) - { - case gXcvrPwrIdle_c: - pwrMode &= ~(cPWR_MODES_AUTODOZE); - pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_PMC_MODE); - break; - case gXcvrPwrAutodoze_c: - pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE); - break; - case gXcvrPwrDoze_c: - pwrMode &= ~(cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE); - pwrMode |= cPWR_MODES_XTALEN; - break; - case gXcvrPwrHibernate_c: - pwrMode &= ~(cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE); - break; - default: - return; + switch (newState) { + case gXcvrPwrIdle_c: + pwrMode &= ~(cPWR_MODES_AUTODOZE); + pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_PMC_MODE); + break; + case gXcvrPwrAutodoze_c: + pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE); + break; + case gXcvrPwrDoze_c: + pwrMode &= ~(cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE); + pwrMode |= cPWR_MODES_XTALEN; + break; + case gXcvrPwrHibernate_c: + pwrMode &= ~(cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE); + break; + default: + return; } mPwrState = newState; MCR20Drv_DirectAccessSPIWrite(PWR_MODES, pwrMode); - if( !xtalState && (pwrMode & cPWR_MODES_XTALEN)) - { + if (!xtalState && (pwrMode & cPWR_MODES_XTALEN)) { /* wait for crystal oscillator to complet its warmup */ - while( ( MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY ) != cPWR_MODES_XTAL_READY); + while ((MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY) != cPWR_MODES_XTAL_READY); /* wait for radio wakeup from hibernate interrupt */ - while( ( MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) ) != (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) ); + while ((MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS)) != (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS)); MCR20Drv_DirectAccessSPIWrite(IRQSTS2, cIRQSTS2_WAKE_IRQ); } @@ -1481,8 +1429,7 @@ static uint8_t rf_get_channel_energy(void) MCR20Drv_IRQ_Disable(); /* RX can start only from Idle state */ - if( mPhySeqState != gIdle_c ) - { + if (mPhySeqState != gIdle_c) { MCR20Drv_IRQ_Enable(); return 0; } @@ -1492,8 +1439,7 @@ static uint8_t rf_get_channel_energy(void) /* Switch to ED mode */ ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE; - if( ccaMode != gCcaED_c ) - { + if (ccaMode != gCcaED_c) { mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c); mStatusAndControlRegs[PHY_CTRL4] |= gCcaED_c << cPHY_CTRL4_CCATYPE_Shift_c; MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]); @@ -1504,7 +1450,7 @@ static uint8_t rf_get_channel_energy(void) MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_CCAIRQ | cIRQSTS1_SEQIRQ); MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]); /* Wait for sequence to finish */ - while ( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ)); + while (!(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ)); /* Set XCVR to Idle */ mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ); MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]); @@ -1524,18 +1470,13 @@ static uint8_t rf_get_channel_energy(void) */ static uint8_t rf_convert_energy_level(uint8_t energyLevel) { - if(energyLevel >= 90) - { + if (energyLevel >= 90) { /* ED value is below minimum. Return 0x00. */ energyLevel = 0x00; - } - else if(energyLevel <= 26) - { + } else if (energyLevel <= 26) { /* ED value is above maximum. Return 0xFF. */ energyLevel = 0xFF; - } - else - { + } else { /* Energy level (-90 dBm to -26 dBm ) --> varies form 0 to 64 */ energyLevel = (90 - energyLevel); /* Rescale the energy level values to the 0x00-0xff range (0 to 64 translates in 0 to 255) */ @@ -1555,43 +1496,53 @@ static uint8_t rf_scale_lqi(int8_t rssi) const int8_t rf_sensitivity = -98; /*rssi < RF sensitivity*/ - if(rssi < rf_sensitivity) - scaled_lqi=0; + if (rssi < rf_sensitivity) { + scaled_lqi = 0; + } /*-91 dBm < rssi < -81 dBm (AT86RF233 XPro)*/ /*-90 dBm < rssi < -80 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 10)) - scaled_lqi=31; + else if (rssi < (rf_sensitivity + 10)) { + scaled_lqi = 31; + } /*-81 dBm < rssi < -71 dBm (AT86RF233 XPro)*/ /*-80 dBm < rssi < -70 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 20)) - scaled_lqi=207; + else if (rssi < (rf_sensitivity + 20)) { + scaled_lqi = 207; + } /*-71 dBm < rssi < -61 dBm (AT86RF233 XPro)*/ /*-70 dBm < rssi < -60 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 30)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 30)) { + scaled_lqi = 255; + } /*-61 dBm < rssi < -51 dBm (AT86RF233 XPro)*/ /*-60 dBm < rssi < -50 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 40)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 40)) { + scaled_lqi = 255; + } /*-51 dBm < rssi < -41 dBm (AT86RF233 XPro)*/ /*-50 dBm < rssi < -40 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 50)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 50)) { + scaled_lqi = 255; + } /*-41 dBm < rssi < -31 dBm (AT86RF233 XPro)*/ /*-40 dBm < rssi < -30 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 60)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 60)) { + scaled_lqi = 255; + } /*-31 dBm < rssi < -21 dBm (AT86RF233 XPro)*/ /*-30 dBm < rssi < -20 dBm (AT86RF212B XPro)*/ - else if(rssi < (rf_sensitivity + 70)) - scaled_lqi=255; + else if (rssi < (rf_sensitivity + 70)) { + scaled_lqi = 255; + } /*rssi > RF saturation*/ - else if(rssi > (rf_sensitivity + 80)) - scaled_lqi=111; + else if (rssi > (rf_sensitivity + 80)) { + scaled_lqi = 111; + } /*-21 dBm < rssi < -11 dBm (AT86RF233 XPro)*/ /*-20 dBm < rssi < -10 dBm (AT86RF212B XPro)*/ - else - scaled_lqi=255; + else { + scaled_lqi = 255; + } return scaled_lqi; } @@ -1605,28 +1556,33 @@ extern "C" void xcvr_spi_init(uint32_t instance) (void)instance; } -extern "C" void RF_IRQ_Init(void) { +extern "C" void RF_IRQ_Init(void) +{ MBED_ASSERT(irq != NULL); irq->mode(PullUp); irq->fall(&PHY_InterruptHandler); } -extern "C" void RF_IRQ_Enable(void) { +extern "C" void RF_IRQ_Enable(void) +{ MBED_ASSERT(irq != NULL); irq->enable_irq(); } -extern "C" void RF_IRQ_Disable(void) { +extern "C" void RF_IRQ_Disable(void) +{ MBED_ASSERT(irq != NULL); irq->disable_irq(); } -extern "C" uint8_t RF_isIRQ_Pending(void) { +extern "C" uint8_t RF_isIRQ_Pending(void) +{ MBED_ASSERT(rf != NULL); return !irq_pin->read(); } -extern "C" void RF_RST_Set(int state) { +extern "C" void RF_RST_Set(int state) +{ MBED_ASSERT(rst != NULL); *rst = state; } @@ -1651,36 +1607,33 @@ extern "C" void xcvr_spi_configure_speed(uint32_t instance, uint32_t freq) } extern "C" void xcvr_spi_transfer(uint32_t instance, - uint8_t * sendBuffer, - uint8_t * receiveBuffer, - size_t transferByteCount) + uint8_t *sendBuffer, + uint8_t *receiveBuffer, + size_t transferByteCount) { MBED_ASSERT(spi != NULL); (void)instance; volatile uint8_t dummy; - if( !transferByteCount ) + if (!transferByteCount) { return; + } - if( !sendBuffer && !receiveBuffer ) + if (!sendBuffer && !receiveBuffer) { return; + } - while( transferByteCount-- ) - { - if( sendBuffer ) - { + while (transferByteCount--) { + if (sendBuffer) { dummy = *sendBuffer; sendBuffer++; - } - else - { + } else { dummy = 0xFF; } dummy = spi->write(dummy); - if( receiveBuffer ) - { + if (receiveBuffer) { *receiveBuffer = dummy; receiveBuffer++; } @@ -1701,7 +1654,7 @@ static void rf_if_unlock(void) } NanostackRfPhyMcr20a::NanostackRfPhyMcr20a(PinName spi_mosi, PinName spi_miso, - PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_irq) + PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_irq) : _spi(spi_mosi, spi_miso, spi_sclk), _rf_cs(spi_cs), _rf_rst(spi_rst, 1), _rf_irq(spi_irq), _rf_irq_pin(spi_irq), _irq_thread(osPriorityRealtime, 1024) @@ -1768,7 +1721,7 @@ void NanostackRfPhyMcr20a::get_mac_address(uint8_t *mac) { rf_if_lock(); - memcpy((void*)mac, (void*)MAC_address, sizeof(MAC_address)); + memcpy((void *)mac, (void *)MAC_address, sizeof(MAC_address)); rf_if_unlock(); } @@ -1782,7 +1735,7 @@ void NanostackRfPhyMcr20a::set_mac_address(uint8_t *mac) rf_if_unlock(); return; } - memcpy((void*)MAC_address, (void*)mac, sizeof(MAC_address)); + memcpy((void *)MAC_address, (void *)mac, sizeof(MAC_address)); rf_if_unlock(); } diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h b/components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h index ca56cae6cae..9f1a1f71be5 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h @@ -42,7 +42,7 @@ * files, so use this section only if there is no other better solution. * *---------------------------------------------------------------------------* *****************************************************************************/ - + /***************************************************************************** * PUBLIC MACROS * @@ -78,10 +78,10 @@ void gXcvrDeassertCS_d(void); void xcvr_spi_init(uint32_t instance); void xcvr_spi_configure_speed(uint32_t instance, uint32_t freq); void xcvr_spi_transfer(uint32_t instance, - uint8_t * sendBuffer, - uint8_t * receiveBuffer, - uint32_t transferByteCount); - + uint8_t *sendBuffer, + uint8_t *receiveBuffer, + uint32_t transferByteCount); + #if defined(__cplusplus) } #endif /* __cplusplus */ From d82990cd25fefa7e3c70a495134308175e215ba9 Mon Sep 17 00:00:00 2001 From: RFulchiero Date: Tue, 21 Aug 2018 11:09:03 -0500 Subject: [PATCH 05/10] Low power timer needs to be reset when setting time. Reset _rtc_lp_timer only if DEVICE_LPTICKER is defined. --- platform/mbed_rtc_time.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/mbed_rtc_time.cpp b/platform/mbed_rtc_time.cpp index fbc8db2b1ba..7ec6171b4d7 100644 --- a/platform/mbed_rtc_time.cpp +++ b/platform/mbed_rtc_time.cpp @@ -57,6 +57,7 @@ static time_t _rtc_lpticker_read(void) static void _rtc_lpticker_write(time_t t) { + _rtc_lp_timer->reset(); _rtc_lp_base = t; } From 0de5ab26861f2e1f358762539a56eb59616e8292 Mon Sep 17 00:00:00 2001 From: RFulchiero Date: Tue, 11 Sep 2018 17:27:19 -0500 Subject: [PATCH 06/10] Add a protected HAL set_time() test When DEVICE_LPTICKER is defined set_time() only works correctly on the first call. This test calls set_time() twice and ensures the time set by both calls is correct. This test only runs if DEVICE_RTC or DEVICE_LPTICKER is defined. --- TESTS/mbed_hal/rtc_time/main.cpp | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/TESTS/mbed_hal/rtc_time/main.cpp b/TESTS/mbed_hal/rtc_time/main.cpp index 857d033cd84..c537b02fc65 100644 --- a/TESTS/mbed_hal/rtc_time/main.cpp +++ b/TESTS/mbed_hal/rtc_time/main.cpp @@ -169,6 +169,31 @@ void test_local_time_invalid_param() TEST_ASSERT_EQUAL(false, _rtc_localtime(1, NULL, RTC_4_YEAR_LEAP_YEAR_SUPPORT)); } +/* Test set_time() function called a few seconds apart. + * + * Given is set_time() function. + * When set_time() is used to set the system time two times. + * Then if the value returned from time() is always correct return true, otherwise return false. + */ +#define NEW_TIME 15 +void test_set_time_twice() +{ + time_t current_time; + + /* Set the time to NEW_TIME and check it */ + set_time(NEW_TIME); + current_time = time(NULL); + TEST_ASSERT_EQUAL (true, (current_time == NEW_TIME)); + + /* Wait 2 seconds */ + wait_ms(2000); + + /* set the time to NEW_TIME again and check it */ + set_time(NEW_TIME); + current_time = time(NULL); + TEST_ASSERT_EQUAL (true, (current_time == NEW_TIME)); +} + Case cases[] = { Case("test is leap year - RTC leap years full support", test_is_leap_year), Case("test is leap year - RTC leap years partial support", test_is_leap_year), @@ -176,6 +201,9 @@ Case cases[] = { Case("test make time boundary values - RTC leap years partial support", test_mk_time_boundary), Case("test make time - invalid param", test_mk_time_invalid_param), Case("test local time - invalid param", test_local_time_invalid_param), +#if DEVICE_RTC || DEVICE_LPTICKER + Case("test set_time twice", test_set_time_twice), +#endif }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) From c0647267ccc9bedbef5527a1c76b7234be9c7b4c Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Tue, 6 Nov 2018 16:45:09 +0200 Subject: [PATCH 07/10] Sync with Atmel RF driver v3.0.6 --- components/802.15.4_RF/atmel-rf-driver/mbed_lib.json | 4 ++++ .../atmel-rf-driver/source/NanostackRfPhyAtmel.cpp | 8 +------- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/components/802.15.4_RF/atmel-rf-driver/mbed_lib.json b/components/802.15.4_RF/atmel-rf-driver/mbed_lib.json index 9d8424f2d56..e44a0dc527f 100644 --- a/components/802.15.4_RF/atmel-rf-driver/mbed_lib.json +++ b/components/802.15.4_RF/atmel-rf-driver/mbed_lib.json @@ -24,6 +24,10 @@ "provide-default": { "help": "Provide default NanostackRfpy. [true/false]", "value": false + }, + "irq-thread-stack-size": { + "help": "The stack size of the Thread serving the Atmel RF interrupts", + "value": 1024 } }, "target_overrides": { diff --git a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp index 7fec78f6e73..89652958bb1 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp +++ b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp @@ -270,7 +270,7 @@ RFBits::RFBits(PinName spi_mosi, PinName spi_miso, SLP_TR(spi_slp), IRQ(spi_irq) #ifdef MBED_CONF_RTOS_PRESENT - , irq_thread(osPriorityRealtime, 1024) + , irq_thread(osPriorityRealtime, MBED_CONF_ATMEL_RF_IRQ_THREAD_STACK_SIZE, NULL, "atmel_irq_thread") #endif { #ifdef MBED_CONF_RTOS_PRESENT @@ -1071,13 +1071,10 @@ static void rf_if_irq_task_process_irq(void) static void rf_if_interrupt_handler(void) #endif { - static uint8_t last_is, last_ts; uint8_t irq_status, full_trx_status; - uint8_t orig_xah_ctrl_1 = xah_ctrl_1; /*Read and clear interrupt flag, and pick up trx_status*/ irq_status = rf_if_read_register_with_status(IRQ_STATUS, &full_trx_status); - uint8_t orig_flags = rf_flags; /*Frame end interrupt (RX and TX)*/ if (irq_status & TRX_END) { @@ -1098,8 +1095,6 @@ static void rf_if_interrupt_handler(void) // Here some counter could be used to monitor the underrun occurancy count. // Do not print anything here! } - last_is = irq_status; - last_ts = full_trx_status; } /* @@ -1635,7 +1630,6 @@ static bool rf_start_tx() rf_flags_clear(RFF_RX); // Check whether we saw any delay in the PLL_ON transition. if (poll_count > 0) { - tr_warning("PLL_ON delayed, retry count: %d", poll_count); // let's get back to the receiving state. rf_receive(state); return false; From d5df64299a05064b04049c2e999670793a8269ed Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Tue, 6 Nov 2018 16:51:35 +0200 Subject: [PATCH 08/10] Sync with MCR20a RF driver v1.0.3 --- .../mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp index 544808845d4..b2595401ba8 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp @@ -998,19 +998,11 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt } break; } - /*Set channel*/ - case PHY_EXTENSION_SET_CHANNEL: - break; /*Read energy on the channel*/ case PHY_EXTENSION_READ_CHANNEL_ENERGY: *data_ptr = rf_get_channel_energy(); break; - /*Read status of the link*/ - case PHY_EXTENSION_READ_LINK_STATUS: - break; - case PHY_EXTENSION_CONVERT_SIGNAL_INFO: - break; - case PHY_EXTENSION_ACCEPT_ANY_BEACON: + default: break; } return 0; From 9613e0ffbd3a1b3ed61aaa35087e01cc4a8476a5 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Thu, 25 Oct 2018 15:01:59 -0500 Subject: [PATCH 09/10] Increase background stack size to fix overflows On platforms using both tickless and the low power ticker wrapper so much of the background stack is used that it overflows. To ensure the background thread's stack doesn't overflow increase this size by 256 bytes when tickless is enabled. Worst case usage on the NUCLEO_F476RG was recorded at 656 when tickless is turned on so this increased size should safely prevent overflows. --- rtos/TARGET_CORTEX/mbed_rtx_conf.h | 10 ++++++++-- rtos/mbed_lib.json | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/rtos/TARGET_CORTEX/mbed_rtx_conf.h b/rtos/TARGET_CORTEX/mbed_rtx_conf.h index f0b2fc39849..8554098e240 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_conf.h +++ b/rtos/TARGET_CORTEX/mbed_rtx_conf.h @@ -39,10 +39,16 @@ #define OS_TIMER_THREAD_STACK_SIZE MBED_CONF_RTOS_TIMER_THREAD_STACK_SIZE #endif +// Increase the idle thread stack size when tickless is enabled +#if defined(MBED_TICKLESS) && defined(LPTICKER_DELAY_TICKS) && (LPTICKER_DELAY_TICKS > 0) +#define EXTRA_IDLE_STACK MBED_CONF_RTOS_IDLE_THREAD_STACK_SIZE_TICKLESS_EXTRA +#else +#define EXTRA_IDLE_STACK 0 +#endif #ifdef MBED_CONF_APP_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE MBED_CONF_APP_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE (MBED_CONF_APP_IDLE_THREAD_STACK_SIZE + EXTRA_IDLE_STACK) #else -#define OS_IDLE_THREAD_STACK_SIZE MBED_CONF_RTOS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE (MBED_CONF_RTOS_IDLE_THREAD_STACK_SIZE + EXTRA_IDLE_STACK) #endif #define OS_DYNAMIC_MEM_SIZE 0 diff --git a/rtos/mbed_lib.json b/rtos/mbed_lib.json index 561a36f9e40..76e5321c672 100644 --- a/rtos/mbed_lib.json +++ b/rtos/mbed_lib.json @@ -17,6 +17,10 @@ "thread-stack-size": { "help": "The default stack size of new threads", "value": 4096 + }, + "idle-thread-stack-size-tickless-extra": { + "help": "Additional size to add to the idle thread when tickless is enabled and LPTICKER_DELAY_TICKS is used", + "value": 256 } }, "macros": ["_RTE_"], From 542744d03c4289ab00bb3a49dbb98d44c5be1fff Mon Sep 17 00:00:00 2001 From: David Saada Date: Tue, 30 Oct 2018 14:26:12 +0200 Subject: [PATCH 10/10] Support erase value in Flash HAL drivers, FlashIAP and block devices --- TESTS/mbed_drivers/flashiap/main.cpp | 18 ++++++++++++++---- .../COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp | 14 ++++++++++++++ .../COMPONENT_FLASHIAP/FlashIAPBlockDevice.h | 6 ++++++ drivers/FlashIAP.cpp | 5 +++++ drivers/FlashIAP.h | 7 +++++++ .../flash_common_algo.c | 7 +++++++ hal/flash_api.h | 7 +++++++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c | 7 +++++++ .../TARGET_CM3DS_MPS2/flash_api.c | 7 +++++++ .../TARGET_Cypress/TARGET_PSOC6/flash_api.c | 7 +++++++ .../TARGET_MCUXpresso_MCUS/api/flash_api.c | 7 +++++++ .../TARGET_NRF5x/TARGET_NRF51/flash_api.c | 7 +++++++ .../TARGET_NRF5x/TARGET_NRF52/flash_api.c | 7 +++++++ .../TARGET_NUVOTON/TARGET_M2351/flash_api.c | 8 ++++++++ .../TARGET_LPC176X/device/flash_api.c | 7 +++++++ .../TARGET_LPC/flash_api.c | 7 +++++++ .../TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c | 8 ++++++++ .../TARGET_MCU_RTL8195A/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32F0/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32F1/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32F2/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32F3/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32F4/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32F7/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32L0/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32L1/flash_api.c | 7 +++++++ targets/TARGET_STM/TARGET_STM32L4/flash_api.c | 7 +++++++ .../TARGET_EFM32/flash_api.c | 12 ++++++++++++ .../TARGET_TOSHIBA/TARGET_TMPM46B/flash_api.c | 11 +++++++++++ .../TARGET_TOSHIBA/TARGET_TMPM4G9/flash_api.c | 7 +++++++ 30 files changed, 232 insertions(+), 4 deletions(-) diff --git a/TESTS/mbed_drivers/flashiap/main.cpp b/TESTS/mbed_drivers/flashiap/main.cpp index 6fecee4c79a..be46362d55f 100644 --- a/TESTS/mbed_drivers/flashiap/main.cpp +++ b/TESTS/mbed_drivers/flashiap/main.cpp @@ -55,9 +55,6 @@ void flashiap_program_test() TEST_ASSERT_TRUE(sector_size % page_size == 0); uint32_t prog_size = std::max(page_size, (uint32_t)8); uint8_t *data = new uint8_t[prog_size + 2]; - for (uint32_t i = 0; i < prog_size + 2; i++) { - data[i] = i; - } // the one before the last sector in the system uint32_t address = (flash_device.get_flash_start() + flash_device.get_flash_size()) - (sector_size); @@ -68,6 +65,20 @@ void flashiap_program_test() ret = flash_device.erase(address, sector_size); TEST_ASSERT_EQUAL_INT32(0, ret); + uint8_t erase_val = flash_device.get_erase_value(); + memset(data, erase_val, prog_size); + + uint8_t *data_flashed = new uint8_t[prog_size]; + for (uint32_t i = 0; i < sector_size / prog_size; i++) { + uint32_t page_addr = address + i * prog_size; + ret = flash_device.read(data_flashed, page_addr, prog_size); + TEST_ASSERT_EQUAL_INT32(0, ret); + TEST_ASSERT_EQUAL_UINT8_ARRAY(data, data_flashed, prog_size); + } + + for (uint32_t i = 0; i < prog_size + 2; i++) { + data[i] = i; + } for (uint32_t i = 0; i < sector_size / prog_size; i++) { uint32_t prog_addr = address + i * prog_size; @@ -75,7 +86,6 @@ void flashiap_program_test() TEST_ASSERT_EQUAL_INT32(0, ret); } - uint8_t *data_flashed = new uint8_t[prog_size]; for (uint32_t i = 0; i < sector_size / prog_size; i++) { uint32_t page_addr = address + i * prog_size; ret = flash_device.read(data_flashed, page_addr, prog_size); diff --git a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp index 020964ec3f2..c0ce2ce2ba0 100644 --- a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp @@ -227,6 +227,20 @@ bd_size_t FlashIAPBlockDevice::get_erase_size(bd_addr_t addr) const return erase_size; } +int FlashIAPBlockDevice::get_erase_value() const +{ + if (!_is_initialized) { + return -1; + } + + uint8_t erase_val = _flash.get_erase_value(); + + DEBUG_PRINTF("get_erase_value: %" PRIX8 "\r\n", erase_val); + + return erase_val; +} + + bd_size_t FlashIAPBlockDevice::size() const { DEBUG_PRINTF("size: %" PRIX64 "\r\n", _size); diff --git a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h index 20279658fb3..0c1213295a1 100644 --- a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h +++ b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h @@ -109,6 +109,12 @@ class FlashIAPBlockDevice : public BlockDevice { */ virtual bd_size_t get_erase_size(bd_addr_t addr) const; + /** Get the value of storage when erased + * + * @return The value of storage when erased + */ + virtual int get_erase_value() const; + /** Get the total size of the underlying device * * @return Size of the underlying device in bytes diff --git a/drivers/FlashIAP.cpp b/drivers/FlashIAP.cpp index 879a74f3c89..b6b1c2377da 100644 --- a/drivers/FlashIAP.cpp +++ b/drivers/FlashIAP.cpp @@ -203,6 +203,11 @@ uint32_t FlashIAP::get_flash_size() const return flash_get_size(&_flash); } +uint8_t FlashIAP::get_erase_value() const +{ + return flash_get_erase_value(&_flash); +} + } #endif diff --git a/drivers/FlashIAP.h b/drivers/FlashIAP.h index 1699b692453..a33436c0f04 100644 --- a/drivers/FlashIAP.h +++ b/drivers/FlashIAP.h @@ -131,6 +131,13 @@ class FlashIAP : private NonCopyable { */ uint32_t get_page_size() const; + /** Get the flash erase value + * + * Get the value we read after erase operation + * @return flash erase value + */ + uint8_t get_erase_value() const; + private: /* Check if address and size are aligned to a sector diff --git a/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c index 8fdc6443c67..b91191d9ebe 100644 --- a/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c +++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c @@ -260,4 +260,11 @@ MBED_NONSECURE_ENTRY uint32_t flash_get_size(const flash_t *obj) return obj->target_config->flash_size; } +MBED_NONSECURE_ENTRY uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif // #ifndef DOMAIN_NS diff --git a/hal/flash_api.h b/hal/flash_api.h index 4231c083bac..4b59193e459 100644 --- a/hal/flash_api.h +++ b/hal/flash_api.h @@ -117,6 +117,13 @@ uint32_t flash_get_start_address(const flash_t *obj); */ uint32_t flash_get_size(const flash_t *obj); +/** Get the flash erase value + * + * @param obj The flash object + * @return The flash erase value + */ +uint8_t flash_get_erase_value(const flash_t *obj); + /**@}*/ #ifdef __cplusplus diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c index 019388a145b..3fe832baf20 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/flash_api.c @@ -101,3 +101,10 @@ uint32_t flash_get_size(const flash_t *obj) return ZBT_SRAM1_SIZE; } + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/flash_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/flash_api.c index 2a96377aeb5..a86a95fb9d1 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/flash_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/flash_api.c @@ -101,3 +101,10 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/flash_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/flash_api.c index 4215ac72dd8..16452e61d23 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/flash_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/flash_api.c @@ -82,4 +82,11 @@ uint32_t flash_get_size(const flash_t *obj) return CY_FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif // DEVICE_FLASH diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/flash_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/flash_api.c index eebb48072ce..e0e413ac1c6 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/flash_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/flash_api.c @@ -148,4 +148,11 @@ uint32_t flash_get_size(const flash_t *obj) #endif } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c index 2ab1acc374d..ab1c28d8b7b 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c @@ -195,6 +195,13 @@ uint32_t flash_get_start_address(const flash_t *obj) return 0; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif /** @}*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/flash_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/flash_api.c index 58c028143dc..c5fce46be8c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/flash_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/flash_api.c @@ -209,4 +209,11 @@ uint32_t flash_get_start_address(const flash_t *obj) return 0; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c b/targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c index 09314673e5d..6939db1b4f8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c @@ -134,4 +134,12 @@ void flash_set_target_config(flash_t *obj) } #endif // #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +MBED_NONSECURE_ENTRY uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif // #if DEVICE_FLASH diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c b/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c index bbf5c86aaa7..5693cd10b69 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c @@ -200,4 +200,11 @@ uint32_t flash_get_size(const flash_t *obj) return 0x80000; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c index ccd89b06a6d..db047c712a5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c @@ -122,4 +122,11 @@ uint32_t flash_get_size(const flash_t *obj) return FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c index 34223653e84..ba24d29d9b7 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c @@ -751,4 +751,12 @@ static void cache_control(void) __DSB(); // ensure completion of the invalidation __ISB(); // ensure instruction fetch path sees new I cache state } + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c index c8e3849aaef..813834e412d 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/flash_api.c @@ -69,3 +69,10 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + diff --git a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c index 169128d9946..7b74c559883 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c @@ -172,4 +172,11 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c index 8c07436265b..2dd57c45281 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c @@ -172,4 +172,11 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c index 0c76349ad35..b5e05aa782f 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c @@ -215,4 +215,11 @@ static uint32_t GetSectorSize(uint32_t Sector) return sectorsize; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c index 169128d9946..7b74c559883 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -172,4 +172,11 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c index 8f94d39b467..b9334c32d1d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c @@ -230,4 +230,11 @@ static uint32_t GetSectorSize(uint32_t Sector) return sectorsize; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c index 495a4f97b2d..87d439edf25 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c @@ -265,4 +265,11 @@ static uint32_t GetSectorSize(uint32_t Sector) return sectorsize; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c index 8277e728544..77c1fde3077 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c @@ -174,4 +174,11 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c index 2b6389440d9..f6d64ba3193 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c @@ -171,4 +171,11 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c index 7361cbcccc8..fe2a44c5023 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c @@ -284,4 +284,11 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c index 85993676069..a741eb3f3f2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c @@ -144,4 +144,16 @@ uint32_t flash_get_size(const flash_t *obj) return FLASH_SIZE; } +/** Get the flash erase value + * + * @param obj The flash object + * @return The flash erase value + */ +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + #endif // DEVICE_FLASH diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/flash_api.c index 7dd16b4a108..0425fd9669a 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/flash_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/flash_api.c @@ -162,3 +162,14 @@ uint32_t flash_get_size(const flash_t *obj) { return FLASH_CHIP_SIZE; } + +#if defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma location = "FLASH_ROM" +#endif +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/flash_api.c index 486612771d4..1245690750d 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/flash_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/flash_api.c @@ -121,3 +121,10 @@ static void internal_hosc_enable(void) work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); } + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +}