diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c
index 50759eb74b5..71a150d88e0 100644
--- a/targets/TARGET_STM/sleep.c
+++ b/targets/TARGET_STM/sleep.c
@@ -52,7 +52,7 @@ static void wait_loop(uint32_t timeout)
 
 
 // On L4 platforms we've seen unstable PLL CLK configuraiton
-// when DEEP SLEEP exits just few �s after being entered
+// when DEEP SLEEP exits just few µs after being entered
 // So we need to force MSI usage before setting clocks again
 static void ForcePeriphOutofDeepSleep(void)
 {
@@ -151,7 +151,25 @@ void hal_sleep(void)
     core_util_critical_section_enter();
 
     // Request to enter SLEEP mode
+#if TARGET_STM32L4
+    // State Transitions (see 5.3 Low-power modes, Fig. 13):
+    //  * (opt): Low Power Run (LPR) Mode -> Run Mode
+    //  * Run Mode -> Sleep
+    //  --- Wait for Interrupt --
+    //  * Sleep -> Run Mode
+    //  * (opt): Run Mode -> Low Power Run Mode
+
+    // [5.4.1 Power control register 1 (PWR_CR1)]
+    // 	LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).
+    int lowPowerMode = PWR->CR1 & PWR_CR1_LPR;
+    if (lowPowerMode) {
+        HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+    } else {
+        HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+    }
+#else
     HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
 
     // Enable IRQs
     core_util_critical_section_exit();