diff --git a/features/FEATURE_BLE/targets/TARGET_WISE1530_F412RE/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_WISE1530_F412RE/HCIDriver.cpp new file mode 100644 index 00000000000..6cc169ff39f --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_WISE1530_F412RE/HCIDriver.cpp @@ -0,0 +1,427 @@ +#include +#include "CordioBLE.h" +#include "CordioHCIDriver.h" +#include "hci_api.h" +#include "hci_cmd.h" +#include "hci_core.h" +#include "bstream.h" +#include +#include "hci_mbed_os_adaptation.h" +#include "H4TransportDriver.h" + +extern const int brcm_patch_ram_length; +extern const uint8_t brcm_patchram_buf[]; + +static const uint8_t pre_brcm_patchram_buf[] = { + // RESET followed by download mini driver cmd + 0x03, 0x0C, 0x00, + 0x2E, 0xFC, 0x00, +}; +static const int pre_brcm_patch_ram_length = sizeof(pre_brcm_patchram_buf); + +#define HCI_RESET_RAND_CNT 4 +#define HCI_VS_CMD_SET_SLEEP_MODE 0xFC27 + + +extern "C" uint32_t Set_GPIO_Clock(uint32_t port_idx); + +// 0: push pull +// 1: open drain +static void output_mode(PinName pin, int mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t port_index = STM_PORT(pin); + uint32_t pin_index = STM_PIN(pin); + + // Enable GPIO clock + uint32_t gpio_add = Set_GPIO_Clock(port_index); + GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; + + + /* Output mode configuration*/ + gpio->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pin_index)) ; + gpio->OTYPER |= (uint16_t)(((uint16_t)mode) << ((uint16_t)pin_index)); +} + +namespace ble { +namespace vendor { +namespace wise1530 { + +class HCIDriver : public cordio::CordioHCIDriver { +public: + HCIDriver( + cordio::CordioHCITransportDriver& transport_driver, + PinName bt_host_wake_name, + PinName bt_device_wake_name, + PinName bt_power_name + ) : cordio::CordioHCIDriver(transport_driver), + bt_host_wake_name(bt_host_wake_name), + bt_device_wake_name(bt_device_wake_name), + bt_power_name(bt_power_name), + bt_host_wake(bt_host_wake_name, PIN_INPUT, PullNone, 0), + bt_device_wake(bt_device_wake_name, PIN_OUTPUT, PullDefault, 1), + bt_power(bt_power_name, PIN_OUTPUT, PullUp, 0), + service_pack_index(0), + service_pack_ptr(0), + service_pack_length(0), + service_pack_next(), + service_pack_transfered(false) { + } + + virtual void do_initialize() + { + output_mode(bt_host_wake_name, 1); + output_mode(bt_device_wake_name, 0); + output_mode(bt_power_name, 1); + + wait_ms(500); + + bt_device_wake = 0; + wait_ms(500); + + bt_power = 1; + wait_ms(500); + } + + virtual void do_terminate() { } + + virtual void start_reset_sequence() + { + prepare_service_pack_transfert(); + } + + virtual void handle_reset_sequence(uint8_t *pMsg) + { + uint16_t opcode; + static uint8_t randCnt; + + /* if event is a command complete event */ + if (*pMsg == HCI_CMD_CMPL_EVT) { + /* parse parameters */ + pMsg += HCI_EVT_HDR_LEN; + pMsg++; /* skip num packets */ + BSTREAM_TO_UINT16(opcode, pMsg); + pMsg++; /* skip status */ + + if (service_pack_transfered == false) { + randCnt = 0; + ack_service_pack_command(opcode, pMsg); + return; + } + + /* decode opcode */ + switch (opcode) { + // Note: Reset is handled by ack_service_pack. + case HCI_VS_CMD_SET_SLEEP_MODE: + HciWriteLeHostSupport(); + break; + + case HCI_OPCODE_WRITE_LE_HOST_SUPPORT: + randCnt = 0; + /* send next command in sequence */ + HciSetEventMaskCmd((uint8_t *) hciEventMask); + break; + + case HCI_OPCODE_SET_EVENT_MASK: + randCnt = 0; + /* send next command in sequence */ + HciLeSetEventMaskCmd((uint8_t *) hciLeEventMask); + break; + + case HCI_OPCODE_LE_SET_EVENT_MASK: + /* send next command in sequence */ + HciSetEventMaskPage2Cmd((uint8_t *) hciEventMaskPage2); + break; + + case HCI_OPCODE_SET_EVENT_MASK_PAGE2: + /* send next command in sequence */ + HciReadBdAddrCmd(); + break; + + case HCI_OPCODE_READ_BD_ADDR: + /* parse and store event parameters */ + BdaCpy(hciCoreCb.bdAddr, pMsg); + HciLeReadBufSizeCmd(); + break; + + case HCI_OPCODE_LE_READ_BUF_SIZE: + /* parse and store event parameters */ + BSTREAM_TO_UINT16(hciCoreCb.bufSize, pMsg); + BSTREAM_TO_UINT8(hciCoreCb.numBufs, pMsg); + + // FixMe: The number of ACL buffer returned by the chip is + // incorrect. If more than two ACL packets are present in + // the controller, it may block the controller. + // Important: The ACL overflow event is **not** reported + // by the controller. + hciCoreCb.numBufs = 2; + + /* initialize ACL buffer accounting */ + hciCoreCb.availBufs = hciCoreCb.numBufs; + + /* send next command in sequence */ + HciLeReadSupStatesCmd(); + break; + + case HCI_OPCODE_LE_READ_SUP_STATES: + /* parse and store event parameters */ + memcpy(hciCoreCb.leStates, pMsg, HCI_LE_STATES_LEN); + + /* send next command in sequence */ + HciLeReadWhiteListSizeCmd(); + break; + + case HCI_OPCODE_LE_READ_WHITE_LIST_SIZE: + /* parse and store event parameters */ + BSTREAM_TO_UINT8(hciCoreCb.whiteListSize, pMsg); + + /* send next command in sequence */ + HciLeReadLocalSupFeatCmd(); + break; + + case HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT: + /* parse and store event parameters */ + BSTREAM_TO_UINT16(hciCoreCb.leSupFeat, pMsg); + + /* send next command in sequence */ + hciCoreReadResolvingListSize(); + break; + + case HCI_OPCODE_LE_READ_RES_LIST_SIZE: + /* parse and store event parameters */ + BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg); + + /* send next command in sequence */ + hciCoreReadMaxDataLen(); + break; + + case HCI_OPCODE_LE_READ_MAX_DATA_LEN: { + uint16_t maxTxOctets; + uint16_t maxTxTime; + + BSTREAM_TO_UINT16(maxTxOctets, pMsg); + BSTREAM_TO_UINT16(maxTxTime, pMsg); + + /* use Controller's maximum supported payload octets and packet duration times + * for transmission as Host's suggested values for maximum transmission number + * of payload octets and maximum packet transmission time for new connections. + */ + HciLeWriteDefDataLen(maxTxOctets, maxTxTime); + } break; + + case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN: + if (hciCoreCb.extResetSeq) { + /* send first extended command */ + (*hciCoreCb.extResetSeq)(pMsg, opcode); + } else { + /* initialize extended parameters */ + hciCoreCb.maxAdvDataLen = 0; + hciCoreCb.numSupAdvSets = 0; + hciCoreCb.perAdvListSize = 0; + + /* send next command in sequence */ + HciLeRandCmd(); + } + break; + + case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN: + case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS: + case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE: + if (hciCoreCb.extResetSeq) { + /* send next extended command in sequence */ + (*hciCoreCb.extResetSeq)(pMsg, opcode); + } + break; + + case HCI_OPCODE_LE_RAND: + /* check if need to send second rand command */ + if (randCnt < (HCI_RESET_RAND_CNT-1)) { + randCnt++; + HciLeRandCmd(); + } else { + uint8_t addr[6] = { 0 }; + memcpy(addr, pMsg, sizeof(addr)); + DM_RAND_ADDR_SET(addr, DM_RAND_ADDR_STATIC); + // note: will invoke set rand address + cordio::BLE::deviceInstance().getGap().setAddress( + BLEProtocol::AddressType::RANDOM_STATIC, + addr + ); + } + break; + + case HCI_OPCODE_LE_SET_RAND_ADDR: + /* send next command in sequence */ + signal_reset_sequence_done(); + break; + + default: + break; + } + } + } + +private: + + // send pre_brcm_patchram_buf + void prepare_service_pack_transfert(void) + { + service_pack_ptr = pre_brcm_patchram_buf; + service_pack_length = pre_brcm_patch_ram_length; + service_pack_next = &HCIDriver::start_service_pack_transfert; + service_pack_index = 0; + service_pack_transfered = false; + send_service_pack_command(); + } + + // Called once pre_brcm_patchram_buf has been transferred; send brcm_patchram_buf + void start_service_pack_transfert(void) + { + service_pack_ptr = brcm_patchram_buf; + service_pack_length = brcm_patch_ram_length; + service_pack_next = &HCIDriver::terminate_service_pack_transfert; + service_pack_index = 0; + service_pack_transfered = false; + send_service_pack_command(); + } + + // Called once post_brcm_patchram_buf has been transferred; start regular initialization. + void terminate_service_pack_transfert(void) + { + service_pack_ptr = NULL; + service_pack_length = 0; + service_pack_next = NULL; + service_pack_index = 0; + service_pack_transfered = true; + wait_ms(1000); + set_sleep_mode(); + } + + void send_service_pack_command(void) + { + uint16_t cmd_len = service_pack_ptr[service_pack_index + 2]; + uint16_t cmd_opcode = (service_pack_ptr[service_pack_index + 1] << 8) | service_pack_ptr[service_pack_index + 0]; + uint8_t *pBuf = hciCmdAlloc(cmd_opcode, cmd_len); + if (pBuf) { + memcpy(pBuf + HCI_CMD_HDR_LEN, service_pack_ptr + service_pack_index + HCI_CMD_HDR_LEN, cmd_len); + hciCmdSend(pBuf); + } else { + } + } + + void ack_service_pack_command(uint16_t opcode, uint8_t* msg) + { + uint16_t cmd_opcode = (service_pack_ptr[service_pack_index + 1] << 8) | service_pack_ptr[service_pack_index + 0]; + + if (cmd_opcode != opcode) { + // DO something in case of error + + while (true); + + } + + // update service pack index + service_pack_index += (HCI_CMD_HDR_LEN + service_pack_ptr[service_pack_index + 2]); + + if (service_pack_index < service_pack_length) { + send_service_pack_command(); + } else { + (this->*service_pack_next)(); + } + } + + void set_sleep_mode() + { + uint8_t *pBuf; + if ((pBuf = hciCmdAlloc(HCI_VS_CMD_SET_SLEEP_MODE, 12)) != NULL) + { + pBuf[HCI_CMD_HDR_LEN] = 0x00; // no sleep moode + pBuf[HCI_CMD_HDR_LEN + 1] = 0x00; // no idle threshold host (N/A) + pBuf[HCI_CMD_HDR_LEN + 2] = 0x00; // no idle threshold HC (N/A) + pBuf[HCI_CMD_HDR_LEN + 3] = 0x00; // BT WAKE + pBuf[HCI_CMD_HDR_LEN + 4] = 0x00; // HOST WAKE + pBuf[HCI_CMD_HDR_LEN + 5] = 0x00; // Sleep during SCO + pBuf[HCI_CMD_HDR_LEN + 6] = 0x00; // Combining sleep mode and SCM + pBuf[HCI_CMD_HDR_LEN + 7] = 0x00; // Tristate TX + pBuf[HCI_CMD_HDR_LEN + 8] = 0x00; // Active connection handling on suspend + pBuf[HCI_CMD_HDR_LEN + 9] = 0x00; // resume timeout + pBuf[HCI_CMD_HDR_LEN + 10] = 0x00; // break to host + pBuf[HCI_CMD_HDR_LEN + 10] = 0x00; // Pulsed host wake + hciCmdSend(pBuf); + } + } + + static const uint16_t HCI_OPCODE_WRITE_LE_HOST_SUPPORT = 0x0C6D; + + void HciWriteLeHostSupport() + { + uint8_t *pBuf; + if ((pBuf = hciCmdAlloc(HCI_OPCODE_WRITE_LE_HOST_SUPPORT, 2)) != NULL) + { + pBuf[HCI_CMD_HDR_LEN] = 0x01; + pBuf[HCI_CMD_HDR_LEN + 1] = 0x00; + hciCmdSend(pBuf); + } + } + + void hciCoreReadResolvingListSize(void) + { + /* if LL Privacy is supported by Controller and included */ + if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) && + (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY)) + { + /* send next command in sequence */ + HciLeReadResolvingListSize(); + } + else + { + hciCoreCb.resListSize = 0; + + /* send next command in sequence */ + hciCoreReadMaxDataLen(); + } + } + + void hciCoreReadMaxDataLen(void) + { + /* if LE Data Packet Length Extensions is supported by Controller and included */ + if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) && + (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT)) + { + /* send next command in sequence */ + HciLeReadMaxDataLen(); + } + else + { + /* send next command in sequence */ + HciLeRandCmd(); + } + } + + PinName bt_host_wake_name; + PinName bt_device_wake_name; + PinName bt_power_name; + DigitalInOut bt_host_wake; + DigitalInOut bt_device_wake; + DigitalInOut bt_power; + size_t service_pack_index; + const uint8_t* service_pack_ptr; + int service_pack_length; + void (HCIDriver::*service_pack_next)(); + bool service_pack_transfered; + +}; + +} // namespace wise1530 +} // namespace vendor +} // namespace ble + +ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() { + static ble::vendor::cordio::H4TransportDriver transport_driver( + /* TX */ PA_2, /* RX */ PA_3, /* cts */ PA_0, /* rts */ PA_1, 115200 + ); + static ble::vendor::wise1530::HCIDriver hci_driver( + transport_driver, /* host wake */ PC_0, /* device wake */ PB_8, /* bt_power */ PC_6 + ); + return hci_driver; +} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PeripheralNames.h new file mode 100644 index 00000000000..0bf04caec8d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PeripheralNames.h @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PA_9 +#define STDIO_UART_RX PA_10 +#define STDIO_UART UART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + FMPI2C_1 = (int)FMPI2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PeripheralPins.c new file mode 100644 index 00000000000..afcfddea69c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PeripheralPins.c @@ -0,0 +1,327 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - A0 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - LED1 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - A1 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - A3 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - A4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - A5 + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { +// {PB_3, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, +// {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, +// {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_10, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PB_15, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PD_12, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PD_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PF_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + +// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_2, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_4, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PinNames.h new file mode 100644 index 00000000000..8f50c4d5775 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/PinNames.h @@ -0,0 +1,229 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_3, + A1 = PC_0, + A2 = PC_3, + A3 = PC_1, + A4 = PC_4, + A5 = PC_5, + D0 = PG_9, + D1 = PG_14, + D2 = PF_15, + D3 = PE_13, + D4 = PF_14, + D5 = PE_11, + D6 = PE_9, + D7 = PF_13, + D8 = PF_12, + D9 = PD_15, + D10 = PD_14, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + GPIO0 = PA_5, + GPIO1 = PB_0, + GPIO2 = PB_1, + GPIO7 = PB_14, + + I2S_CK = PB_12, + I2S_SW = PA_4, + I2S_MCK = PB_10, + I2S_SD = PC_12, + + SERIAL_TX = PA_9, + SERIAL_RX = PA_10, + + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + UART2_TX = PB_10, + UART2_RX = PC_11, + + I2C0_SCL = PB_6, + I2C0_SDA = PB_7, + I2C0_RST = PC_13, + + SPI0_MOSI = PC_3, + SPI0_MISO = PC_2, + SPI0_SCK = PB_13, + SPI0_CS = PB_9, + + PWM_OUT = D9, + + ADCONV0 = PA_6, + ADCONV1 = PA_7, + ADCONV2 = PC_4, + ADCONV3 = PC_5, + + EXTI1 = PC_0, + + USB_HS_DP = PA_12, + USB_HS_DN = PA_11, + LED_RED = GPIO0, + LED1 = LED_RED, + LED2 = LED_RED, + USER_BUTTON = GPIO2, + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412rx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412rx.S new file mode 100644 index 00000000000..79e79059d30 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412rx.S @@ -0,0 +1,449 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f412rx.s +;* Author : MCD Application Team +;* Version : V2.6.0 +;* Date : 04-November-2016 +;* Description : STM32F412Rx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_MICRO/stm32f412zg.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_MICRO/stm32f412zg.sct new file mode 100644 index 00000000000..cdc67e0b8ed --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_MICRO/stm32f412zg.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2016, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F412ZG: 1024 KB FLASH (0x100000) + 256 KB SRAM (0x40000) +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1C4) (0x40000-0x1C4) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_STD/startup_stm32f412rx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_STD/startup_stm32f412rx.S new file mode 100644 index 00000000000..255e87ca4a5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_STD/startup_stm32f412rx.S @@ -0,0 +1,400 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f412rx.s +;* Author : MCD Application Team +;* Version : V2.6.0 +;* Date : 04-November-2016 +;* Description : STM32F412Rx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20040000 ; Top of RAM 256K + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_STD/stm32f412zg.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_STD/stm32f412zg.sct new file mode 100644 index 00000000000..cdc67e0b8ed --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_ARM_STD/stm32f412zg.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2016, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F412ZG: 1024 KB FLASH (0x100000) + 256 KB SRAM (0x40000) +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1C4) (0x40000-0x1C4) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_GCC_ARM/STM32F412RE.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_GCC_ARM/STM32F412RE.ld new file mode 100644 index 00000000000..c10094b9caa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_GCC_ARM/STM32F412RE.ld @@ -0,0 +1,160 @@ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 1024K +#endif +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 256K - 0x1C4 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f412rx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f412rx.S new file mode 100644 index 00000000000..9aafce9792e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f412rx.S @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file startup_stm32f412rx.s + * @author MCD Application Team + * @version V2.5.1 + * @date 28-June-2016 + * @brief STM32F412Rx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QUADSPI_IRQHandler /* QuadSPI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_IAR/startup_stm32f412rx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_IAR/startup_stm32f412rx.S new file mode 100644 index 00000000000..e3b8f7c007f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_IAR/startup_stm32f412rx.S @@ -0,0 +1,639 @@ +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Version : V2.5.1 +;* Date : 28-June-2016 +;* Description : STM32F412Zx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter0 + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter1 + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_IAR/stm32f412zx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_IAR/stm32f412zx.icf new file mode 100644 index 00000000000..f702047a09c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/TOOLCHAIN_IAR/stm32f412zx.icf @@ -0,0 +1,33 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } + +/* [ROM = 1024kb = 0x100000] */ +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE; + +/* [RAM = 256kb = 0x40000] Vector table dynamic copy: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200001C8; +define symbol __region_RAM_end__ = 0x2001FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x8000; +define symbol __size_heap__ = 0x10000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/cmsis.h new file mode 100644 index 00000000000..f0c2b2a9071 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/cmsis_nvic.h new file mode 100644 index 00000000000..a892171acef --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/cmsis_nvic.h @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F412ZG +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 97 vectors = 388 bytes from 0x40 to 0x1C3 +// Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM +#define NVIC_NUM_VECTORS 113 +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM + + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/flash_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/flash_data.h new file mode 100644 index 00000000000..9a4964bfad0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/flash_data.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Flash size */ +#define FLASH_SIZE (uint32_t) 0x100000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/hal_tick.h new file mode 100644 index 00000000000..19d9584eee3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/hal_tick.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "stm32f4xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() + +#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/stm32f412rx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/stm32f412rx.h new file mode 100644 index 00000000000..c18e20d2a0f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/stm32f412rx.h @@ -0,0 +1,14522 @@ +/** + ****************************************************************************** + * @file stm32f412rx.h + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS STM32F412Rx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - peripherals registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f412rx + * @{ + */ + + #ifndef __STM32F412Rx_H + #define __STM32F412Rx_H + + #ifdef __cplusplus + extern "C" { + #endif /* __cplusplus */ + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + + /** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ + #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ + #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ + #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U /*!< FPU present */ + #endif + /** + * @} + */ + + /** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + + /** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum + { + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + RNG_IRQn = 80, /*!< RNG global Interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ + FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ + FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */ + } IRQn_Type; + + /** + * @} + */ + + #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + #include "system_stm32f4xx.h" + #include + + /** @addtogroup Peripheral_registers_structures + * @{ + */ + + /** + * @brief Analog to Digital Converter + */ + + typedef struct + { + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ + } ADC_TypeDef; + + typedef struct + { + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ + } ADC_Common_TypeDef; + + + /** + * @brief Controller Area Network TxMailBox + */ + + typedef struct + { + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ + } CAN_TxMailBox_TypeDef; + + /** + * @brief Controller Area Network FIFOMailBox + */ + + typedef struct + { + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ + } CAN_FIFOMailBox_TypeDef; + + /** + * @brief Controller Area Network FilterRegister + */ + + typedef struct + { + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ + } CAN_FilterRegister_TypeDef; + + /** + * @brief Controller Area Network + */ + + typedef struct + { + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ + } CAN_TypeDef; + + /** + * @brief CRC calculation unit + */ + + typedef struct + { + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + } CRC_TypeDef; + + /** + * @brief DFSDM module registers + */ + typedef struct + { + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ + } DFSDM_Filter_TypeDef; + + /** + * @brief DFSDM channel configuration registers + */ + typedef struct + { + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + } DFSDM_Channel_TypeDef; + + /** + * @brief Debug MCU + */ + + typedef struct + { + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ + }DBGMCU_TypeDef; + + + /** + * @brief DMA Controller + */ + + typedef struct + { + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ + } DMA_Stream_TypeDef; + + typedef struct + { + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + } DMA_TypeDef; + + /** + * @brief External Interrupt/Event Controller + */ + + typedef struct + { + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ + } EXTI_TypeDef; + + /** + * @brief FLASH Registers + */ + + typedef struct + { + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ + } FLASH_TypeDef; + + + + /** + * @brief Flexible Static Memory Controller + */ + + typedef struct + { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + } FSMC_Bank1_TypeDef; + + /** + * @brief Flexible Static Memory Controller Bank1E + */ + + typedef struct + { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ + } FSMC_Bank1E_TypeDef; + /** + * @brief General Purpose I/O + */ + + typedef struct + { + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + } GPIO_TypeDef; + + /** + * @brief System configuration controller + */ + + typedef struct + { + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG Configuration register2, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x24 */ + } SYSCFG_TypeDef; + + /** + * @brief Inter-integrated Circuit Interface + */ + + typedef struct + { + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ + } I2C_TypeDef; + + /** + * @brief Inter-integrated Circuit Interface + */ + + typedef struct + { + __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ + } FMPI2C_TypeDef; + + /** + * @brief Independent WATCHDOG + */ + + typedef struct + { + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + } IWDG_TypeDef; + + + /** + * @brief Power Control + */ + + typedef struct + { + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ + } PWR_TypeDef; + + /** + * @brief Reset and Clock Control + */ + + typedef struct + { + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + uint32_t RESERVED7; /*!< Reserved, 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ + } RCC_TypeDef; + + /** + * @brief Real-Time Clock + */ + + typedef struct + { + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + } RTC_TypeDef; + + /** + * @brief SD host Interface + */ + + typedef struct + { + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ + } SDIO_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ + + typedef struct + { + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + } SPI_TypeDef; + + /** + * @brief QUAD Serial Peripheral Interface + */ + + typedef struct + { + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ + } QUADSPI_TypeDef; + + /** + * @brief TIM + */ + + typedef struct + { + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + } TIM_TypeDef; + + /** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + + typedef struct + { + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + } USART_TypeDef; + + /** + * @brief Window WATCHDOG + */ + + typedef struct + { + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ + } WWDG_TypeDef; + + /** + * @brief RNG + */ + + typedef struct + { + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + } RNG_TypeDef; + + /** + * @brief USB_OTG_Core_Registers + */ + typedef struct + { + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ + } USB_OTG_GlobalTypeDef; + + /** + * @brief USB_OTG_device_Registers + */ + typedef struct + { + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ + } USB_OTG_DeviceTypeDef; + + /** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ + typedef struct + { + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ + } USB_OTG_INEndpointTypeDef; + + /** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ + typedef struct + { + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ + } USB_OTG_OUTEndpointTypeDef; + + /** + * @brief USB_OTG_Host_Mode_Register_Structures + */ + typedef struct + { + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ + } USB_OTG_HostTypeDef; + + /** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ + typedef struct + { + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ + } USB_OTG_HostChannelTypeDef; + + /** + * @} + */ + + /** @addtogroup Peripheral_memory_map + * @{ + */ + #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ + #define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */ + #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */ + #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */ + #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */ + #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + #define FLASH_END 0x080FFFFFU /*!< FLASH end address */ + #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ + #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ + + /* Legacy defines */ + #define SRAM_BASE SRAM1_BASE + #define SRAM_BB_BASE SRAM1_BB_BASE + + /*!< Peripheral memory map */ + #define APB1PERIPH_BASE PERIPH_BASE + #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) + #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) + #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + + /*!< APB1 peripherals */ + #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) + #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) + #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) + #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) + #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) + #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) + #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) + #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) + #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) + #define RTC_BASE (APB1PERIPH_BASE + 0x2800U) + #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) + #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) + #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) + #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) + #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) + #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) + #define USART2_BASE (APB1PERIPH_BASE + 0x4400U) + #define USART3_BASE (APB1PERIPH_BASE + 0x4800U) + #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) + #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) + #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) + #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U) + #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) + #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) + #define PWR_BASE (APB1PERIPH_BASE + 0x7000U) + + /*!< APB2 peripherals */ + #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) + #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) + #define USART1_BASE (APB2PERIPH_BASE + 0x1000U) + #define USART6_BASE (APB2PERIPH_BASE + 0x1400U) + #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) + #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) + /* Legacy define */ + #define ADC_BASE ADC1_COMMON_BASE + #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) + #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) + #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) + #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) + #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) + #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) + #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) + #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) + #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) + #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) + #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U) + #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U) + #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U) + #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U) + #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U) + #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U) + + /*!< AHB1 peripherals */ + #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) + #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) + #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) + #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) + #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) + #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) + #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) + #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) + #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) + #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) + #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) + #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) + #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) + #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) + #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) + #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) + #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) + #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) + #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) + #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) + #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) + #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) + #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) + #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) + #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) + #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) + #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) + #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) + #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) + + /*!< AHB2 peripherals */ + #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) + + + /*!< FSMC Bankx registers base address */ + #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U) + #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U) + + /*!< Debug MCU registers base address */ + #define DBGMCU_BASE 0xE0042000U + /*!< USB registers base address */ + #define USB_OTG_FS_PERIPH_BASE 0x50000000U + + #define USB_OTG_GLOBAL_BASE 0x000U + #define USB_OTG_DEVICE_BASE 0x800U + #define USB_OTG_IN_ENDPOINT_BASE 0x900U + #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U + #define USB_OTG_EP_REG_SIZE 0x20U + #define USB_OTG_HOST_BASE 0x400U + #define USB_OTG_HOST_PORT_BASE 0x440U + #define USB_OTG_HOST_CHANNEL_BASE 0x500U + #define USB_OTG_HOST_CHANNEL_SIZE 0x20U + #define USB_OTG_PCGCCTL_BASE 0xE00U + #define USB_OTG_FIFO_BASE 0x1000U + #define USB_OTG_FIFO_SIZE 0x1000U + + #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */ + #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */ + #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ + /** + * @} + */ + + /** @addtogroup Peripheral_declaration + * @{ + */ + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) + #define TIM5 ((TIM_TypeDef *) TIM5_BASE) + #define TIM6 ((TIM_TypeDef *) TIM6_BASE) + #define TIM7 ((TIM_TypeDef *) TIM7_BASE) + #define TIM12 ((TIM_TypeDef *) TIM12_BASE) + #define TIM13 ((TIM_TypeDef *) TIM13_BASE) + #define TIM14 ((TIM_TypeDef *) TIM14_BASE) + #define RTC ((RTC_TypeDef *) RTC_BASE) + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) + #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) + #define SPI3 ((SPI_TypeDef *) SPI3_BASE) + #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) + #define USART2 ((USART_TypeDef *) USART2_BASE) + #define USART3 ((USART_TypeDef *) USART3_BASE) + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) + #define I2C3 ((I2C_TypeDef *) I2C3_BASE) + #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE) + #define CAN1 ((CAN_TypeDef *) CAN1_BASE) + #define CAN2 ((CAN_TypeDef *) CAN2_BASE) + #define PWR ((PWR_TypeDef *) PWR_BASE) + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) + #define TIM8 ((TIM_TypeDef *) TIM8_BASE) + #define USART1 ((USART_TypeDef *) USART1_BASE) + #define USART6 ((USART_TypeDef *) USART6_BASE) + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) + #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) + /* Legacy define */ + #define ADC ADC1_COMMON + #define SDIO ((SDIO_TypeDef *) SDIO_BASE) + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) + #define SPI4 ((SPI_TypeDef *) SPI4_BASE) + #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) + #define TIM9 ((TIM_TypeDef *) TIM9_BASE) + #define TIM10 ((TIM_TypeDef *) TIM10_BASE) + #define TIM11 ((TIM_TypeDef *) TIM11_BASE) + #define SPI5 ((SPI_TypeDef *) SPI5_BASE) + #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) + #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) + #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) + #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) + #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) + #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) + #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) + #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + #define CRC ((CRC_TypeDef *) CRC_BASE) + #define RCC ((RCC_TypeDef *) RCC_BASE) + #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) + #define DMA1 ((DMA_TypeDef *) DMA1_BASE) + #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) + #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) + #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) + #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) + #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) + #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) + #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) + #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) + #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) + #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) + #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) + #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) + #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) + #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) + #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) + #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + #define RNG ((RNG_TypeDef *) RNG_BASE) + #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) + #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) + + /** + * @} + */ + + /** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + + /******************************************************************************/ + /* Peripheral Registers_Bits_Definition */ + /******************************************************************************/ + + /******************************************************************************/ + /* */ + /* Analog to Digital Converter */ + /* */ + /******************************************************************************/ + + /******************** Bit definition for ADC_SR register ********************/ + #define ADC_SR_AWD_Pos (0U) + #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ + #define ADC_SR_AWD ADC_SR_AWD_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ + !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ + !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \ + !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ + /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ + /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ + /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ + /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, + STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ + /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG + and STM32F479NG Devices */ + /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */ + /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */ + /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */ + #define STM32F412Rx /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */ + /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, + STM32F413RG, STM32F413VG and STM32F413ZG Devices */ + /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS version number V2.6.1 + */ +#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F410Tx) + #include "stm32f410tx.h" +#elif defined(STM32F410Cx) + #include "stm32f410cx.h" +#elif defined(STM32F410Rx) + #include "stm32f410rx.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#elif defined(STM32F469xx) + #include "stm32f469xx.h" +#elif defined(STM32F479xx) + #include "stm32f479xx.h" +#elif defined(STM32F412Cx) + #include "stm32f412cx.h" +#elif defined(STM32F412Zx) + #include "stm32f412zx.h" +#elif defined(STM32F412Rx) + #include "stm32f412rx.h" +#elif defined(STM32F412Vx) + #include "stm32f412vx.h" +#elif defined(STM32F413xx) + #include "stm32f413xx.h" +#elif defined(STM32F423xx) + #include "stm32f423xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0U, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/system_stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/system_stm32f4xx.h new file mode 100644 index 00000000000..113f67cfe61 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/device/system_stm32f4xx.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/objects.h new file mode 100644 index 00000000000..565319422ca --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/objects.h @@ -0,0 +1,53 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct trng_s { + RNG_HandleTypeDef handle; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/system_clock.c new file mode 100644 index 00000000000..2ffdfc51c0b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_Advantech_F412RE/system_clock.c @@ -0,0 +1,268 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 + * AHBCLK (MHz) | 100 + * APB1CLK (MHz) | 50 + * APB2CLK (MHz) | 100 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "nvic_addr.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h index fe95369830c..7c8b0fa2053 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h @@ -80,7 +80,6 @@ #define HAL_RNG_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED -#define HAL_SD_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED @@ -95,7 +94,10 @@ #define HAL_SPDIFRX_MODULE_ENABLED #define HAL_DFSDM_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED +#ifndef TARGET_WICED +#define HAL_SD_MODULE_ENABLED #define HAL_MMC_MODULE_ENABLED +#endif /* ########################## HSE/HSI Values adaptation ##################### */ /** diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index f208b87fd38..34b91a93906 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -90,7 +90,8 @@ defined(TARGET_STM32F439ZI)) #define INITIAL_SP (0x20030000UL) -#elif defined(TARGET_STM32F412ZG) +#elif (defined(TARGET_STM32F412ZG) ||\ + defined(TARGET_Advantech_F412RE)) #define INITIAL_SP (0x20040000UL) #elif (defined(TARGET_STM32F413ZH) ||\ diff --git a/targets/TARGET_WICED/.mbedignore b/targets/TARGET_WICED/.mbedignore new file mode 100644 index 00000000000..5b1a5a276dc --- /dev/null +++ b/targets/TARGET_WICED/.mbedignore @@ -0,0 +1,137 @@ +WICED/libraries/filesystems/wicedfs/ +WICED/libraries/filesystems/FileX/ +WICED/libraries/filesystems/tester/ +WICED/libraries/filesystems/FATFS/ +WICED/libraries/filesystems/ota2/ +WICED/libraries/drivers/bluetooth/bluetooth_dual_mode.ThreadX.NetX.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_dual_mode.ThreadX.NetX.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_dual_mode.ThreadX.NetX.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_dual_mode.ThreadX.NetX_Duo.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_dual_mode.ThreadX.NetX_Duo.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_dual_mode.ThreadX.NetX_Duo.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_low_energy.ThreadX.NetX.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_low_energy.ThreadX.NetX.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_low_energy.ThreadX.NetX.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_low_energy.ThreadX.NetX_Duo.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_low_energy.ThreadX.NetX_Duo.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_low_energy.ThreadX.NetX_Duo.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_sbc.ThreadX.NetX.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_sbc.ThreadX.NetX.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_sbc.ThreadX.NetX.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_sbc.ThreadX.NetX_Duo.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_sbc.ThreadX.NetX_Duo.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_sbc.ThreadX.NetX_Duo.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_wiced_hci_bt.ThreadX.NetX.ARM_CM3.release.a +WICED/libraries/drivers/bluetooth/bluetooth_wiced_hci_bt.ThreadX.NetX.ARM_CM4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_wiced_hci_bt.ThreadX.NetX.ARM_CR4.release.a +WICED/libraries/drivers/bluetooth/bluetooth_wiced_hci_bt.ThreadX.NetX_Duo.ARM_CM3.release.a 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+/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "WISE1530Interface.h" + +#include "EthernetInterface.h" +#include "nsapi.h" +#include "lwipopts.h" + +#include "wiced_wifi.h" +#include "wiced_management.h" +#include "wwd_network_constants.h" +#include "wwd_buffer_interface.h" + +#include "lwip/etharp.h" +#include "lwip/ethip6.h" + + +static int wise1530_toerror(wiced_result_t res) { + return -res; +} + +static nsapi_security_t wise1530_tosecurity(wiced_security_t sec) { + switch (sec & (WEP_ENABLED | WPA_SECURITY | WPA2_SECURITY)) { + case WEP_ENABLED: return NSAPI_SECURITY_WEP; + case WPA_SECURITY: return NSAPI_SECURITY_WPA; + case WPA2_SECURITY: return NSAPI_SECURITY_WPA2; + default: + if (sec == WICED_SECURITY_OPEN) return NSAPI_SECURITY_NONE; + else return NSAPI_SECURITY_UNKNOWN; + } +} + +static wiced_security_t wise1530_fromsecurity(nsapi_security_t sec) { + switch (sec) { + case NSAPI_SECURITY_NONE: return WICED_SECURITY_OPEN; + case NSAPI_SECURITY_WEP: return WICED_SECURITY_WEP_PSK; + case NSAPI_SECURITY_WPA: return WICED_SECURITY_WPA_MIXED_PSK; + case NSAPI_SECURITY_WPA2: return WICED_SECURITY_WPA2_MIXED_PSK; + case NSAPI_SECURITY_WPA_WPA2: return WICED_SECURITY_WPA2_MIXED_PSK; + default: return WICED_SECURITY_UNKNOWN; + } +} + +int WISE1530Interface::connect( + const char *ssid, const char *pass, + nsapi_security_t security, + uint8_t channel) +{ + int err = set_channel(channel); + if (err) { + return err; + } + + err = set_credentials(ssid, pass, security); + if (err) { + return err; + } + + return connect(); +} + +int WISE1530Interface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) +{ + if ((ssid == NULL) || + (pass == NULL && security != NSAPI_SECURITY_NONE) || + (strlen(pass) > 63 && (security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA || security == NSAPI_SECURITY_WPA_WPA2))) + { + return NSAPI_ERROR_PARAMETER; + } + _ssid = ssid; + _pass = pass; + _security = security; + return NSAPI_ERROR_OK; +} + +int WISE1530Interface::set_network(const char *ip_address, const char *netmask, const char *gateway) +{ + return _iface.set_network(ip_address, netmask, gateway); +} + +int WISE1530Interface::set_dhcp(bool dhcp) +{ + return _iface.set_dhcp(dhcp); +} + +struct wise1530_scan_security_userdata { + Semaphore sema; + const char *ssid; + int ssidlen; + wiced_security_t security; +}; + +static wiced_result_t wise1530_scan_security_handler( + wiced_scan_handler_result_t *result) +{ + wise1530_scan_security_userdata *data = + (wise1530_scan_security_userdata*)result->user_data; + malloc_transfer_to_curr_thread(result); + + // finished scan, either succesfully or through an abort + if (result->status != WICED_SCAN_INCOMPLETE) { + data->sema.release(); + free(result); + return WICED_SUCCESS; + } + + if (data->ssidlen == result->ap_details.SSID.length && + memcmp(data->ssid, result->ap_details.SSID.value, data->ssidlen) == 0) { + // found a match + data->security = result->ap_details.security; + wwd_wifi_abort_scan(); + } + + // release result + free(result); + return WICED_SUCCESS; +} + +int WISE1530Interface::connect() +{ + // initialize wiced, this is noop if already init + wiced_result_t res = wiced_init(); + if (res != WICED_SUCCESS) { + return wise1530_toerror(res); + } + + // setup ssid + wiced_ssid_t ssid; + strncpy((char*)ssid.value, _ssid, SSID_NAME_SIZE); + ssid.value[SSID_NAME_SIZE-1] = '\0'; + ssid.length = strlen((char*)ssid.value); + + // choose network security + wiced_security_t security = wise1530_fromsecurity(_security); + if (security == WICED_SECURITY_OPEN) { + // none actually indicates we need to find out the security ourselves + // if ssid isn't being broadcasted we just continue with security none + wise1530_scan_security_userdata data; + data.ssid = _ssid; + data.ssidlen = strlen(_ssid); + data.security = WICED_SECURITY_OPEN; + + res = wiced_wifi_scan_networks(wise1530_scan_security_handler, &data); + if (res != WICED_SUCCESS) { + return wise1530_toerror(res); + } + + int tok = data.sema.wait(); + if (tok < 1) { + return NSAPI_ERROR_WOULD_BLOCK; + } + + security = data.security; + } + + // join the network + res = (wiced_result_t)wwd_wifi_join( + &ssid, + security, + (const uint8_t *)_pass, strlen(_pass), + NULL, + WWD_STA_INTERFACE); + if (res != WICED_SUCCESS) { + return wise1530_toerror(res); + } + + // bring up lwip + return _iface.connect(); +} + +int WISE1530Interface::disconnect() +{ + // bring down lwip + int err = _iface.disconnect(); + if (err) { + return err; + } + + // leave network + wiced_result_t res = (wiced_result_t)wwd_wifi_leave(WWD_STA_INTERFACE); + if (res != WICED_SUCCESS) { + return wise1530_toerror(res); + } + + return 0; +} + +const char *WISE1530Interface::get_mac_address() +{ + return _iface.get_mac_address(); +} + +const char *WISE1530Interface::get_ip_address() +{ + return _iface.get_ip_address(); +} + +const char *WISE1530Interface::get_gateway() +{ + return _iface.get_gateway(); +} + +const char *WISE1530Interface::get_netmask() +{ + return _iface.get_netmask(); +} + +int8_t WISE1530Interface::get_rssi() +{ + int32_t rssi; + wiced_result_t res = (wiced_result_t)wwd_wifi_get_rssi(&rssi); + if (res != 0) { + return 0; + } + + return (int8_t)rssi; +} + +struct wise1530_scan_userdata { + Semaphore sema; + WiFiAccessPoint *aps; + unsigned count; + unsigned offset; +}; + +static wiced_result_t wise1530_scan_count_handler( + wiced_scan_handler_result_t *result) +{ + wise1530_scan_userdata *data = (wise1530_scan_userdata*)result->user_data; + malloc_transfer_to_curr_thread(result); + + // finished scan, either succesfully or through an abort + if (result->status != WICED_SCAN_INCOMPLETE) { + data->sema.release(); + free(result); + return WICED_SUCCESS; + } + + // just count the available networks + data->offset += 1; + + // release result + free(result); + return WICED_SUCCESS; +} + +static wiced_result_t wise1530_scan_handler( + wiced_scan_handler_result_t *result) +{ + wise1530_scan_userdata *data = (wise1530_scan_userdata*)result->user_data; + malloc_transfer_to_curr_thread(result); + + // finished scan, either succesfully or through an abort + if (result->status != WICED_SCAN_INCOMPLETE) { + data->sema.release(); + free(result); + return WICED_SUCCESS; + } + + // can't really keep anymore scan results + if (data->offset == data->count) { + wwd_wifi_abort_scan(); + free(result); + return WICED_SUCCESS; + } + + // get ap stats + nsapi_wifi_ap ap; + + uint8_t length = result->ap_details.SSID.length; + if (length < sizeof(ap.ssid)-1) { + length = sizeof(ap.ssid)-1; + } + memcpy(ap.ssid, result->ap_details.SSID.value, length); + ap.ssid[length] = '\0'; + + memcpy(ap.bssid, result->ap_details.BSSID.octet, sizeof(ap.bssid)); + + ap.security = wise1530_tosecurity(result->ap_details.security); + ap.rssi = result->ap_details.signal_strength; + ap.channel = result->ap_details.channel; + + // store as ap object + data->aps[data->offset] = WiFiAccessPoint(ap); + data->offset += 1; + + // release result + free(result); + return WICED_SUCCESS; +} + +int WISE1530Interface::scan(WiFiAccessPoint *aps, unsigned count) +{ + // initialize wiced, this is noop if already init + wiced_result_t res = wiced_init(); + if (res != WICED_SUCCESS) { + return wise1530_toerror(res); + } + + wise1530_scan_userdata data; + data.aps = aps; + data.count = count; + data.offset = 0; + + // either count available ap or actually scan based on count argument + wiced_scan_result_handler_t handler = (count == 0) + ? wise1530_scan_count_handler : wise1530_scan_handler; + + res = wiced_wifi_scan_networks(handler, &data); + if (res != WICED_SUCCESS) { + return wise1530_toerror(res); + } + + int tok = data.sema.wait(); + if (tok < 1) { + return NSAPI_ERROR_WOULD_BLOCK; + } + + return data.offset; +} + +NetworkStack *WISE1530Interface::get_stack() +{ + return _iface.get_stack(); +} diff --git a/targets/TARGET_WICED/TARGET_WISE1530_F412RE/WISE1530Interface.h b/targets/TARGET_WICED/TARGET_WISE1530_F412RE/WISE1530Interface.h new file mode 100644 index 00000000000..7c68fca3038 --- /dev/null +++ b/targets/TARGET_WICED/TARGET_WISE1530_F412RE/WISE1530Interface.h @@ -0,0 +1,167 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef WISE1530_INTERFACE_H +#define WISE1530_INTERFACE_H + +#include "mbed.h" +#include "EthernetInterface.h" + + +/** WISE1530Interface class + * Implementation of the NetworkStack for the WISE1530 + */ +class WISE1530Interface : public WiFiInterface +{ +public: + /** Start the interface + * + * Attempts to connect to a WiFi network. Requires ssid and passphrase to be set. + * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. + * + * @return 0 on success, negative error code on failure + */ + virtual int connect(); + + /** Start the interface + * + * Attempts to connect to a WiFi network. + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) + * @param channel This parameter is not supported, setting it to anything else than 0 will result in NSAPI_ERROR_UNSUPPORTED + * @return 0 on success, or error code on failure + */ + virtual int connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, + uint8_t channel = 0); + + /** Stop the interface + * @return 0 on success, negative on failure + */ + virtual int disconnect(); + + /** Set a static IP address + * + * Configures this network interface to use a static IP address. + * Implicitly disables DHCP, which can be enabled in set_dhcp. + * Requires that the network is disconnected. + * + * @param address Null-terminated representation of the local IP address + * @param netmask Null-terminated representation of the local network mask + * @param gateway Null-terminated representation of the local gateway + * @return 0 on success, negative error code on failure + */ + virtual nsapi_error_t set_network( + const char *ip_address, const char *netmask, const char *gateway); + + /** Enable or disable DHCP on the network + * + * Requires that the network is disconnected + * + * @param dhcp False to disable dhcp (defaults to enabled) + * @return 0 on success, negative error code on failure + */ + virtual nsapi_error_t set_dhcp(bool dhcp); + + /** Set the WiFi network credentials + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection + * (defaults to NSAPI_SECURITY_NONE) + * @return 0 on success, or error code on failure + */ + virtual int set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); + + /** Set the WiFi network channel - NOT SUPPORTED + * + * This function is not supported and will return NSAPI_ERROR_UNSUPPORTED + * + * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) + * @return Not supported, returns NSAPI_ERROR_UNSUPPORTED + */ + virtual int set_channel(uint8_t channel) { + if (channel != 0) { + return NSAPI_ERROR_UNSUPPORTED; + } + + return 0; + } + + /** Get the internally stored MAC address + * @return MAC address of the interface + */ + virtual const char *get_mac_address(); + + /** Get the internally stored IP address + * @return IP address of the interface or null if not yet connected + */ + virtual const char *get_ip_address(); + + /** Get the local gateway + * + * @return Null-terminated representation of the local gateway + * or null if no network mask has been recieved + */ + virtual const char *get_gateway(); + + /** Get the local network mask + * + * @return Null-terminated representation of the local network mask + * or null if no network mask has been recieved + */ + virtual const char *get_netmask(); + + /** Gets the current radio signal strength for active connection + * + * @return Connection strength in dBm (negative value) + */ + virtual int8_t get_rssi(); + + /** Scan for available networks + * + * This function will block. + * + * @param ap Pointer to allocated array to store discovered AP + * @param count Size of allocated @a res array, or 0 to only count available AP + * @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0) + * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error + */ + virtual int scan(WiFiAccessPoint *res, unsigned count); + +protected: + /** Provide access to the NetworkStack object + * + * @return The underlying NetworkStack object + */ + virtual NetworkStack *get_stack(); + +private: + class LWIPInterface : public EthernetInterface { + public: + using EthernetInterface::get_stack; + }; + + LWIPInterface _iface; + + const char *_ssid; + const char *_pass; + nsapi_security_t _security; + uint8_t _channel; +}; + +#endif diff --git a/targets/TARGET_WICED/TARGET_WISE1530_F412RE/wise1530_emac.c b/targets/TARGET_WICED/TARGET_WISE1530_F412RE/wise1530_emac.c new file mode 100644 index 00000000000..e2ef6167123 --- /dev/null +++ b/targets/TARGET_WICED/TARGET_WISE1530_F412RE/wise1530_emac.c @@ -0,0 +1,228 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_wait_api.h" +#include "nsapi.h" +#include "lwipopts.h" +#include + +#include "wiced_wifi.h" +#include "wiced_management.h" +#include "wwd_network_constants.h" +#include "wwd_buffer_interface.h" + +#include "lwip/etharp.h" +#include "lwip/ethip6.h" + + +/* globally stored netif for for wiced + */ +static struct netif *host_network_netif = 0; + +/* called by lwip layer, nops + */ +void eth_arch_enable_interrupts(void) {} +void eth_arch_disable_interrupts(void) {} + +/* notify link is up or down + */ +wiced_result_t wiced_network_notify_link_up(void) +{ + if (host_network_netif) { + netif_set_link_up(host_network_netif); + } + return WICED_SUCCESS; +} + +wiced_result_t wiced_network_notify_link_down(void) +{ + if (host_network_netif) { + netif_set_link_down(host_network_netif); + } + return WICED_SUCCESS; +} + +/* + * Called by WICED to pass received data to the network stack + * + * Implemented in 'network adapter driver' which is specific to the + * network stack in use. + * Packets received from the Wi-Fi network by WICED are forwarded to this function which + * must be implemented in the network interface. Ethernet headers + * are present at the start of these packet buffers. + * + * This function is called asynchronously in the context of the + * WICED thread whenever new data has arrived. + * Packet buffers are allocated within WICED, and ownership is transferred + * to the network stack. The network stack or application is thus + * responsible for releasing the packet buffers. + * Most packet buffering systems have a pointer to the 'current point' within + * the packet buffer. When this function is called, the pointer points + * to the start of the Ethernet header. There is other inconsequential data + * before the Ethernet header. + * + * It is preferable that the @ref host_network_process_ethernet_data function simply puts + * the received packet on a queue for processing by another thread. This avoids the + * WICED thread being unnecessarily tied up which would delay other packets + * being transmitted or received. + * + * @param buffer : Handle of the packet which has just been received. Responsibility for + * releasing this buffer is transferred from WICED at this point. + * @param interface : The interface (AP or STA) on which the packet was received. + * + */ +void host_network_process_ethernet_data(wiced_buffer_t buffer, wwd_interface_t interface) +{ + MBED_ASSERT(interface == WWD_STA_INTERFACE); + + if (!host_network_netif) { + // ignore any trailing packets + host_buffer_release(buffer, WWD_NETWORK_RX); + return; + } + + void *data = host_buffer_get_current_piece_data_pointer(buffer); + uint16_t size = host_buffer_get_current_piece_size(buffer); + + struct pbuf *p = pbuf_alloc(PBUF_RAW, size, PBUF_RAM); + if (!p) { + // ignore oom, may be caused by excessive packets from outside source + return; + } + + memcpy(p->payload, data, size); + host_buffer_release(buffer, WWD_NETWORK_RX); + + err_t err = host_network_netif->input(p, host_network_netif); + MBED_ASSERT(err == ERR_OK); +} + +/* + * Called by the Network Stack to send an ethernet frame + * + * Implemented in 'network adapter driver' which is specific to the + * network stack in use. + * This function takes Ethernet data from the network stack and queues it for transmission over the wireless network. + * The function can be called from any thread context as it is thread safe, however + * it must not be called from interrupt context since it can block while waiting + * for a lock on the transmit queue. + * + * This function returns immediately after the packet has been queued for transmit, + * NOT after it has been transmitted. Packet buffers passed to the WICED core + * are released inside the WICED core once they have been transmitted. + * + * Some network stacks assume the driver send function blocks until the packet has been physically sent. This + * type of stack typically releases the packet buffer immediately after the driver send function returns. + * In this case, and assuming the buffering system can count references to packet buffers, the driver send function + * can take an additional reference to the packet buffer. This enables the network stack and the WICED core driver + * to independently release their own packet buffer references. + * + * @param buffer : Handle of the packet buffer to be sent. + * @param interface : the interface over which to send the packet (AP or STA) + * + */ +extern void wwd_network_send_ethernet_data(wiced_buffer_t buffer, wwd_interface_t interface); /* Returns immediately - Wiced_buffer_tx_completed will be called once the transmission has finished */ + +/* Called by LWIP to send an ethernet frame + * + * Must call wwd_network_send_ethernet_data, see above + */ +err_t host_network_send_ethernet_data(struct netif *netif, struct pbuf *p) +{ + void *data = p->payload; + uint16_t size = p->tot_len; + + wiced_buffer_t buffer; + wwd_result_t res = host_buffer_get(&buffer, WWD_NETWORK_TX, size+64, WICED_TRUE); + MBED_ASSERT(res == WWD_SUCCESS); + + host_buffer_add_remove_at_front(&buffer, 64); + + void *dest = host_buffer_get_current_piece_data_pointer(buffer); + (void)data; + pbuf_copy_partial(p, dest, size, 0); + + wwd_network_send_ethernet_data(buffer, WWD_STA_INTERFACE); + + return ERR_OK; +} + +/* + * Should be called at the beginning of the program to set up the + * network interface. + * + * This function should be passed as a parameter to netif_add(). + * + * @param[in] netif the lwip network interface structure for this netif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t eth_arch_enetif_init(struct netif *netif) +{ + // Make sure WICED is up, noop if already init + wiced_result_t res = wiced_init(); + MBED_ASSERT(res == WICED_SUCCESS); + + // get mac address + wiced_mac_t mac; + res = wiced_wifi_get_mac_address(&mac); + MBED_ASSERT(res == WICED_SUCCESS); + + MBED_STATIC_ASSERT(sizeof(netif->hwaddr) >= sizeof(mac.octet), + "Must have enouch space for mac address"); + memcpy(netif->hwaddr, mac.octet, sizeof(mac.octet)); + netif->hwaddr_len = sizeof(mac.octet); + + // get mtu + netif->mtu = WICED_PAYLOAD_MTU; + + // get flags, note link starts already up + netif->flags + = NETIF_FLAG_BROADCAST + | NETIF_FLAG_ETHARP + | NETIF_FLAG_ETHERNET + | NETIF_FLAG_LINK_UP; + + // get interface name + netif->hostname = "wiced"; + memcpy(netif->name, "wl", 2); + + // setup output functions +#if LWIP_IPV4 + netif->output = etharp_output; +#endif +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif + + // setup link output function + netif->linkoutput = host_network_send_ethernet_data; + + // keep track of netif for wiced + host_network_netif = netif; + + return ERR_OK; +} + +/* Other stubs + */ +wiced_result_t wiced_network_deinit (void) { return WICED_SUCCESS; } +wiced_result_t wiced_network_init (void) { return WICED_SUCCESS; } +void wiced_wireless_link_down_handler (void) {} +void wiced_wireless_link_renew_handler (void) {} +void wiced_wireless_link_up_handler (void) {} + diff --git a/targets/TARGET_WICED/TARGET_WISE1530_F412RE/wise1530_test_config.json b/targets/TARGET_WICED/TARGET_WISE1530_F412RE/wise1530_test_config.json new file mode 100644 index 00000000000..fc1acb6bece --- /dev/null +++ b/targets/TARGET_WICED/TARGET_WISE1530_F412RE/wise1530_test_config.json @@ -0,0 +1,27 @@ +{ + "config": { + "header-file": { + "help" : "String for including your driver header file", + "value" : "\"WISE1530Interface.h\"" + }, + "object-construction" : { + "value" : "new WISE1530Interface()" + }, + "connect-statement" : { + "help" : "Must use 'net' variable name", + "value" : "((WISE1530Interface *)net)->connect(\"ssid\", \"password\")" + }, + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"195.34.89.241\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + }, + "tcp-echo-prefix" : { + "help" : "Some servers send a prefix before echoed message", + "value" : "\"u-blox AG TCP/UDP test service\\n\"" + } + } +} diff --git a/targets/TARGET_WICED/WICED.md b/targets/TARGET_WICED/WICED.md new file mode 100644 index 00000000000..120d2ee7707 --- /dev/null +++ b/targets/TARGET_WICED/WICED.md @@ -0,0 +1,245 @@ +# How to add the WICED SDK + +This document summarizes how to download and integrate the WICED SDK into Mbed OS. + +**NOTE:** This document is intended for when the WICED SDK is extracted from Mbed OS. + +There are several files not provided by the WICED SDK. This is a non-exhaustive +list of files that are currently provided by Mbed OS: +- w_generated_mac_address.txt +- w_generated_security_dct.h +- w_resources.h +- mbed_lib.json + +## Download the WICED SDK and Advantech patch for the WISE1530 + +You can find the full instructions to download the WICED SDK with Advantech's patches +on Advantech's Wiki: +http://ess-wiki.advantech.com.tw/view/WISE-1530_SDK + +To get the WICED SDK, download WICED-Studio-4.1 for your platform: +https://community.cypress.com/community/wiced-wifi/wiced-wifi-documentation + +Once downloaded, move the folder `43xxx_Wi-Fi` into `targets/TARGET_WICED`. Rename +the `43xxx_Wi-Fi` folder to `WICED`. + +For the WISE1530, download the patch from Advantech: +http://ess-wiki.advantech.com.tw/wiki/images/4/44/WM-BN-BM-22_SDK_5.1.x_platform_patch_v1.5.zip + +Once downloaded, copy the contents into `targets/TARGET_WICED/WICED`. + +## Enable compilation of the WICED SDK and Mbed OS wrapper + +To enable compilation of the WICED SDK, add the label `WICED` to the `target.extra_labels` and 'BLE' to the `target.features_add` +in your mbed_app.json: + +``` json +{ + "target_overrides": { + "WISE1530_F412RE": { + "target.extra_labels_add": ["WICED"], + "target.features_add": ["BLE"] + } + } +} +``` + +## Modify the WICED SDK to support Mbed OS's build tools + +1. Remove these files because they are unnecessary and large: + - `targets/TARGET_WICED/WICED/tools` + - `targets/TARGET_WICED/WICED/apps` + - `targets/TARGET_WICED/WICED/doc` + - `targets/TARGET_WICED/WICED/RTOS/NoOS` + - `targets/TARGET_WICED/WICED/RTOS/NuttX` + - `targets/TARGET_WICED/WICED/RTOS/ThreadX` + - `targets/TARGET_WICED/WICED/network/NetX` + - `targets/TARGET_WICED/WICED/network/NetX_Duo` + - `targets/TARGET_WICED/WICED/network/NoNS` + - `targets/TARGET_WICED/WICED/network/NuttX_NS` + +1. Add the `w_` prefix to all c/h files in WICED that do not begin with + `wiced_` or `wwd_`. + + Edit all c/h files and change the relevant `#include` statments to use the + updated file names. + + This is required to avoid naming conflicts between Mbed OS and the WICED SDK. + +1. Prevent Mbed OS from compiling the include-only c files. These are + any include statments that refer to a file ending in `.c`. + + For example: + + ``` diff + - libraries/crypto/micro-ecc/w_asm_arm.c + + libraries/crypto/micro-ecc/w_asm_arm.inc + ``` + + Edit all c/h files, and change the relevant `#include` statements to use the + updated file names. + +1. Remove any references to the WICED file system. + + For example: + + ``` diff + - #include "wicedfs.h" + ``` + +1. Create a C wrapper for the firmware image. + + In `targets/TARGET_WICED/WICED/resources/firmware/4343W`: + + ``` bash + xxd -i 4343WA1.bin > 4343WA1.c + sed -i 's/__4343WA1_bin/wifi_firmware_image_data/' 4343WA1.c + sed -i 's/unsigned/const unsigned/' 4343WA1.c + ``` + + Then, modify the firmware image in the C wrapper to match WICED's link-time + resource API. + + In `targets/TARGET_WICED/WICED/resources/firmware/4343W/4343WA1.c`: + + ``` c + #include "w_resources.h" + + extern const resource_hnd_t wifi_firmware_image; + extern const char wifi_firmware_image_data[383156]; + + const resource_hnd_t wifi_firmware_image = { + .location = RESOURCE_IN_MEMORY, + .size = sizeof(wifi_firmware_image_data), + .val.mem.data = wifi_firmware_image_data, + }; + + const char wifi_firmware_image_data[383156] = { + ... + ``` + + Then, create a `w_resources.h` file to reference the above firmware image. + + ``` c + #ifndef INCLUDED_RESOURCES_H_ + #define INCLUDED_RESOURCES_H_ + #include "wiced_resource.h" + extern const resource_hnd_t wifi_firmware_image; + extern const char wifi_firmware_image_data[383156]; + #endif + ``` + +1. Create the `w_generated_security_dct.h` file that + the WICED SDK tools would normally generate. + + ``` c + #define CERTIFICATE_STRING "\0" + #define PRIVATE_KEY_STRING "\0" + ``` + +1. Create the `w_generated_mac_address.txt` file that + the WICED SDK tools would normally generate. + + ``` c + #define NVRAM_GENERATED_MAC_ADDRESS "macaddr=02:0A:F7:11:b6:19" + #define DCT_GENERATED_MAC_ADDRESS "\x02\x0A\xF7\x19\x11\xb6" + #define DCT_GENERATED_ETHERNET_MAC_ADDRESS "\x02\x0A\xF7\x19\x11\xb7" + ``` + +1. Change any instances of `_irq` functions to match Mbed OS's linker `_IRQHandler` + + For example: + + ``` diff + - WWD_RTOS_DEFINE_ISR( NoOS_systick_irq ) + + WWD_RTOS_DEFINE_ISR( NoOS_systick_IRQHandler ) + ``` + +1. Comment out the bad `wwd_bus_packet_available_to_read` call while polling for + bus packet status. + + In `targets/TARGET_WICED/WICED/WWD/internal/wwd_thread.c` line 336: + + ``` diff + wwd_bus_interrupt = WICED_FALSE; + + /* Check if the interrupt indicated there is a packet to read */ + - if ( wwd_bus_packet_available_to_read( ) != 0) + + // TODO: packet check causes device to lock up^M + + if ( /*wwd_bus_packet_available_to_read( )*/ 1 != 0)^M + { + /* Receive all available packets */ + do + ``` + + Note this is required for the WISE1530 but may not be needed for other + platforms. + +1. Remove the includes of `w_core_cm4.h` and `w_core_cmFunc.h`, and replace the + includes with references to Mbed OS's `core_cm4.h`. + + For example: + + ``` diff + - #include "w_core_cmFunc.h" + + #include "core_cm4.h" + ``` + +1. Remove the padding of SDPCM data packets. This requires modifications in two + places. + + In `targets/TARGET_WICED/WICED/WWD/internal/w_wwd_sdpcm.c` line 210: + + ``` diff + typedef struct + { + sdpcm_common_header_t common; + - uint8_t _padding[2]; + + //uint8_t _padding[2]; + sdpcm_bdc_header_t bdc_header; + } sdpcm_data_header_t; + ``` + + In `targets/TARGET_WICED/WICED/WWD/internal/w_wwd_sdpcm.c` line 1282: + + ``` diff + /* Prepare the SDPCM header */ + memset( (uint8_t*) &packet->sdpcm_header, 0, sizeof(sdpcm_header_t) ); + packet->sdpcm_header.sw_header.channel_and_flags = (uint8_t) header_type; + - packet->sdpcm_header.sw_header.header_length = ( header_type == DATA_HEADER ) ? sizeof(sdpcm_header_t) + 2 : sizeof(sdpcm_header_t); + + packet->sdpcm_header.sw_header.header_length = ( header_type == DATA_HEADER ) ? sizeof(sdpcm_header_t) /*+ 2*/ : sizeof(sdpcm_header_t);^M + packet->sdpcm_header.sw_header.sequence = 0; /* Note: The real sequence will be written later */ + packet->sdpcm_header.frametag[0] = size; + packet->sdpcm_header.frametag[1] = (uint16_t) ~size; + ``` + + Note this is required for the WISE1530 but may not be needed for other + platforms. + +1. Set up SDIO_ENUMERATION_TIMEOUT_MS to be configurable. Mbed OS will override this, + depending on the current platform. + + In `targets/TARGET_WICED/WICED/WICED/platform/MCU/STM32F4xx/WWD/wwd_SDIO.c` line 66: + + ``` diff + #define SDIO_IRQ_CHANNEL ((u8)0x31) + #define DMA2_3_IRQ_CHANNEL ((u8)DMA2_Stream3_IRQn) + #define BUS_LEVEL_MAX_RETRIES (5) + + + + #ifndef SDIO_ENUMERATION_TIMEOUT_MS + #define SDIO_ENUMERATION_TIMEOUT_MS (500) + + #endif + ``` + +## Running the Mbed OS socket demo + +For the WISE1530, you now have access to the Mbed OS WISE1530Interface class. + +You can try this class with the Mbed OS socket example: +https://github.com/armmbed/mbed-os-example-sockets + + + + + + diff --git a/targets/TARGET_WICED/mbed_lib.json b/targets/TARGET_WICED/mbed_lib.json new file mode 100644 index 00000000000..ce7fbb2ab7b --- /dev/null +++ b/targets/TARGET_WICED/mbed_lib.json @@ -0,0 +1,487 @@ +{ + "name": "WICED", + "config": { + "p2p-max-associated-devices": { + "macro_name": "P2P_MAX_ASSOCIATED_DEVICES", + "value": 5, + "help": "WICED Wi-Fi Direct Options" + }, + "wiced-allocate-packet-timeout": { + "macro_name": "WICED_ALLOCATE_PACKET_TIMEOUT", + "value": 2000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-application-priority": { + "macro_name": "WICED_APPLICATION_PRIORITY", + "value": 7, + "help": "Thread priority, 9 is lowest, 0 is highest" + }, + "wiced-auto-ip-address-resolution-timeout": { + "macro_name": "WICED_AUTO_IP_ADDRESS_RESOLUTION_TIMEOUT", + "value": 15000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-default-application-stack-size": { + "macro_name": "WICED_DEFAULT_APPLICATION_STACK_SIZE", + "value": 6144, + "help": "Application thread stack size" + }, + "wiced-default-country-aggregate-code": { + "macro_name": "WICED_DEFAULT_COUNTRY_AGGREGATE_CODE", + "value": "WICED_COUNTRY_AGGREGATE_XV_0", + "help": "WICED_DEFAULT_COUNTRY_AGGREGATE_CODE" + }, + "wiced-default-country-code": { + "macro_name": "WICED_DEFAULT_COUNTRY_CODE", + "value": "WICED_COUNTRY_UNITED_STATES", + "help": "Country code" + }, + "wiced-default-ioctl-packet-timeout": { + "macro_name": "WICED_DEFAULT_IOCTL_PACKET_TIMEOUT", + "value": "WICED_NEVER_TIMEOUT", + "help": "Default WICED IOCTL/IOVAR timeouts in milliseconds" + }, + "wiced-default-library-priority": { + "macro_name": "WICED_DEFAULT_LIBRARY_PRIORITY", + "value": 5, + "help": "Thread priority, 9 is lowest, 0 is highest" + }, + "wiced-default-soft-ap-dtim-period": { + "macro_name": "WICED_DEFAULT_SOFT_AP_DTIM_PERIOD", + "value": 1, + "help": "Soft AP Options" + }, + "wiced-default-tcp-listen-queue-size": { + "macro_name": "WICED_DEFAULT_TCP_LISTEN_QUEUE_SIZE", + "value": 5, + "help": "WICED TCP Options" + }, + "wiced-default-tcp-rx-depth-queue": { + "macro_name": "WICED_DEFAULT_TCP_RX_DEPTH_QUEUE", + "value": 5, + "help": "WICED TCP Options" + }, + "wiced-default-tcp-tx-depth-queue": { + "macro_name": "WICED_DEFAULT_TCP_TX_DEPTH_QUEUE", + "value": 5, + "help": "WICED TCP Options" + }, + "wiced-default-tcp-tx-retries": { + "macro_name": "WICED_DEFAULT_TCP_TX_RETRIES", + "value": 10, + "help": "WICED TCP Options" + }, + "wiced-default-udp-queue-size": { + "macro_name": "WICED_DEFAULT_UDP_QUEUE_SIZE", + "value": 5, + "help": "WICED UDP Options" + }, + "wiced-default-worker-priority": { + "macro_name": "WICED_DEFAULT_WORKER_PRIORITY", + "value": 5, + "help": "Thread priority, 9 is lowest, 0 is highest" + }, + "wiced-dhcp-ip-address-resolution-timeout": { + "macro_name": "WICED_DHCP_IP_ADDRESS_RESOLUTION_TIMEOUT", + "value": 15000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-disable-ampdu-tx": { + "macro_name": "WICED_DISABLE_AMPDU_TX", + "value": null, + "help": "Uncomment to disable AMPDU transmission" + }, + "wiced-disable-defaults": { + "macro_name": "WICED_DISABLE_DEFAULTS", + "value": "", + "help": "Uncomment to disable defaults" + }, + "wiced-disable-mcu-powersave": { + "macro_name": "WICED_DISABLE_MCU_POWERSAVE", + "value": null, + "help": "Uncomment to disable MCU powersave API functions" + }, + "wiced-disable-ssid-broadcast": { + "macro_name": "WICED_DISABLE_SSID_BROADCAST", + "value": null, + "help": "Uncomment to \"hide\" the soft AP" + }, + "wiced-disable-stdio": { + "macro_name": "WICED_DISABLE_STDIO", + "value": null, + "help": "WICED_DISABLE_STDIO" + }, + "wiced-disable-tls": { + "macro_name": "WICED_DISABLE_TLS", + "value": null, + "help": "Uncomment both to disable TLS completely" + }, + "wiced-disable-watchdog": { + "macro_name": "WICED_DISABLE_WATCHDOG", + "value": null, + "help": "Uncomment to disable watchdog. For debugging only" + }, + "wiced-enable-auto-country": { + "macro_name": "WICED_ENABLE_AUTO_COUNTRY", + "value": null, + "help": "Uncomment to enable Auto country support" + }, + "wiced-enable-mcu-rtc": { + "macro_name": "WICED_ENABLE_MCU_RTC", + "value": null, + "help": "Uncomment to enable MCU real time clock" + }, + "wiced-join-retry-attempts": { + "macro_name": "WICED_JOIN_RETRY_ATTEMPTS", + "value": 3, + "help": "WICED Join Options" + }, + "wiced-network-worker-priority": { + "macro_name": "WICED_NETWORK_WORKER_PRIORITY", + "value": 3, + "help": "Thread priority, 9 is lowest, 0 is highest" + }, + "wiced-ntp-reply-timeout": { + "macro_name": "WICED_NTP_REPLY_TIMEOUT", + "value": 5000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-tcp-accept-timeout": { + "macro_name": "WICED_TCP_ACCEPT_TIMEOUT", + "value": 3000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-tcp-bind-timeout": { + "macro_name": "WICED_TCP_BIND_TIMEOUT", + "value": 3000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-tcp-disconnect-timeout": { + "macro_name": "WICED_TCP_DISCONNECT_TIMEOUT", + "value": 3000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-tcp-send-timeout": { + "macro_name": "WICED_TCP_SEND_TIMEOUT", + "value": 3000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-tcp-window-size": { + "macro_name": "WICED_TCP_WINDOW_SIZE", + "value": "(7 * 1024)", + "help": "WICED TCP Options" + }, + "wiced-tls-default-verification": { + "macro_name": "WICED_TLS_DEFAULT_VERIFICATION", + "value": "TLS_VERIFICATION_REQUIRED", + "help": "WICED TLS Options" + }, + "wiced-tls-max-resumable-sessions": { + "macro_name": "WICED_TLS_MAX_RESUMABLE_SESSIONS", + "value": 4, + "help": "WICED TLS Options" + }, + "wiced-tls-receive-timeout": { + "macro_name": "WICED_TLS_RECEIVE_TIMEOUT", + "value": 5000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-tls-transmit-timeout": { + "macro_name": "WICED_TLS_TRANSMIT_TIMEOUT", + "value": 5000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-udp-bind-timeout": { + "macro_name": "WICED_UDP_BIND_TIMEOUT", + "value": 3000, + "help": "Default WICED networking timeouts in milliseconds" + }, + "wiced-use-ethernet-interface": { + "macro_name": "WICED_USE_ETHERNET_INTERFACE", + "value": null, + "help": "WICED Connectivity Options" + }, + "wiced-use-wifi-ap-interface": { + "macro_name": "WICED_USE_WIFI_AP_INTERFACE", + "value": "", + "help": "WICED Connectivity Options" + }, + "wiced-use-wifi-p": { + "macro_name": "WICED_USE_WIFI_P", + "value": "null2P_INTERFACE", + "help": "WICED Connectivity Options" + }, + "wiced-use-wifi-sta-interface": { + "macro_name": "WICED_USE_WIFI_STA_INTERFACE", + "value": "", + "help": "WICED Connectivity Options" + }, + "wiced-wifi-isolate-ap-clients": { + "macro_name": "WICED_WIFI_ISOLATE_AP_CLIENTS", + "value": null, + "help": "Uncomment to prevent soft AP clients from communicating with each other" + }, + "wiced-wifi-roaming-scan-period-in-seconds": { + "macro_name": "WICED_WIFI_ROAMING_SCAN_PERIOD_IN_SECONDS", + "value": 10, + "help": "WICED WiFi Roaming related options (for STA interface)" + }, + "wiced-wifi-roaming-trigger-delta-in-dbm": { + "macro_name": "WICED_WIFI_ROAMING_TRIGGER_DELTA_IN_DBM", + "value": 5, + "help": "WICED WiFi Roaming related options (for STA interface)" + }, + "wiced-wifi-roaming-trigger-mode": { + "macro_name": "WICED_WIFI_ROAMING_TRIGGER_MODE", + "value": "WICED_WIFI_OPTIMIZE_BANDWIDTH_ROAMING_TRIGGER", + "help": "WICED WiFi Roaming related options (for STA interface)" + }, + "wprint-enable-app-debug": { + "macro_name": "WPRINT_ENABLE_APP_DEBUG", + "value": null, + "help": "Application prints" + }, + "wprint-enable-app-error": { + "macro_name": "WPRINT_ENABLE_APP_ERROR", + "value": null, + "help": "Application prints" + }, + "wprint-enable-app-info": { + "macro_name": "WPRINT_ENABLE_APP_INFO", + "value": null, + "help": "Application prints" + }, + "wprint-enable-lib-debug": { + "macro_name": "WPRINT_ENABLE_LIB_DEBUG", + "value": null, + "help": "General library prints" + }, + "wprint-enable-lib-error": { + "macro_name": "WPRINT_ENABLE_LIB_ERROR", + "value": null, + "help": "General library prints" + }, + "wprint-enable-lib-info": { + "macro_name": "WPRINT_ENABLE_LIB_INFO", + "value": null, + "help": "General library prints" + }, + "wprint-enable-network-debug": { + "macro_name": "WPRINT_ENABLE_NETWORK_DEBUG", + "value": null, + "help": "Network stack prints" + }, + "wprint-enable-network-error": { + "macro_name": "WPRINT_ENABLE_NETWORK_ERROR", + "value": null, + "help": "Network stack prints" + }, + "wprint-enable-network-info": { + "macro_name": "WPRINT_ENABLE_NETWORK_INFO", + "value": null, + "help": "Network stack prints" + }, + "wprint-enable-platform-debug": { + "macro_name": "WPRINT_ENABLE_PLATFORM_DEBUG", + "value": null, + "help": "Platform prints" + }, + "wprint-enable-platform-error": { + "macro_name": "WPRINT_ENABLE_PLATFORM_ERROR", + "value": null, + "help": "Platform prints" + }, + "wprint-enable-platform-info": { + "macro_name": "WPRINT_ENABLE_PLATFORM_INFO", + "value": null, + "help": "Platform prints" + }, + "wprint-enable-rtos-debug": { + "macro_name": "WPRINT_ENABLE_RTOS_DEBUG", + "value": null, + "help": "RTOS prints" + }, + "wprint-enable-rtos-error": { + "macro_name": "WPRINT_ENABLE_RTOS_ERROR", + "value": null, + "help": "RTOS prints" + }, + "wprint-enable-rtos-info": { + "macro_name": "WPRINT_ENABLE_RTOS_INFO", + "value": null, + "help": "RTOS prints" + }, + "wprint-enable-security-debug": { + "macro_name": "WPRINT_ENABLE_SECURITY_DEBUG", + "value": null, + "help": "Security stack prints" + }, + "wprint-enable-security-error": { + "macro_name": "WPRINT_ENABLE_SECURITY_ERROR", + "value": null, + "help": "Security stack prints" + }, + "wprint-enable-security-info": { + "macro_name": "WPRINT_ENABLE_SECURITY_INFO", + "value": null, + "help": "Security stack prints" + }, + "wprint-enable-supplicant-debug": { + "macro_name": "WPRINT_ENABLE_SUPPLICANT_DEBUG", + "value": null, + "help": "Supplicant stack prints" + }, + "wprint-enable-supplicant-error": { + "macro_name": "WPRINT_ENABLE_SUPPLICANT_ERROR", + "value": null, + "help": "Supplicant stack prints" + }, + "wprint-enable-supplicant-info": { + "macro_name": "WPRINT_ENABLE_SUPPLICANT_INFO", + "value": null, + "help": "Supplicant stack prints" + }, + "wprint-enable-webserver-debug": { + "macro_name": "WPRINT_ENABLE_WEBSERVER_DEBUG", + "value": null, + "help": "Webserver prints" + }, + "wprint-enable-webserver-error": { + "macro_name": "WPRINT_ENABLE_WEBSERVER_ERROR", + "value": null, + "help": "Webserver prints" + }, + "wprint-enable-webserver-info": { + "macro_name": "WPRINT_ENABLE_WEBSERVER_INFO", + "value": null, + "help": "Webserver prints" + }, + "wprint-enable-wiced-debug": { + "macro_name": "WPRINT_ENABLE_WICED_DEBUG", + "value": null, + "help": "Wiced internal prints" + }, + "wprint-enable-wiced-error": { + "macro_name": "WPRINT_ENABLE_WICED_ERROR", + "value": null, + "help": "Wiced internal prints" + }, + "wprint-enable-wiced-info": { + "macro_name": "WPRINT_ENABLE_WICED_INFO", + "value": null, + "help": "Wiced internal prints" + }, + "wprint-enable-wps-debug": { + "macro_name": "WPRINT_ENABLE_WPS_DEBUG", + "value": null, + "help": "WPS stack prints" + }, + "wprint-enable-wps-error": { + "macro_name": "WPRINT_ENABLE_WPS_ERROR", + "value": null, + "help": "WPS stack prints" + }, + "wprint-enable-wps-info": { + "macro_name": "WPRINT_ENABLE_WPS_INFO", + "value": null, + "help": "WPS stack prints" + }, + "wprint-enable-wwd-debug": { + "macro_name": "WPRINT_ENABLE_WWD_DEBUG", + "value": null, + "help": "Wiced Wi-Fi Driver prints" + }, + "wprint-enable-wwd-error": { + "macro_name": "WPRINT_ENABLE_WWD_ERROR", + "value": null, + "help": "Wiced Wi-Fi Driver prints" + }, + "wprint-enable-wwd-info": { + "macro_name": "WPRINT_ENABLE_WWD_INFO", + "value": null, + "help": "Wiced Wi-Fi Driver prints" + }, + "wwd-enable-stats": { + "macro_name": "WWD_ENABLE_STATS", + "value": null, + "help": "Enables stats collection in Wi-Fi driver" + }, + "bootloader-magic-number": { + "macro_name": "BOOTLOADER_MAGIC_NUMBER", + "value": "0x4d435242", + "help": "Internally used configuration" + }, + "bus": { + "macro_name": "BUS", + "value": "\"SDIO\"", + "help": "Internally used configuration" + }, + "max-watchdog-timeout-seconds": { + "macro_name": "MAX_WATCHDOG_TIMEOUT_SECONDS", + "value": "22", + "help": "Internally used configuration" + }, + "sflash-apps-header-loc": { + "macro_name": "SFLASH_APPS_HEADER_LOC", + "value": "0x0000", + "help": "Internally used configuration" + }, + "sflash-support-macronix-parts": { + "macro_name": "SFLASH_SUPPORT_MACRONIX_PARTS", + "value": "", + "help": "Internally used configuration" + }, + "stdc-headers": { + "macro_name": "STDC_HEADERS", + "value": "", + "help": "Internally used configuration" + }, + "stm32f412xg": { + "macro_name": "STM32F412xG", + "value": "", + "help": "Internally used configuration" + }, + "sys-time-h-available": { + "macro_name": "SYS_TIME_H_AVAILABLE", + "value": "", + "help": "Internally used configuration" + }, + "use-stdperiph-driver": { + "macro_name": "USE_STDPERIPH_DRIVER", + "value": "", + "help": "Internally used configuration" + }, + "wwd-direct-resources": { + "macro_name": "WWD_DIRECT_RESOURCES", + "value": "", + "help": "Internally used configuration" + }, + "wwd-startup-delay": { + "macro_name": "WWD_STARTUP_DELAY", + "value": 10, + "help": "Internally used configuration" + }, + "wwd-disable-thread-packet-available-check": { + "macro_name": "WWD_DISABLE_THREAD_PACKET_AVAILABLE_CHECK", + "value": "", + "help": "Internally used configuration" + }, + "wwd-disable-sdpcm-padding": { + "macro_name": "WWD_DISABLE_SDPCM_PADDING", + "value": "", + "help": "Internally used configuration" + }, + "sdio-enumeration-timeout-ms": { + "macro_name": "SDIO_ENUMERATION_TIMEOUT_MS", + "value": 2000, + "help": "SDIO enumeration timeout in milliseconds, retries occur every 1 ms" + } + }, + "target_overrides": { + "*": { + "target.features_add": [ + "LWIP" + ] + } + } +} diff --git a/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WICED/w_rtos.h b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WICED/w_rtos.h new file mode 100644 index 00000000000..4e53317b483 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WICED/w_rtos.h @@ -0,0 +1,157 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef W_RTOS_H +#define W_RTOS_H + +#include "wiced_result.h" +#include "wiced_utilities.h" +#include "wwd_rtos.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************** + * Macros + ******************************************************/ + +#define WICED_HARDWARE_IO_WORKER_THREAD ((wiced_worker_thread_t*)&wiced_hardware_io_worker_thread) +#define WICED_NETWORKING_WORKER_THREAD ((wiced_worker_thread_t*)&wiced_networking_worker_thread ) + +#define WICED_PRIORITY_TO_NATIVE_PRIORITY(priority) (2 - ((int8_t)priority / 2)) +#define WICED_END_OF_THREAD(thread) malloc_leak_check( &(thread).handle, LEAK_CHECK_THREAD); (void)(thread) +#define WICED_END_OF_CURRENT_THREAD( ) malloc_leak_check( NULL, LEAK_CHECK_THREAD) +#define WICED_END_OF_CURRENT_THREAD_NO_LEAK_CHECK( ) + +#define WICED_TO_MALLOC_THREAD( x ) ((malloc_thread_handle) &((x)->handle )) + +#define WICED_GET_THREAD_HANDLE( thread ) (&(( thread )->handle )) + +#define WICED_GET_QUEUE_HANDLE( queue ) (&(( queue )->handle )) + +/****************************************************** + * Constants + ******************************************************/ + +/* Configuration of Built-in Worker Threads + * + * 1. wiced_hardware_io_worker_thread is designed to handle deferred execution of quick, non-blocking hardware I/O operations. + * - priority : higher than that of wiced_networking_worker_thread + * - stack size : small. Consequently, no printf is allowed here. + * - event queue size : the events are quick; therefore, large queue isn't required. + * + * 2. wiced_networking_worker_thread is designed to handle deferred execution of networking operations + * - priority : lower to allow wiced_hardware_io_worker_thread to preempt and run + * - stack size : considerably larger than that of wiced_hardware_io_worker_thread because of the networking functions. + * - event queue size : larger than that of wiced_hardware_io_worker_thread because networking operation may block + */ +#ifndef HARDWARE_IO_WORKER_THREAD_STACK_SIZE +#ifdef DEBUG +#define HARDWARE_IO_WORKER_THREAD_STACK_SIZE (768) /* debug builds can use larger stack for example because of compiled-in asserts, switched off optimisation, etc */ +#else +#define HARDWARE_IO_WORKER_THREAD_STACK_SIZE (512) +#endif +#endif +#define HARDWARE_IO_WORKER_THREAD_QUEUE_SIZE (10) + +#ifndef NETWORKING_WORKER_THREAD_STACK_SIZE +#define NETWORKING_WORKER_THREAD_STACK_SIZE (6*1024) +#endif +#define NETWORKING_WORKER_THREAD_QUEUE_SIZE (15) + +#ifndef TIMER_WORKER_THREAD_STACK_SIZE +#define TIMER_WORKER_THREAD_STACK_SIZE (1024) +#endif + +#ifndef TIMER_WORKER_THREAD_QUEUE_SIZE +#define TIMER_WORKER_THREAD_QUEUE_SIZE (20) +#endif + +#define RTOS_NAME "mbed" +#define RTOS_VERSION "???" + +/****************************************************** + * Enumerations + ******************************************************/ + +/****************************************************** + * Type Definitions + ******************************************************/ + +typedef struct { unsigned buffer[16]; } wiced_event_flags_t; + +typedef host_semaphore_type_t wiced_semaphore_t; + +typedef struct { unsigned buffer[16]; } wiced_mutex_t; + +typedef void (*timer_handler_t)( void* arg ); + +/****************************************************** + * Structures + ******************************************************/ + +typedef struct +{ + host_thread_type_t handle; + void* stack; +} wiced_thread_t; + +typedef struct +{ + host_queue_type_t handle; + void* buffer; +} wiced_queue_t; + +typedef struct +{ + wiced_thread_t thread; + wiced_queue_t event_queue; +} wiced_worker_thread_t; + +typedef wiced_result_t (*event_handler_t)( void* arg ); + +typedef struct +{ + int id; + uint32_t time_ms; + timer_handler_t function; + void* arg; +} wiced_timer_t; + +typedef struct +{ + event_handler_t function; + void* arg; + wiced_timer_t timer; + wiced_worker_thread_t* thread; +} wiced_timed_event_t; + +/****************************************************** + * Global Variables + ******************************************************/ + +extern wiced_worker_thread_t wiced_hardware_io_worker_thread; +extern wiced_worker_thread_t wiced_networking_worker_thread; + +/****************************************************** + * Function Declarations + ******************************************************/ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WICED/wiced_rtos.cpp b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WICED/wiced_rtos.cpp new file mode 100644 index 00000000000..7df1819eb80 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WICED/wiced_rtos.cpp @@ -0,0 +1,584 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_result.h" +#include "wiced_utilities.h" +#include "wiced_rtos.h" +#include "wiced_time.h" +#include "wwd_rtos.h" +#include "mbed.h" + + +// worker threads defined here +wiced_worker_thread_t wiced_hardware_io_worker_thread; +wiced_worker_thread_t wiced_networking_worker_thread; + + +/** Creates and starts a new thread + * + * Creates and starts a new thread + * + * @param[out] thread : Pointer to variable that will receive the thread handle + * @param[in] priority : A priority number or WICED_DEFAULT_APP_THREAD_PRIORITY. + * @param[in] name : A text name for the thread (can be null) + * @param[in] function : The main thread function + * @param[in] stack_size : Stack size for this thread + * @param[in] arg : Argument which will be passed to thread function + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_create_thread( + wiced_thread_t *thread, + uint8_t priority, + const char *name, + wiced_thread_function_t function, + uint32_t stack_size, + void *arg) +{ + thread->stack = malloc(stack_size); + if (thread->stack == NULL) { + return WICED_OUT_OF_HEAP_SPACE; + } + + wiced_result_t result = wiced_rtos_create_thread_with_stack( + thread, + priority, + name, + function, + thread->stack, + stack_size, + arg); + + if (result != WICED_WWD_SUCCESS) { + free(thread->stack); + thread->stack = NULL; + } + + return (wiced_result_t)result; +} + + +/** Creates and starts a new thread with user provided stack + * + * Creates and starts a new thread with user provided stack + * + * @param[out] thread : Pointer to variable that will receive the thread handle + * @param[in] priority : A priority number or WICED_DEFAULT_APP_THREAD_PRIORITY. + * @param[in] name : A text name for the thread (can be null) + * @param[in] function : The main thread function + * @param[in] stack : The stack for this thread + * @param[in] stack_size : Stack size for this thread + * @param[in] arg : Argument which will be passed to thread function + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_create_thread_with_stack( + wiced_thread_t *thread, + uint8_t priority, + const char *name, + wiced_thread_function_t function, + void *stack, + uint32_t stack_size, + void *arg) +{ + int8_t native_priority = WICED_PRIORITY_TO_NATIVE_PRIORITY(priority); + + memset(stack, 0, stack_size); + + return (wiced_result_t)host_rtos_create_thread_with_arg( + WICED_GET_THREAD_HANDLE(thread), + function, + name, + thread->stack, + stack_size, + native_priority, + (wiced_thread_arg_t)arg); +} + + +/** Deletes a terminated thread + * + * @param[in] thread : The handle of the thread to delete + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_delete_thread(wiced_thread_t *thread) +{ + wiced_result_t result = (wiced_result_t)host_rtos_finish_thread( + WICED_GET_THREAD_HANDLE(thread)); + if (result != WICED_WWD_SUCCESS) { + return result; + } + + result = (wiced_result_t)host_rtos_delete_terminated_thread( + WICED_GET_THREAD_HANDLE(thread)); + if (result != WICED_WWD_SUCCESS) { + return result; + } + + if (thread->stack != NULL) { + free(thread->stack); + thread->stack = NULL; + } + + return result; +} + +/** Forcibly wakes another thread + * + * Causes the specified thread to wake from suspension. This will usually + * cause an error or timeout in that thread, since the task it was waiting on + * is not complete. + * + * @param[in] thread : The handle of the other thread which will be woken + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_thread_force_awake(wiced_thread_t *t) +{ + // TODO this is probably not correct + Thread *thread = reinterpret_cast(&t->handle); + osStatus err = thread->terminate(); + return (err == osOK) ? WICED_SUCCESS : WICED_ERROR; +} + + +/** Checks if a thread is the current thread + * + * Checks if a specified thread is the currently running thread + * + * @param[in] thread : The handle of the other thread against which the current thread will be compared + * + * @return WICED_SUCCESS : specified thread is the current thread + * @return WICED_ERROR : specified thread is not currently running + */ +extern "C" wiced_result_t wiced_rtos_is_current_thread(wiced_thread_t *thread); + // not supported, force linking error + + +/** Checks the stack of the current thread + * + * @return WICED_SUCCESS : if the current thread stack is within limits + * @return WICED_ERROR : if the current thread stack has extended beyond its limits + */ +extern "C" wiced_result_t wiced_rtos_check_stack(void) +{ + // do nothing, stack checking in rtos + return WICED_SUCCESS; +} + +/** @} */ +/*****************************************************************************/ +/** @addtogroup mutexes Mutexes + * @ingroup rtos + * + * Mutex management functionss + * + * + * @{ + */ +/*****************************************************************************/ + +/** Initialises a mutex + * + * Initialises a mutex + * A mutex is different to a semaphore in that a thread that already holds + * the lock on the mutex can request the lock again (nested) without causing + * it to be suspended. + * + * @param[in] mutex : A pointer to the mutex handle to be initialised + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_init_mutex(wiced_mutex_t *p) +{ + MBED_STATIC_ASSERT(sizeof(wiced_mutex_t) >= sizeof(Mutex), + "wiced_mutex_t must fit Mutex type"); + new (p) Mutex; + return WICED_WWD_SUCCESS; +} + + +/** Obtains the lock on a mutex + * + * Attempts to obtain the lock on a mutex. If the lock is already held + * by another thead, the calling thread will be suspended until + * the mutex lock is released by the other thread. + * + * @param[in] mutex : A pointer to the mutex handle to be locked + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_lock_mutex(wiced_mutex_t *p) +{ + Mutex *mutex = reinterpret_cast(p); + mutex->lock(); + return WICED_WWD_SUCCESS; +} + + +/** Releases the lock on a mutex + * + * Releases a currently held lock on a mutex. If another thread + * is waiting on the mutex lock, then it will be resumed. + * + * @param[in] mutex : A pointer to the mutex handle to be unlocked + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_unlock_mutex(wiced_mutex_t *p) +{ + Mutex *mutex = reinterpret_cast(p); + mutex->unlock(); + return WICED_WWD_SUCCESS; +} + + +/** De-initialise a mutex + * + * Deletes a mutex created with @ref wiced_rtos_init_mutex + * + * @param[in] mutex : A pointer to the mutex handle + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_deinit_mutex(wiced_mutex_t *p) +{ + Mutex *mutex = reinterpret_cast(p); + mutex->~Mutex(); + return WICED_WWD_SUCCESS; +} + + +/** @} */ +/*****************************************************************************/ +/** @addtogroup queues Queues + * @ingroup rtos + * + * Queue management functionss + * + * + * @{ + */ +/*****************************************************************************/ + +/** Initialises a queue + * + * Initialises a FIFO queue + * + * @param[in] queue : A pointer to the queue handle to be initialised + * @param[in] name : A text string name for the queue (NULL is allowed) + * @param[in] message_size : Size in bytes of objects that will be held in the queue + * @param[in] number_of_messages : Depth of the queue - i.e. max number of objects in the queue + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_init_queue(wiced_queue_t *queue, const char *name, uint32_t message_size, uint32_t number_of_messages) +{ + size_t buffer_size = (sizeof(mbed_rtos_storage_msg_queue_t) + + number_of_messages*(sizeof(mbed_rtos_storage_message_t) + message_size)); + queue->buffer = malloc(buffer_size); + if (!queue->buffer) { + return WICED_OUT_OF_HEAP_SPACE; + } + + wiced_result_t result = (wiced_result_t)host_rtos_init_queue( + WICED_GET_QUEUE_HANDLE(queue), + queue->buffer, + buffer_size, + message_size); + + if (result != WICED_WWD_SUCCESS) { + free(queue->buffer); + queue->buffer = NULL; + } + + return result; +} + + +/** De-initialise a queue + * + * Deletes a queue created with @ref wiced_rtos_init_queue + * + * @param[in] queue : A pointer to the queue handle + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_deinit_queue(wiced_queue_t *queue) +{ + wiced_result_t result = (wiced_result_t)host_rtos_deinit_queue( + WICED_GET_QUEUE_HANDLE(queue)); + if (result != WICED_WWD_SUCCESS) { + return result; + } + + if (queue->buffer != NULL) { + free(queue->buffer); + queue->buffer = NULL; + } + + return result; +} + + +/** Check if a queue is empty + * + * @param[in] queue : A pointer to the queue handle + * + * @return WICED_SUCCESS : queue is empty. + * @return WICED_ERROR : queue is not empty. + */ +extern "C" wiced_result_t wiced_rtos_is_queue_empty(wiced_queue_t *queue); + // not supported, force linking error + + +/** Check if a queue is full + * + * @param[in] queue : A pointer to the queue handle + * + * @return WICED_SUCCESS : queue is full. + * @return WICED_ERROR : queue is not full. + */ +extern "C" wiced_result_t wiced_rtos_is_queue_full(wiced_queue_t *queue); + // not supported, force linking error + + +/** Get the queue occupancy + * + * @param[in] queue : A pointer to the queue handle + * @param[out] count : Pointer to integer for storing occupancy count + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_get_queue_occupancy(wiced_queue_t *queue, uint32_t *count); + // not supported, force linking error + + +/** @} */ +/*****************************************************************************/ +/** @addtogroup rtostmr RTOS timers + * @ingroup rtos + * + * RTOS timer management functions + * These timers are based on the RTOS time-slice scheduling, so are not + * highly accurate. They are also affected by high loading on the processor. + * + * + * @{ + */ +/*****************************************************************************/ + +static void timer_thread_main(uint32_t p) { + reinterpret_cast(p)->dispatch(); +} + +static EventQueue *timer_event_queue() { + static bool timer_thread_initialized = false; + static EventQueue timer_event_queue(TIMER_WORKER_THREAD_QUEUE_SIZE); + static wiced_thread_t timer_thread; + + if (!timer_thread_initialized) { + wiced_result_t result = wiced_rtos_create_thread( + &timer_thread, + osPriorityHigh, + "timer queue", + timer_thread_main, + TIMER_WORKER_THREAD_STACK_SIZE, + (void*)&timer_event_queue); + + MBED_ASSERT(result == WICED_SUCCESS); + timer_thread_initialized = true; + } + + return &timer_event_queue; +} + +/** Initialises a RTOS timer + * + * Initialises a RTOS timer + * Timer does not start running until @ref wiced_rtos_start_timer is called + * + * @param[in] timer : A pointer to the timer handle to be initialised + * @param[in] time_ms : Timer period in milliseconds + * @param[in] function : The callback handler function that is called each + * time the timer expires + * @param[in] arg : An argument that will be passed to the callback + * function + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_init_timer(wiced_timer_t *timer, uint32_t time_ms, timer_handler_t function, void *arg) +{ + // make sure event queue has been initialized + timer_event_queue(); + + timer->id = -1; + timer->time_ms = time_ms; + timer->function = function; + timer->arg = arg; + + return WICED_SUCCESS; +} + + +/** Starts a RTOS timer running + * + * Starts a RTOS timer running. Timer must have been previously + * initialised with @ref wiced_rtos_init_timer + * + * @param[in] timer : A pointer to the timer handle to start + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_start_timer(wiced_timer_t *timer) +{ + timer->id = timer_event_queue()->call_in(timer->time_ms, timer->function, timer->arg); + return timer->id ? WICED_SUCCESS : WICED_ERROR; +} + + +/** Stops a running RTOS timer + * + * Stops a running RTOS timer. Timer must have been previously + * started with @ref wiced_rtos_start_timer + * + * @param[in] timer : A pointer to the timer handle to stop + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_stop_timer(wiced_timer_t *timer) +{ + timer_event_queue()->cancel(timer->id); + return WICED_SUCCESS; +} + + +/** De-initialise a RTOS timer + * + * Deletes a RTOS timer created with @ref wiced_rtos_init_timer + * + * @param[in] timer : A pointer to the RTOS timer handle + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_deinit_timer(wiced_timer_t *timer) +{ + wiced_rtos_stop_timer(timer); + return WICED_SUCCESS; +} + + +/** Check if an RTOS timer is running + * + * @param[in] timer : A pointer to the RTOS timer handle + * + * @return WICED_SUCCESS : if running. + * @return WICED_ERROR : if not running + */ +extern "C" wiced_result_t wiced_rtos_is_timer_running(wiced_timer_t *timer); + // not supported, force linking error (racey) + +/** Get the current system tick time in milliseconds + * + * @note The time will roll over every 49.7 days + * + * @param[out] time : A pointer to the variable which will receive the time value + * + * @return @ref wiced_result_t + */ +wiced_result_t wiced_time_get_time(wiced_time_t *time) +{ + *time = timer_event_queue()->tick(); + return WICED_SUCCESS; +} + +/** @} */ +/*****************************************************************************/ +/** @addtogroup eventflags Event Flags + * @ingroup rtos + * + * Event flags management functions + * + * + * @{ + */ +/*****************************************************************************/ + +/** Initialise an event flags + * + * @param[in] event_flags : A pointer to the event flags handle +S * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_init_event_flags(wiced_event_flags_t *event_flags); + // not supported, force linking error + +/** Wait for event flags to be set + * + * @param[in] event_flags : Pointer to the event flags handle + * @param[in] flags_to_wait_for : Group of event flags (ORed bit-fields) to wait for + * @param[out] flags_set : Event flag(s) set + * @param[in] clear_set_flags : TRUE to clear set flag, FALSE leaves flags unchanged. + * @param[in] wait_option : Wait option + * @param[in] timeout_ms : Timeout in milliseconds + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_wait_for_event_flags(wiced_event_flags_t *event_flags, uint32_t flags_to_wait_for, uint32_t *flags_set, wiced_bool_t clear_set_flags, wiced_event_flags_wait_option_t wait_option, uint32_t timeout_ms); + // not supported, force linking error + + +/** Set event flags + * + * @param[in] event_flags : Pointer to the event flags handle + * @param[in] flags_to_set : Group of event flags (ORed bit-fields) to set + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_set_event_flags(wiced_event_flags_t *event_flags, uint32_t flags_to_set); + // not supported, force linking error + + +/** De-initialise an event flags + * + * @param[in] event_flags : Pointer to the event flags handle + * + * @return WICED_SUCCESS : on success. + * @return WICED_ERROR : if an error occurred + */ +extern "C" wiced_result_t wiced_rtos_deinit_event_flags(wiced_event_flags_t *event_flags); + // not supported, force linking error + +/** @} */ + diff --git a/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos.cpp b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos.cpp new file mode 100644 index 00000000000..697041a3175 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos.cpp @@ -0,0 +1,200 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wwd_rtos.h" +#include "wwd_constants.h" +#include "wwd_assert.h" +#include "wwd_rtos_interface.h" +#include "wiced_utilities.h" +#include "rtos.h" +#include "ticker_api.h" + + +extern "C" wwd_result_t host_rtos_create_thread( + host_thread_type_t *p, + void (*entry_function)(uint32_t), + const char *name, void *stack, + uint32_t stack_size, + uint32_t priority) +{ + return host_rtos_create_thread_with_arg( + p, entry_function, name, stack, stack_size, priority, 0); +} + +extern "C" wwd_result_t host_rtos_create_thread_with_arg( + host_thread_type_t *p, + void (*entry_function)(uint32_t), + const char *name, + void *stack, + uint32_t stack_size, + uint32_t priority, + uint32_t arg) +{ + MBED_STATIC_ASSERT(sizeof(host_thread_type_t) >= sizeof(Thread), + "host_thread_type_t must fit Thread type"); + Thread *thread = new (p) Thread(osPriorityNormal, + stack_size, (unsigned char*)stack); + int err = thread->start(callback( + reinterpret_cast(entry_function), + reinterpret_cast(arg))); + + return (!err) ? WWD_SUCCESS : WWD_THREAD_CREATE_FAILED; +} + +extern "C" wwd_result_t host_rtos_create_configed_thread( + host_thread_type_t *p, + void (*entry_function)(uint32_t), + const char *name, + void *stack, + uint32_t stack_size, + uint32_t priority, + host_rtos_thread_config_type_t *config) +{ + return host_rtos_create_thread( + p, entry_function, name, stack, stack_size, priority); +} + +extern "C" wwd_result_t host_rtos_finish_thread(host_thread_type_t *p) +{ + // NOP: Return from thread terminates thread + return WWD_SUCCESS; +} + +extern "C" wwd_result_t host_rtos_join_thread(host_thread_type_t *p) +{ + Thread *thread = reinterpret_cast(p); + int err = thread->join(); + return (!err) ? WWD_SUCCESS : WWD_THREAD_CREATE_FAILED; +} + +extern "C" wwd_result_t host_rtos_delete_terminated_thread(host_thread_type_t *p) +{ + Thread *thread = reinterpret_cast(p); + thread->~Thread(); + return WWD_SUCCESS; +} + +extern "C" wwd_result_t host_rtos_init_semaphore( + host_semaphore_type_t *p) +{ + MBED_STATIC_ASSERT(sizeof(host_semaphore_type_t) >= sizeof(Semaphore), + "host_semaphore_type_t must fit Semaphore type"); + new (p) Semaphore; + return WWD_SUCCESS; +} + +extern "C" wwd_result_t host_rtos_get_semaphore( + host_semaphore_type_t *p, + uint32_t timeout_ms, + wiced_bool_t will_set_in_isr) +{ + if (timeout_ms == NEVER_TIMEOUT) { + timeout_ms = osWaitForever; + } + + Semaphore *sema = reinterpret_cast(p); + int32_t res = sema->wait(timeout_ms); + return (res >= 1) ? WWD_SUCCESS : WWD_TIMEOUT; +} + +extern "C" wwd_result_t host_rtos_set_semaphore( + host_semaphore_type_t *p, + wiced_bool_t called_from_ISR) +{ + Semaphore *sema = reinterpret_cast(p); + sema->release(); + return WWD_SUCCESS; +} + +extern "C" wwd_result_t host_rtos_deinit_semaphore( + host_semaphore_type_t *p) +{ + Semaphore *sema = reinterpret_cast(p); + sema->~Semaphore(); + return WWD_SUCCESS; +} + +extern "C" wwd_time_t host_rtos_get_time(void) +{ +// TODO +// const ticker_data_t *ticker = get_us_ticker_data(); +// us_timestamp_t timestamp = ticker_read_us(ticker); +// return (wwd_time_t)(timestamp / 1000); + return us_ticker_read() / 1000; +} + +extern "C" wwd_result_t host_rtos_delay_milliseconds(uint32_t num_ms) +{ + wait_ms(num_ms); + return WWD_SUCCESS; +} + +// We have to implement a direct layer to the cmsis queue since the +// mbed APIs lack a dynamic queue +#define HOST_QUEUE_OVERHEAD (10*sizeof(uint32_t)) +struct host_queue { + osMessageQueueId_t id; + osMessageQueueAttr_t attr; +}; + +extern "C" wwd_result_t host_rtos_init_queue(host_queue_type_t *p, void *buffer, uint32_t buffer_size, uint32_t message_size) +{ + MBED_STATIC_ASSERT(sizeof(host_queue_type_t) >= sizeof(struct host_queue), + "host_queue_type_t must fit Queue type"); + MBED_ASSERT(buffer_size > HOST_QUEUE_OVERHEAD); + + // cmsis queue needs pointer overhead for each message, + // we need to recalculate real queue size + uint32_t real_message_size = sizeof(mbed_rtos_storage_message_t) + message_size; + uint32_t real_queue_size = (buffer_size - sizeof(mbed_rtos_storage_msg_queue_t)) / real_message_size; + struct host_queue *q = reinterpret_cast(p); + memset(buffer, 0, buffer_size); + + q->attr.cb_mem = &((uint8_t*)buffer)[0]; + q->attr.cb_size = sizeof(mbed_rtos_storage_msg_queue_t); + q->attr.mq_mem = &((uint8_t*)buffer)[sizeof(mbed_rtos_storage_msg_queue_t)]; + q->attr.mq_size = buffer_size - sizeof(mbed_rtos_storage_msg_queue_t); + + q->id = osMessageQueueNew(real_queue_size, message_size, &q->attr); + if (q->id == NULL) { + error("Error initialising the queue object\n"); + } + + return WWD_SUCCESS; +} + +extern "C" wwd_result_t host_rtos_push_to_queue(host_queue_type_t *p, void *m, uint32_t timeout_ms) +{ + struct host_queue *q = reinterpret_cast(p); + osStatus_t err = osMessageQueuePut(q->id, m, 0, timeout_ms); + MBED_ASSERT(err == osOK || err == osErrorTimeout); + return err == osOK ? WWD_SUCCESS : WWD_TIMEOUT; +} + +extern "C" wwd_result_t host_rtos_pop_from_queue(host_queue_type_t *p, void *m, uint32_t timeout_ms) +{ + + struct host_queue *q = reinterpret_cast(p); + + osStatus_t err = osMessageQueueGet(q->id, m, 0, timeout_ms); + MBED_ASSERT(err == osOK || err == osErrorTimeout); + return err == osOK ? WWD_SUCCESS : WWD_TIMEOUT; +} + +extern "C" wwd_result_t host_rtos_deinit_queue(host_queue_type_t *p) +{ + // do nothing + return WWD_SUCCESS; +} diff --git a/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos.h b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos.h new file mode 100644 index 00000000000..3aeeb8b525a --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef W_WWD_RTOS_H +#define W_WWD_RTOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "cmsis_os.h" + +#define RTOS_HIGHER_PRIORTIY_THAN(x) (x < osPriorityHigh ? x+1 : osPriorityHigh) +#define RTOS_LOWER_PRIORTIY_THAN(x) (x > osPriorityLow ? x-1 : osPriorityLow) +#define RTOS_LOWEST_PRIORITY (osPriorityLow) +#define RTOS_HIGHEST_PRIORITY (osPriorityHigh) +#define RTOS_DEFAULT_THREAD_PRIORITY (osPriorityNormal) + +#define RTOS_USE_DYNAMIC_THREAD_STACK + +#ifndef WWD_LOGGING_STDOUT_ENABLE +#ifdef DEBUG +#define WWD_THREAD_STACK_SIZE (732 + 1400) /* Stack checking requires a larger stack */ +#else /* ifdef DEBUG */ +#define WWD_THREAD_STACK_SIZE (544 + 1400) +#endif /* ifdef DEBUG */ +#else /* if WWD_LOGGING_STDOUT_ENABLE */ +#define WWD_THREAD_STACK_SIZE (544 + 4096 + 1400) /* WWD_LOG uses printf and requires a minimum of 4K stack */ +#endif /* WWD_LOGGING_STDOUT_ENABLE */ + +typedef struct { unsigned buffer[64]; } host_thread_type_t; /** definition of a thread handle */ +typedef struct { unsigned buffer[16]; } host_semaphore_type_t; /** definition of a semaphore */ +typedef struct { unsigned buffer[16]; } host_queue_type_t; /** definition of a message queue */ + +typedef struct +{ + unsigned char info; /* not supported yet */ +} host_rtos_thread_config_type_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* ifndef INCLUDED_WWD_RTOS_H_ */ diff --git a/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos_isr.h b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos_isr.h new file mode 100644 index 00000000000..0f92a050571 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/RTOS/mbed/WWD/wwd_rtos_isr.h @@ -0,0 +1,109 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef W_WWD_RTOS_ISR_H +#define W_WWD_RTOS_ISR_H + +#include "w_platform_isr.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************** + * Macros + ******************************************************/ + +/* Use this macro to define an RTOS-aware interrupt handler where RTOS + * primitives can be safely accessed. + * Current port has no vectored interrupt controller, so single entry point + * to all interrupts is used. And this entry is wrapped with RTOS-aware code, + * so all interrupts are actually RTOS-aware. + * + * @usage: + * WWD_RTOS_DEFINE_ISR( my_irq_handler ) + * { + * // Do something here + * } + */ +#define WWD_RTOS_DEFINE_ISR( function ) PLATFORM_DEFINE_ISR( function ) + +/* Macro for mapping a function defined using WWD_RTOS_DEFINE_ISR + * to an interrupt handler declared in + * /WICED/platform/MCU//platform_isr_interface.h + * + * @usage: + * WWD_RTOS_MAP_ISR( my_IRQHandler, USART1_IRQHandler ) + */ +#define WWD_RTOS_MAP_ISR( function, isr ) PLATFORM_MAP_ISR( function, isr ) + +/* Use this macro to define function which serves as ISR demuxer. + * It is used when no vectored interrupt controller, and single + * vector triggered for all interrupts. + * + * @usage: + * WWD_RTOS_DEFINE_ISR_DEMUXER( my_irq_handler ) + * { + * // Do something here + * } + */ +#define WWD_RTOS_DEFINE_ISR_DEMUXER( function ) PLATFORM_DEFINE_ISR( function ) + +/* Macro to declare that function is ISR demuxer. + * Function has to be defined via WWD_RTOS_DEFINE_ISR_DEMUXER + * + * @usage: + * WWD_RTOS_MAP_ISR_DEMUXER( my_irq_demuxer ) + */ +#define WWD_RTOS_MAP_ISR_DEMUXER( function ) PLATFORM_MAP_ISR( function, ) + +/****************************************************** + * Constants + ******************************************************/ + +/* Define interrupt handlers. These defines are used by the vector table. */ +// mbed handles isrs seperately, these are just to create linking errors if +// get pulled in somewhere +extern void __null_isr( void ); +#define SVC_IRQHandler __null_isr +#define PENDSV_IRQHandler __null_isr +#define SYSTICK_IRQHandler __null_isr + +/****************************************************** + * Enumerations + ******************************************************/ + +/****************************************************** + * Type Definitions + ******************************************************/ + +/****************************************************** + * Structures + ******************************************************/ + +/****************************************************** + * Global Variables + ******************************************************/ + +/****************************************************** + * Function Declarations + ******************************************************/ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wiced_network.h b/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wiced_network.h new file mode 100644 index 00000000000..c9a3857be18 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wiced_network.h @@ -0,0 +1,142 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef WICED_NETWORK_H +#define WICED_NETWORK_H +#include "w_tls_types.h" +#include "w_dtls_types.h" +#include "wiced_result.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** + * Macros + ******************************************************/ + +#define IP_HANDLE(interface) (wiced_ip_handle[(interface) & 3]) + +/****************************************************** + * Constants + ******************************************************/ + +#define WICED_MAXIMUM_NUMBER_OF_SOCKETS_WITH_CALLBACKS (1) +#define WICED_MAXIMUM_NUMBER_OF_SERVER_SOCKETS (1) + +#define SIZE_OF_ARP_ENTRY sizeof(1) + +#define IP_STACK_SIZE (2 * 1024) +#define ARP_CACHE_SIZE (6 * SIZE_OF_ARP_ENTRY) +#define DHCP_STACK_SIZE (1024) + +#define WICED_ANY_PORT (0) + +/****************************************************** + * Enumerations + ******************************************************/ + +typedef enum +{ + WICED_SOCKET_ERROR +} wiced_socket_state_t; + +/****************************************************** + * Type Definitions + ******************************************************/ +typedef struct +{ + int dummy; +}NOOS_DUMMY; +typedef NOOS_DUMMY wiced_packet_t; + +//typedef NOOS_DUMMY wiced_tls_context_type_t; +//typedef NOOS_DUMMY wiced_tls_context_t; +//typedef NOOS_DUMMY wiced_tls_session_t; +//typedef NOOS_DUMMY wiced_tls_certificate_t; +//typedef NOOS_DUMMY wiced_tls_endpoint_type_t; +typedef NOOS_DUMMY NOOS_TCP_SOCKET; + +/****************************************************** + * Structures + ******************************************************/ + +typedef struct wiced_tcp_socket_struct wiced_tcp_socket_t; +typedef struct wiced_udp_socket_struct wiced_udp_socket_t; + +typedef wiced_result_t (*wiced_tcp_socket_callback_t)( wiced_tcp_socket_t* socket, void* arg ); +typedef wiced_result_t (*wiced_udp_socket_callback_t)( wiced_udp_socket_t* socket, void* arg ); + +struct wiced_udp_socket_struct +{ + wiced_dtls_context_t* dtls_context; + struct + { + wiced_tcp_socket_callback_t disconnect; + wiced_tcp_socket_callback_t receive; + wiced_tcp_socket_callback_t connect; + } callbacks; + void* callback_arg; +}; + +struct wiced_tcp_socket_struct +{ + NOOS_TCP_SOCKET socket; + wiced_tls_context_t* tls_context; + wiced_bool_t context_malloced; + struct + { + wiced_tcp_socket_callback_t disconnect; + wiced_tcp_socket_callback_t receive; + wiced_tcp_socket_callback_t connect; + } callbacks; + void* callback_arg; +}; + +typedef struct +{ + wiced_tcp_socket_t socket[WICED_MAXIMUM_NUMBER_OF_SERVER_SOCKETS]; + int interface; + uint16_t port; + wiced_tls_identity_t* tls_identity; +} wiced_tcp_server_t; + +/****************************************************** + * Global Variables + ******************************************************/ +typedef struct +{ + int dummy; +}NOOS_IP; +typedef struct +{ + int dummy; +}NOOS_PACKET_POOL; +/* + * Note: These objects are for internal use only! + */ +extern NOOS_IP wiced_ip_handle [3]; +extern NOOS_PACKET_POOL wiced_packet_pools [2]; /* 0=TX, 1=RX */ + +/****************************************************** + * Function Declarations + ******************************************************/ + + +#ifdef __cplusplus +} /*extern "C" */ +#endif +#endif diff --git a/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wwd_buffer.c b/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wwd_buffer.c new file mode 100644 index 00000000000..8fd45385172 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wwd_buffer.c @@ -0,0 +1,95 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include +#include "wwd_buffer.h" +#include "wwd_constants.h" +#include "wwd_assert.h" +#include "network/wwd_buffer_interface.h" +#include "mbed_critical.h" + +wwd_result_t host_buffer_check_leaked(void) +{ + /* Nothing to do */ + return WWD_SUCCESS; +} + +wwd_result_t internal_host_buffer_get(wiced_buffer_t * buffer, wwd_buffer_dir_t direction, unsigned short size, unsigned long timeout_ms) +{ + assert(core_util_are_interrupts_enabled()); + void *p = malloc(sizeof(wiced_buffer_impl_t)); + if (!p) { + return WWD_BUFFER_UNAVAILABLE_PERMANENT; + } + *buffer = p; + + p = malloc(size); + if (!p) { + free(p); + return WWD_BUFFER_UNAVAILABLE_PERMANENT; + } + (*buffer)->ptr = p; + + (*buffer)->size = size; + (*buffer)->offset = 0; + return WWD_SUCCESS; +} + +wwd_result_t host_buffer_get(/*@out@*/ wiced_buffer_t * buffer, wwd_buffer_dir_t direction, unsigned short size, wiced_bool_t wait) +{ + return internal_host_buffer_get(buffer, direction, size, wait); +} + +void host_buffer_release(wiced_buffer_t buffer, wwd_buffer_dir_t direction ) +{ + assert(buffer != NULL); + assert(core_util_are_interrupts_enabled()); + free(buffer->ptr); // bug here + free(buffer); +} + +uint8_t* host_buffer_get_current_piece_data_pointer(wiced_buffer_t buffer ) +{ + return &buffer->ptr[buffer->offset]; +} + +uint16_t host_buffer_get_current_piece_size(wiced_buffer_t buffer) +{ + UNUSED_PARAMETER(buffer); + return buffer->size; +} + +wiced_buffer_t host_buffer_get_next_piece(wiced_buffer_t buffer) +{ + UNUSED_PARAMETER(buffer); + return NULL; +} + +wwd_result_t host_buffer_add_remove_at_front(wiced_buffer_t * buffer, int32_t add_remove_amount) +{ + assert((*buffer)->offset >= -add_remove_amount); + (*buffer)->offset += add_remove_amount; + (*buffer)->size -= add_remove_amount; + return WWD_SUCCESS; +} + +wwd_result_t host_buffer_set_size(wiced_buffer_t buffer, unsigned short size) +{ + buffer->size = size; + return WWD_SUCCESS; +} diff --git a/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wwd_buffer.h b/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wwd_buffer.h new file mode 100644 index 00000000000..7f0642d8406 --- /dev/null +++ b/targets/TARGET_WICED/wiced_port/WICED/network/mbed/WWD/wwd_buffer.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef INCLUDED_WWD_BUFFER_H_ +#define INCLUDED_WWD_BUFFER_H_ + + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** + * Constants + ******************************************************/ + +/****************************************************** + * Structures + ******************************************************/ + +typedef struct +{ + uint16_t size; + uint16_t offset; + uint8_t *ptr; +} wiced_buffer_impl_t; + +typedef wiced_buffer_impl_t *wiced_buffer_t; + +typedef void wiced_buffer_fifo_t; + +/****************************************************** + * Function declarations + ******************************************************/ + +/****************************************************** + * Global variables + ******************************************************/ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* ifndef INCLUDED_WWD_BUFFER_H_ */ diff --git a/targets/targets.json b/targets/targets.json index fa6b0ddff93..9935b1b0fd1 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1118,6 +1118,21 @@ } } }, + "WISE1530_F412RE": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM", "STM32F4", "Advantech_F412RE", "CORDIO"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"], + "release_versions": ["5"], + "device_name": "STM32F412RE" + }, "DISCO_F413ZH": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"],